git.sur5r.net Git - openocd/blob - src/flash/stm32x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "replacements.h"
  28
  29 #include "stm32x.h"
  30 #include "flash.h"
  31 #include "target.h"
  32 #include "log.h"
  33 #include "armv7m.h"
  34 #include "algorithm.h"
  35 #include "binarybuffer.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39
  40 int stm32x_register_commands(struct command_context_s *cmd_ctx);
  41 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  42 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
  43 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
  44 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  45 int stm32x_probe(struct flash_bank_s *bank);
  46 int stm32x_auto_probe(struct flash_bank_s *bank);
  47 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  48 int stm32x_protect_check(struct flash_bank_s *bank);
  49 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  50
  51 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int stm32x_mass_erase(struct flash_bank_s *bank);
  57
  58 flash_driver_t stm32x_flash =
  59 {
  60         .name = "stm32x",
  61         .register_commands = stm32x_register_commands,
  62         .flash_bank_command = stm32x_flash_bank_command,
  63         .erase = stm32x_erase,
  64         .protect = stm32x_protect,
  65         .write = stm32x_write,
  66         .probe = stm32x_probe,
  67         .auto_probe = stm32x_auto_probe,
  68         .erase_check = default_flash_mem_blank_check,
  69         .protect_check = stm32x_protect_check,
  70         .info = stm32x_info
  71 };
  72
  73 int stm32x_register_commands(struct command_context_s *cmd_ctx)
  74 {
  75         command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
  76
  77         register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
  78                                          "lock device");
  79         register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
  80                                          "unlock protected device");
  81         register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
  82                                          "mass erase device");
  83         register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
  84                                          "read device option bytes");
  85         register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
  86                                          "write device option bytes");
  87         return ERROR_OK;
  88 }
  89
  90 /* flash bank stm32x <base> <size> 0 0 <target#>
  91  */
  92 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  93 {
  94         stm32x_flash_bank_t *stm32x_info;
  95
  96         if (argc < 6)
  97         {
  98                 LOG_WARNING("incomplete flash_bank stm32x configuration");
  99                 return ERROR_FLASH_BANK_INVALID;
 100         }
 101
 102         stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
 103         bank->driver_priv = stm32x_info;
 104
 105         stm32x_info->write_algorithm = NULL;
 106         stm32x_info->probed = 0;
 107
 108         return ERROR_OK;
 109 }
 110
 111 u32 stm32x_get_flash_status(flash_bank_t *bank)
 112 {
 113         target_t *target = bank->target;
 114         u32 status;
 115
 116         target_read_u32(target, STM32_FLASH_SR, &status);
 117
 118         return status;
 119 }
 120
 121 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
 122 {
 123         u32 status;
 124
 125         /* wait for busy to clear */
 126         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
 127         {
 128                 LOG_DEBUG("status: 0x%x", status);
 129                 alive_sleep(1);
 130         }
 131
 132         return status;
 133 }
 134
 135 int stm32x_read_options(struct flash_bank_s *bank)
 136 {
 137         u32 optiondata;
 138         stm32x_flash_bank_t *stm32x_info = NULL;
 139         target_t *target = bank->target;
 140
 141         stm32x_info = bank->driver_priv;
 142
 143         /* read current option bytes */
 144         target_read_u32(target, STM32_FLASH_OBR, &optiondata);
 145
 146         stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
 147         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 148
 149         if (optiondata & (1 << OPT_READOUT))
 150                 LOG_INFO("Device Security Bit Set");
 151
 152         /* each bit refers to a 4bank protection */
 153         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 154
 155         stm32x_info->option_bytes.protection[0] = (u16)optiondata;
 156         stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
 157         stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
 158         stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
 159
 160         return ERROR_OK;
 161 }
 162
 163 int stm32x_erase_options(struct flash_bank_s *bank)
 164 {
 165         stm32x_flash_bank_t *stm32x_info = NULL;
 166         target_t *target = bank->target;
 167         u32 status;
 168
 169         stm32x_info = bank->driver_priv;
 170
 171         /* read current options */
 172         stm32x_read_options(bank);
 173
 174         /* unlock flash registers */
 175         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 176         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 177
 178         /* unlock option flash registers */
 179         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 180         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 181
 182         /* erase option bytes */
 183         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
 184         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
 185
 186         status = stm32x_wait_status_busy(bank, 10);
 187
 188         if( status & FLASH_WRPRTERR )
 189                 return ERROR_FLASH_OPERATION_FAILED;
 190         if( status & FLASH_PGERR )
 191                 return ERROR_FLASH_OPERATION_FAILED;
 192
 193         /* clear readout protection and complementary option bytes
 194          * this will also force a device unlock if set */
 195         stm32x_info->option_bytes.RDP = 0x5AA5;
 196
 197         return ERROR_OK;
 198 }
 199
 200 int stm32x_write_options(struct flash_bank_s *bank)
 201 {
 202         stm32x_flash_bank_t *stm32x_info = NULL;
 203         target_t *target = bank->target;
 204         u32 status;
 205
 206         stm32x_info = bank->driver_priv;
 207
 208         /* unlock flash registers */
 209         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 210         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 211
 212         /* unlock option flash registers */
 213         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 214         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 215
 216         /* program option bytes */
 217         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
 218
 219         /* write user option byte */
 220         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 221
 222         status = stm32x_wait_status_busy(bank, 10);
 223
 224         if( status & FLASH_WRPRTERR )
 225                 return ERROR_FLASH_OPERATION_FAILED;
 226         if( status & FLASH_PGERR )
 227                 return ERROR_FLASH_OPERATION_FAILED;
 228
 229         /* write protection byte 1 */
 230         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 231
 232         status = stm32x_wait_status_busy(bank, 10);
 233
 234         if( status & FLASH_WRPRTERR )
 235                 return ERROR_FLASH_OPERATION_FAILED;
 236         if( status & FLASH_PGERR )
 237                 return ERROR_FLASH_OPERATION_FAILED;
 238
 239         /* write protection byte 2 */
 240         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 241
 242         status = stm32x_wait_status_busy(bank, 10);
 243
 244         if( status & FLASH_WRPRTERR )
 245                 return ERROR_FLASH_OPERATION_FAILED;
 246         if( status & FLASH_PGERR )
 247                 return ERROR_FLASH_OPERATION_FAILED;
 248
 249         /* write protection byte 3 */
 250         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 251
 252         status = stm32x_wait_status_busy(bank, 10);
 253
 254         if( status & FLASH_WRPRTERR )
 255                 return ERROR_FLASH_OPERATION_FAILED;
 256         if( status & FLASH_PGERR )
 257                 return ERROR_FLASH_OPERATION_FAILED;
 258
 259         /* write protection byte 4 */
 260         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 261
 262         status = stm32x_wait_status_busy(bank, 10);
 263
 264         if( status & FLASH_WRPRTERR )
 265                 return ERROR_FLASH_OPERATION_FAILED;
 266         if( status & FLASH_PGERR )
 267                 return ERROR_FLASH_OPERATION_FAILED;
 268
 269         /* write readout protection bit */
 270         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 271
 272         status = stm32x_wait_status_busy(bank, 10);
 273
 274         if( status & FLASH_WRPRTERR )
 275                 return ERROR_FLASH_OPERATION_FAILED;
 276         if( status & FLASH_PGERR )
 277                 return ERROR_FLASH_OPERATION_FAILED;
 278
 279         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 280
 281         return ERROR_OK;
 282 }
 283
 284 int stm32x_protect_check(struct flash_bank_s *bank)
 285 {
 286         target_t *target = bank->target;
 287         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 288
 289         u32 protection;
 290         int i, s;
 291         int num_bits;
 292         int set;
 293
 294         if (target->state != TARGET_HALTED)
 295         {
 296                 LOG_ERROR("Target not halted");
 297                 return ERROR_TARGET_NOT_HALTED;
 298         }
 299
 300         /* medium density - each bit refers to a 4bank protection
 301          * high density - each bit refers to a 2bank protection */
 302         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 303
 304         /* medium density - each protection bit is for 4 * 1K pages
 305          * high density - each protection bit is for 2 * 2K pages */
 306         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 307
 308         if (stm32x_info->ppage_size == 2)
 309         {
 310                 /* high density flash */
 311
 312                 set = 1;
 313
 314                 if (protection & (1 << 31))
 315                         set = 0;
 316
 317                 /* bit 31 controls sector 62 - 255 protection */
 318                 for (s = 62; s < bank->num_sectors; s++)
 319                 {
 320                         bank->sectors[s].is_protected = set;
 321                 }
 322
 323                 if (bank->num_sectors > 61)
 324                         num_bits = 31;
 325
 326                 for (i = 0; i < num_bits; i++)
 327                 {
 328                         set = 1;
 329
 330                         if (protection & (1 << i))
 331                                 set = 0;
 332
 333                         for (s = 0; s < stm32x_info->ppage_size; s++)
 334                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 335                 }
 336         }
 337         else
 338         {
 339                 /* medium density flash */
 340                 for (i = 0; i < num_bits; i++)
 341                 {
 342                         set = 1;
 343
 344                         if( protection & (1 << i))
 345                                 set = 0;
 346
 347                         for (s = 0; s < stm32x_info->ppage_size; s++)
 348                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 349                 }
 350         }
 351
 352         return ERROR_OK;
 353 }
 354
 355 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 356 {
 357         target_t *target = bank->target;
 358         int i;
 359         u32 status;
 360
 361         if (bank->target->state != TARGET_HALTED)
 362         {
 363                 LOG_ERROR("Target not halted");
 364                 return ERROR_TARGET_NOT_HALTED;
 365         }
 366
 367         if ((first == 0) && (last == (bank->num_sectors - 1)))
 368         {
 369                 return stm32x_mass_erase(bank);
 370         }
 371
 372         /* unlock flash registers */
 373         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 374         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 375
 376         for (i = first; i <= last; i++)
 377         {
 378                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
 379                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
 380                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
 381
 382                 status = stm32x_wait_status_busy(bank, 10);
 383
 384                 if( status & FLASH_WRPRTERR )
 385                         return ERROR_FLASH_OPERATION_FAILED;
 386                 if( status & FLASH_PGERR )
 387                         return ERROR_FLASH_OPERATION_FAILED;
 388                 bank->sectors[i].is_erased = 1;
 389         }
 390
 391         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 392
 393         return ERROR_OK;
 394 }
 395
 396 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 397 {
 398         stm32x_flash_bank_t *stm32x_info = NULL;
 399         target_t *target = bank->target;
 400         u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 401         int i, reg, bit;
 402         int status;
 403         u32 protection;
 404
 405         stm32x_info = bank->driver_priv;
 406
 407         if (target->state != TARGET_HALTED)
 408         {
 409                 LOG_ERROR("Target not halted");
 410                 return ERROR_TARGET_NOT_HALTED;
 411         }
 412
 413         if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
 414         {
 415                 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
 416                 return ERROR_FLASH_SECTOR_INVALID;
 417         }
 418
 419         /* medium density - each bit refers to a 4bank protection
 420          * high density - each bit refers to a 2bank protection */
 421         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 422
 423         prot_reg[0] = (u16)protection;
 424         prot_reg[1] = (u16)(protection >> 8);
 425         prot_reg[2] = (u16)(protection >> 16);
 426         prot_reg[3] = (u16)(protection >> 24);
 427
 428         if (stm32x_info->ppage_size == 2)
 429         {
 430                 /* high density flash */
 431
 432                 /* bit 7 controls sector 62 - 255 protection */
 433                 if (last > 61)
 434                 {
 435                         if (set)
 436                                 prot_reg[3] &= ~(1 << 7);
 437                         else
 438                                 prot_reg[3] |= (1 << 7);
 439                 }
 440
 441                 if (first > 61)
 442                         first = 62;
 443                 if (last > 61)
 444                         last = 61;
 445
 446                 for (i = first; i <= last; i++)
 447                 {
 448                         reg = (i / stm32x_info->ppage_size) / 8;
 449                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 450
 451                         if( set )
 452                                 prot_reg[reg] &= ~(1 << bit);
 453                         else
 454                                 prot_reg[reg] |= (1 << bit);
 455                 }
 456         }
 457         else
 458         {
 459                 /* medium density flash */
 460                 for (i = first; i <= last; i++)
 461                 {
 462                         reg = (i / stm32x_info->ppage_size) / 8;
 463                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 464
 465                         if( set )
 466                                 prot_reg[reg] &= ~(1 << bit);
 467                         else
 468                                 prot_reg[reg] |= (1 << bit);
 469                 }
 470         }
 471
 472         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 473                 return status;
 474
 475         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 476         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 477         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 478         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 479
 480         return stm32x_write_options(bank);
 481 }
 482
 483 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 484 {
 485         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 486         target_t *target = bank->target;
 487         u32 buffer_size = 8192;
 488         working_area_t *source;
 489         u32 address = bank->base + offset;
 490         reg_param_t reg_params[4];
 491         armv7m_algorithm_t armv7m_info;
 492         int retval = ERROR_OK;
 493
 494         u8 stm32x_flash_write_code[] = {
 495                                                                         /* write: */
 496                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
 497                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
 498                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
 499                 0x23, 0x60,                                     /* str  r3, [r4, #0] */
 500                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
 501                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
 502                                                                         /* busy: */
 503                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
 504                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
 505                 0xFB, 0xD0,                                     /* beq  busy */
 506                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
 507                 0x01, 0xD1,                                     /* bne  exit */
 508                 0x01, 0x3A,                                     /* subs r2, r2, #1 */
 509                 0xED, 0xD1,                                     /* bne  write */
 510                                                                         /* exit: */
 511                 0xFE, 0xE7,                                     /* b exit */
 512                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
 513                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
 514         };
 515
 516         /* flash write code */
 517         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 518         {
 519                 LOG_WARNING("no working area available, can't do block memory writes");
 520                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 521         };
 522
 523         if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
 524                 return retval;
 525
 526         /* memory buffer */
 527         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 528         {
 529                 buffer_size /= 2;
 530                 if (buffer_size <= 256)
 531                 {
 532                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 533                         if (stm32x_info->write_algorithm)
 534                                 target_free_working_area(target, stm32x_info->write_algorithm);
 535
 536                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 537                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 538                 }
 539         };
 540
 541         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 542         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 543
 544         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 545         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 546         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 547         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
 548
 549         while (count > 0)
 550         {
 551                 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
 552
 553                 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
 554                         break;
 555
 556                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 557                 buf_set_u32(reg_params[1].value, 0, 32, address);
 558                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 559
 560                 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 561                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 562                 {
 563                         LOG_ERROR("error executing stm32x flash write algorithm");
 564                         retval = ERROR_FLASH_OPERATION_FAILED;
 565                         break;
 566                 }
 567
 568                 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
 569                 {
 570                         retval = ERROR_FLASH_OPERATION_FAILED;
 571                         break;
 572                 }
 573
 574                 buffer += thisrun_count * 2;
 575                 address += thisrun_count * 2;
 576                 count -= thisrun_count;
 577         }
 578
 579         target_free_working_area(target, source);
 580         target_free_working_area(target, stm32x_info->write_algorithm);
 581
 582         destroy_reg_param(&reg_params[0]);
 583         destroy_reg_param(&reg_params[1]);
 584         destroy_reg_param(&reg_params[2]);
 585         destroy_reg_param(&reg_params[3]);
 586
 587         return retval;
 588 }
 589
 590 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 591 {
 592         target_t *target = bank->target;
 593         u32 words_remaining = (count / 2);
 594         u32 bytes_remaining = (count & 0x00000001);
 595         u32 address = bank->base + offset;
 596         u32 bytes_written = 0;
 597         u8 status;
 598         u32 retval;
 599
 600         if (bank->target->state != TARGET_HALTED)
 601         {
 602                 LOG_ERROR("Target not halted");
 603                 return ERROR_TARGET_NOT_HALTED;
 604         }
 605
 606         if (offset & 0x1)
 607         {
 608                 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
 609                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 610         }
 611
 612         /* unlock flash registers */
 613         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 614         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 615
 616         /* multiple half words (2-byte) to be programmed? */
 617         if (words_remaining > 0)
 618         {
 619                 /* try using a block write */
 620                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 621                 {
 622                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 623                         {
 624                                 /* if block write failed (no sufficient working area),
 625                                  * we use normal (slow) single dword accesses */
 626                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 627                         }
 628                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 629                         {
 630                                 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
 631                                 return ERROR_FLASH_OPERATION_FAILED;
 632                         }
 633                 }
 634                 else
 635                 {
 636                         buffer += words_remaining * 2;
 637                         address += words_remaining * 2;
 638                         words_remaining = 0;
 639                 }
 640         }
 641
 642         while (words_remaining > 0)
 643         {
 644                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 645                 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
 646
 647                 status = stm32x_wait_status_busy(bank, 5);
 648
 649                 if( status & FLASH_WRPRTERR )
 650                         return ERROR_FLASH_OPERATION_FAILED;
 651                 if( status & FLASH_PGERR )
 652                         return ERROR_FLASH_OPERATION_FAILED;
 653
 654                 bytes_written += 2;
 655                 words_remaining--;
 656                 address += 2;
 657         }
 658
 659         if (bytes_remaining)
 660         {
 661                 u8 last_halfword[2] = {0xff, 0xff};
 662                 int i = 0;
 663
 664                 while(bytes_remaining > 0)
 665                 {
 666                         last_halfword[i++] = *(buffer + bytes_written);
 667                         bytes_remaining--;
 668                         bytes_written++;
 669                 }
 670
 671                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 672                 target_write_u16(target, address, *(u16*)last_halfword);
 673
 674                 status = stm32x_wait_status_busy(bank, 5);
 675
 676                 if( status & FLASH_WRPRTERR )
 677                         return ERROR_FLASH_OPERATION_FAILED;
 678                 if( status & FLASH_PGERR )
 679                         return ERROR_FLASH_OPERATION_FAILED;
 680         }
 681
 682         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 683
 684         return ERROR_OK;
 685 }
 686
 687 int stm32x_probe(struct flash_bank_s *bank)
 688 {
 689         target_t *target = bank->target;
 690         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 691         int i;
 692         u16 num_pages;
 693         u32 device_id;
 694         int page_size;
 695
 696         if (bank->target->state != TARGET_HALTED)
 697         {
 698                 LOG_ERROR("Target not halted");
 699                 return ERROR_TARGET_NOT_HALTED;
 700         }
 701
 702         stm32x_info->probed = 0;
 703
 704         /* read stm32 device id register */
 705         target_read_u32(target, 0xE0042000, &device_id);
 706         LOG_INFO( "device id = 0x%08x", device_id );
 707
 708         /* get flash size from target */
 709         if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
 710         {
 711                 /* failed reading flash size, default to max target family */
 712                 num_pages = 0xffff;
 713         }
 714
 715         if ((device_id & 0x7ff) == 0x410)
 716         {
 717                 /* medium density - we have 1k pages
 718                  * 4 pages for a protection area */
 719                 page_size = 1024;
 720                 stm32x_info->ppage_size = 4;
 721
 722                 /* check for early silicon */
 723                 if (num_pages == 0xffff)
 724                 {
 725                         /* number of sectors incorrect on revA */
 726                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
 727                         num_pages = 128;
 728                 }
 729         }
 730         else if ((device_id & 0x7ff) == 0x412)
 731         {
 732                 /* low density - we have 1k pages
 733                  * 4 pages for a protection area */
 734                 page_size = 1024;
 735                 stm32x_info->ppage_size = 4;
 736
 737                 /* check for early silicon */
 738                 if (num_pages == 0xffff)
 739                 {
 740                         /* number of sectors incorrect on revA */
 741                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 32k flash" );
 742                         num_pages = 32;
 743                 }
 744         }
 745         else if ((device_id & 0x7ff) == 0x414)
 746         {
 747                 /* high density - we have 2k pages
 748                  * 2 pages for a protection area */
 749                 page_size = 2048;
 750                 stm32x_info->ppage_size = 2;
 751
 752                 /* check for early silicon */
 753                 if (num_pages == 0xffff)
 754                 {
 755                         /* number of sectors incorrect on revZ */
 756                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
 757                         num_pages = 512;
 758                 }
 759         }
 760         else
 761         {
 762                 LOG_WARNING( "Cannot identify target as a STM32 family." );
 763                 return ERROR_FLASH_OPERATION_FAILED;
 764         }
 765
 766         LOG_INFO( "flash size = %dkbytes", num_pages );
 767
 768         /* calculate numbers of pages */
 769         num_pages /= (page_size / 1024);
 770
 771         bank->base = 0x08000000;
 772         bank->size = (num_pages * page_size);
 773         bank->num_sectors = num_pages;
 774         bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
 775
 776         for (i = 0; i < num_pages; i++)
 777         {
 778                 bank->sectors[i].offset = i * page_size;
 779                 bank->sectors[i].size = page_size;
 780                 bank->sectors[i].is_erased = -1;
 781                 bank->sectors[i].is_protected = 1;
 782         }
 783
 784         stm32x_info->probed = 1;
 785
 786         return ERROR_OK;
 787 }
 788
 789 int stm32x_auto_probe(struct flash_bank_s *bank)
 790 {
 791         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 792         if (stm32x_info->probed)
 793                 return ERROR_OK;
 794         return stm32x_probe(bank);
 795 }
 796
 797 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 798 {
 799         return ERROR_OK;
 800 }
 801
 802 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
 803 {
 804         target_t *target = bank->target;
 805         u32 device_id;
 806         int printed;
 807
 808         /* read stm32 device id register */
 809         target_read_u32(target, 0xE0042000, &device_id);
 810
 811         if ((device_id & 0x7ff) == 0x410)
 812         {
 813                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
 814                 buf += printed;
 815                 buf_size -= printed;
 816
 817                 switch(device_id >> 16)
 818                 {
 819                         case 0x0000:
 820                                 snprintf(buf, buf_size, "A");
 821                                 break;
 822
 823                         case 0x2000:
 824                                 snprintf(buf, buf_size, "B");
 825                                 break;
 826
 827                         case 0x2001:
 828                                 snprintf(buf, buf_size, "Z");
 829                                 break;
 830
 831                         case 0x2003:
 832                                 snprintf(buf, buf_size, "Y");
 833                                 break;
 834
 835                         default:
 836                                 snprintf(buf, buf_size, "unknown");
 837                                 break;
 838                 }
 839         }
 840         else if ((device_id & 0x7ff) == 0x412)
 841         {
 842                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
 843                 buf += printed;
 844                 buf_size -= printed;
 845
 846                 switch(device_id >> 16)
 847                 {
 848                         case 0x1000:
 849                                 snprintf(buf, buf_size, "A");
 850                                 break;
 851
 852                         default:
 853                                 snprintf(buf, buf_size, "unknown");
 854                                 break;
 855                 }
 856         }
 857         else if ((device_id & 0x7ff) == 0x414)
 858         {
 859                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
 860                 buf += printed;
 861                 buf_size -= printed;
 862
 863                 switch(device_id >> 16)
 864                 {
 865                         case 0x1000:
 866                                 snprintf(buf, buf_size, "A");
 867                                 break;
 868
 869                         case 0x1001:
 870                                 snprintf(buf, buf_size, "Z");
 871                                 break;
 872
 873                         default:
 874                                 snprintf(buf, buf_size, "unknown");
 875                                 break;
 876                 }
 877         }
 878         else
 879         {
 880                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
 881                 return ERROR_FLASH_OPERATION_FAILED;
 882         }
 883
 884         return ERROR_OK;
 885 }
 886
 887 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 888 {
 889         flash_bank_t *bank;
 890         target_t *target = NULL;
 891         stm32x_flash_bank_t *stm32x_info = NULL;
 892
 893         if (argc < 1)
 894         {
 895                 command_print(cmd_ctx, "stm32x lock <bank>");
 896                 return ERROR_OK;
 897         }
 898
 899         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 900         if (!bank)
 901         {
 902                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 903                 return ERROR_OK;
 904         }
 905
 906         stm32x_info = bank->driver_priv;
 907
 908         target = bank->target;
 909
 910         if (target->state != TARGET_HALTED)
 911         {
 912                 LOG_ERROR("Target not halted");
 913                 return ERROR_TARGET_NOT_HALTED;
 914         }
 915
 916         if (stm32x_erase_options(bank) != ERROR_OK)
 917         {
 918                 command_print(cmd_ctx, "stm32x failed to erase options");
 919                 return ERROR_OK;
 920         }
 921
 922         /* set readout protection */
 923         stm32x_info->option_bytes.RDP = 0;
 924
 925         if (stm32x_write_options(bank) != ERROR_OK)
 926         {
 927                 command_print(cmd_ctx, "stm32x failed to lock device");
 928                 return ERROR_OK;
 929         }
 930
 931         command_print(cmd_ctx, "stm32x locked");
 932
 933         return ERROR_OK;
 934 }
 935
 936 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 937 {
 938         flash_bank_t *bank;
 939         target_t *target = NULL;
 940         stm32x_flash_bank_t *stm32x_info = NULL;
 941
 942         if (argc < 1)
 943         {
 944                 command_print(cmd_ctx, "stm32x unlock <bank>");
 945                 return ERROR_OK;
 946         }
 947
 948         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 949         if (!bank)
 950         {
 951                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 952                 return ERROR_OK;
 953         }
 954
 955         stm32x_info = bank->driver_priv;
 956
 957         target = bank->target;
 958
 959         if (target->state != TARGET_HALTED)
 960         {
 961                 LOG_ERROR("Target not halted");
 962                 return ERROR_TARGET_NOT_HALTED;
 963         }
 964
 965         if (stm32x_erase_options(bank) != ERROR_OK)
 966         {
 967                 command_print(cmd_ctx, "stm32x failed to unlock device");
 968                 return ERROR_OK;
 969         }
 970
 971         if (stm32x_write_options(bank) != ERROR_OK)
 972         {
 973                 command_print(cmd_ctx, "stm32x failed to lock device");
 974                 return ERROR_OK;
 975         }
 976
 977         command_print(cmd_ctx, "stm32x unlocked");
 978
 979         return ERROR_OK;
 980 }
 981
 982 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 983 {
 984         flash_bank_t *bank;
 985         u32 optionbyte;
 986         target_t *target = NULL;
 987         stm32x_flash_bank_t *stm32x_info = NULL;
 988
 989         if (argc < 1)
 990         {
 991                 command_print(cmd_ctx, "stm32x options_read <bank>");
 992                 return ERROR_OK;
 993         }
 994
 995         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 996         if (!bank)
 997         {
 998                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 999                 return ERROR_OK;
1000         }
1001
1002         stm32x_info = bank->driver_priv;
1003
1004         target = bank->target;
1005
1006         if (target->state != TARGET_HALTED)
1007         {
1008                 LOG_ERROR("Target not halted");
1009                 return ERROR_TARGET_NOT_HALTED;
1010         }
1011
1012         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1013         command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
1014
1015         if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
1016                 command_print(cmd_ctx, "Option Byte Complement Error");
1017
1018         if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
1019                 command_print(cmd_ctx, "Readout Protection On");
1020         else
1021                 command_print(cmd_ctx, "Readout Protection Off");
1022
1023         if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
1024                 command_print(cmd_ctx, "Software Watchdog");
1025         else
1026                 command_print(cmd_ctx, "Hardware Watchdog");
1027
1028         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
1029                 command_print(cmd_ctx, "Stop: No reset generated");
1030         else
1031                 command_print(cmd_ctx, "Stop: Reset generated");
1032
1033         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
1034                 command_print(cmd_ctx, "Standby: No reset generated");
1035         else
1036                 command_print(cmd_ctx, "Standby: Reset generated");
1037
1038         return ERROR_OK;
1039 }
1040
1041 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1042 {
1043         flash_bank_t *bank;
1044         target_t *target = NULL;
1045         stm32x_flash_bank_t *stm32x_info = NULL;
1046         u16 optionbyte = 0xF8;
1047
1048         if (argc < 4)
1049         {
1050                 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
1051                 return ERROR_OK;
1052         }
1053
1054         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1055         if (!bank)
1056         {
1057                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1058                 return ERROR_OK;
1059         }
1060
1061         stm32x_info = bank->driver_priv;
1062
1063         target = bank->target;
1064
1065         if (target->state != TARGET_HALTED)
1066         {
1067                 LOG_ERROR("Target not halted");
1068                 return ERROR_TARGET_NOT_HALTED;
1069         }
1070
1071         if (strcmp(args[1], "SWWDG") == 0)
1072         {
1073                 optionbyte |= (1<<0);
1074         }
1075         else
1076         {
1077                 optionbyte &= ~(1<<0);
1078         }
1079
1080         if (strcmp(args[2], "NORSTSTNDBY") == 0)
1081         {
1082                 optionbyte |= (1<<1);
1083         }
1084         else
1085         {
1086                 optionbyte &= ~(1<<1);
1087         }
1088
1089         if (strcmp(args[3], "NORSTSTOP") == 0)
1090         {
1091                 optionbyte |= (1<<2);
1092         }
1093         else
1094         {
1095                 optionbyte &= ~(1<<2);
1096         }
1097
1098         if (stm32x_erase_options(bank) != ERROR_OK)
1099         {
1100                 command_print(cmd_ctx, "stm32x failed to erase options");
1101                 return ERROR_OK;
1102         }
1103
1104         stm32x_info->option_bytes.user_options = optionbyte;
1105
1106         if (stm32x_write_options(bank) != ERROR_OK)
1107         {
1108                 command_print(cmd_ctx, "stm32x failed to write options");
1109                 return ERROR_OK;
1110         }
1111
1112         command_print(cmd_ctx, "stm32x write options complete");
1113
1114         return ERROR_OK;
1115 }
1116
1117 int stm32x_mass_erase(struct flash_bank_s *bank)
1118 {
1119         target_t *target = bank->target;
1120         u32 status;
1121
1122         if (target->state != TARGET_HALTED)
1123         {
1124                 LOG_ERROR("Target not halted");
1125                 return ERROR_TARGET_NOT_HALTED;
1126         }
1127
1128         /* unlock option flash registers */
1129         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1130         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1131
1132         /* mass erase flash memory */
1133         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1134         target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
1135
1136         status = stm32x_wait_status_busy(bank, 10);
1137
1138         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1139
1140         if( status & FLASH_WRPRTERR )
1141         {
1142                 LOG_ERROR("stm32x device protected");
1143                 return ERROR_OK;
1144         }
1145
1146         if( status & FLASH_PGERR )
1147         {
1148                 LOG_ERROR("stm32x device programming failed");
1149                 return ERROR_OK;
1150         }
1151
1152         return ERROR_OK;
1153 }
1154
1155 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1156 {
1157         flash_bank_t *bank;
1158         int i;
1159
1160         if (argc < 1)
1161         {
1162                 command_print(cmd_ctx, "stm32x mass_erase <bank>");
1163                 return ERROR_OK;
1164         }
1165
1166         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1167         if (!bank)
1168         {
1169                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1170                 return ERROR_OK;
1171         }
1172
1173         if (stm32x_mass_erase(bank) == ERROR_OK)
1174         {
1175                 /* set all sectors as erased */
1176                 for (i = 0; i < bank->num_sectors; i++)
1177                 {
1178                         bank->sectors[i].is_erased = 1;
1179                 }
1180
1181                 command_print(cmd_ctx, "stm32x mass erase complete");
1182         }
1183         else
1184         {
1185                 command_print(cmd_ctx, "stm32x mass erase failed");
1186         }
1187
1188         return ERROR_OK;
1189 }