git.sur5r.net Git - openocd/blob - src/flash/stm32x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "replacements.h"
  28
  29 #include "stm32x.h"
  30 #include "flash.h"
  31 #include "target.h"
  32 #include "log.h"
  33 #include "armv7m.h"
  34 #include "algorithm.h"
  35 #include "binarybuffer.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39
  40 int stm32x_register_commands(struct command_context_s *cmd_ctx);
  41 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  42 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
  43 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
  44 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  45 int stm32x_probe(struct flash_bank_s *bank);
  46 int stm32x_auto_probe(struct flash_bank_s *bank);
  47 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  48 int stm32x_protect_check(struct flash_bank_s *bank);
  49 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  50
  51 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  54 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  55 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  56 int stm32x_mass_erase(struct flash_bank_s *bank);
  57
  58 flash_driver_t stm32x_flash =
  59 {
  60         .name = "stm32x",
  61         .register_commands = stm32x_register_commands,
  62         .flash_bank_command = stm32x_flash_bank_command,
  63         .erase = stm32x_erase,
  64         .protect = stm32x_protect,
  65         .write = stm32x_write,
  66         .probe = stm32x_probe,
  67         .auto_probe = stm32x_auto_probe,
  68         .erase_check = default_flash_mem_blank_check,
  69         .protect_check = stm32x_protect_check,
  70         .info = stm32x_info
  71 };
  72
  73 int stm32x_register_commands(struct command_context_s *cmd_ctx)
  74 {
  75         command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
  76
  77         register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
  78                                          "lock device");
  79         register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
  80                                          "unlock protected device");
  81         register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
  82                                          "mass erase device");
  83         register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
  84                                          "read device option bytes");
  85         register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
  86                                          "write device option bytes");
  87         return ERROR_OK;
  88 }
  89
  90 /* flash bank stm32x <base> <size> 0 0 <target#>
  91  */
  92 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  93 {
  94         stm32x_flash_bank_t *stm32x_info;
  95
  96         if (argc < 6)
  97         {
  98                 LOG_WARNING("incomplete flash_bank stm32x configuration");
  99                 return ERROR_FLASH_BANK_INVALID;
 100         }
 101
 102         stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
 103         bank->driver_priv = stm32x_info;
 104
 105         stm32x_info->write_algorithm = NULL;
 106         stm32x_info->probed = 0;
 107
 108         return ERROR_OK;
 109 }
 110
 111 u32 stm32x_get_flash_status(flash_bank_t *bank)
 112 {
 113         target_t *target = bank->target;
 114         u32 status;
 115
 116         target_read_u32(target, STM32_FLASH_SR, &status);
 117
 118         return status;
 119 }
 120
 121 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
 122 {
 123         u32 status;
 124
 125         /* wait for busy to clear */
 126         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
 127         {
 128                 LOG_DEBUG("status: 0x%x", status);
 129                 alive_sleep(1);
 130         }
 131
 132         return status;
 133 }
 134
 135 int stm32x_read_options(struct flash_bank_s *bank)
 136 {
 137         u32 optiondata;
 138         stm32x_flash_bank_t *stm32x_info = NULL;
 139         target_t *target = bank->target;
 140
 141         stm32x_info = bank->driver_priv;
 142
 143         /* read current option bytes */
 144         target_read_u32(target, STM32_FLASH_OBR, &optiondata);
 145
 146         stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
 147         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 148
 149         if (optiondata & (1 << OPT_READOUT))
 150                 LOG_INFO("Device Security Bit Set");
 151
 152         /* each bit refers to a 4bank protection */
 153         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 154
 155         stm32x_info->option_bytes.protection[0] = (u16)optiondata;
 156         stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
 157         stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
 158         stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
 159
 160         return ERROR_OK;
 161 }
 162
 163 int stm32x_erase_options(struct flash_bank_s *bank)
 164 {
 165         stm32x_flash_bank_t *stm32x_info = NULL;
 166         target_t *target = bank->target;
 167         u32 status;
 168
 169         stm32x_info = bank->driver_priv;
 170
 171         /* read current options */
 172         stm32x_read_options(bank);
 173
 174         /* unlock flash registers */
 175         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 176         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 177
 178         /* unlock option flash registers */
 179         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 180         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 181
 182         /* erase option bytes */
 183         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
 184         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
 185
 186         status = stm32x_wait_status_busy(bank, 10);
 187
 188         if( status & FLASH_WRPRTERR )
 189                 return ERROR_FLASH_OPERATION_FAILED;
 190         if( status & FLASH_PGERR )
 191                 return ERROR_FLASH_OPERATION_FAILED;
 192
 193         /* clear readout protection and complementary option bytes
 194          * this will also force a device unlock if set */
 195         stm32x_info->option_bytes.RDP = 0x5AA5;
 196
 197         return ERROR_OK;
 198 }
 199
 200 int stm32x_write_options(struct flash_bank_s *bank)
 201 {
 202         stm32x_flash_bank_t *stm32x_info = NULL;
 203         target_t *target = bank->target;
 204         u32 status;
 205
 206         stm32x_info = bank->driver_priv;
 207
 208         /* unlock flash registers */
 209         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 210         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 211
 212         /* unlock option flash registers */
 213         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 214         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 215
 216         /* program option bytes */
 217         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
 218
 219         /* write user option byte */
 220         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 221
 222         status = stm32x_wait_status_busy(bank, 10);
 223
 224         if( status & FLASH_WRPRTERR )
 225                 return ERROR_FLASH_OPERATION_FAILED;
 226         if( status & FLASH_PGERR )
 227                 return ERROR_FLASH_OPERATION_FAILED;
 228
 229         /* write protection byte 1 */
 230         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 231
 232         status = stm32x_wait_status_busy(bank, 10);
 233
 234         if( status & FLASH_WRPRTERR )
 235                 return ERROR_FLASH_OPERATION_FAILED;
 236         if( status & FLASH_PGERR )
 237                 return ERROR_FLASH_OPERATION_FAILED;
 238
 239         /* write protection byte 2 */
 240         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 241
 242         status = stm32x_wait_status_busy(bank, 10);
 243
 244         if( status & FLASH_WRPRTERR )
 245                 return ERROR_FLASH_OPERATION_FAILED;
 246         if( status & FLASH_PGERR )
 247                 return ERROR_FLASH_OPERATION_FAILED;
 248
 249         /* write protection byte 3 */
 250         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 251
 252         status = stm32x_wait_status_busy(bank, 10);
 253
 254         if( status & FLASH_WRPRTERR )
 255                 return ERROR_FLASH_OPERATION_FAILED;
 256         if( status & FLASH_PGERR )
 257                 return ERROR_FLASH_OPERATION_FAILED;
 258
 259         /* write protection byte 4 */
 260         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 261
 262         status = stm32x_wait_status_busy(bank, 10);
 263
 264         if( status & FLASH_WRPRTERR )
 265                 return ERROR_FLASH_OPERATION_FAILED;
 266         if( status & FLASH_PGERR )
 267                 return ERROR_FLASH_OPERATION_FAILED;
 268
 269         /* write readout protection bit */
 270         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 271
 272         status = stm32x_wait_status_busy(bank, 10);
 273
 274         if( status & FLASH_WRPRTERR )
 275                 return ERROR_FLASH_OPERATION_FAILED;
 276         if( status & FLASH_PGERR )
 277                 return ERROR_FLASH_OPERATION_FAILED;
 278
 279         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 280
 281         return ERROR_OK;
 282 }
 283
 284 int stm32x_protect_check(struct flash_bank_s *bank)
 285 {
 286         target_t *target = bank->target;
 287         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 288
 289         u32 protection;
 290         int i, s;
 291         int num_bits;
 292         int set;
 293
 294         if (target->state != TARGET_HALTED)
 295         {
 296                 LOG_ERROR("Target not halted");
 297                 return ERROR_TARGET_NOT_HALTED;
 298         }
 299
 300         /* medium density - each bit refers to a 4bank protection
 301          * high density - each bit refers to a 2bank protection */
 302         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 303
 304         /* medium density - each protection bit is for 4 * 1K pages
 305          * high density - each protection bit is for 2 * 2K pages */
 306         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 307
 308         if (stm32x_info->ppage_size == 2)
 309         {
 310                 /* high density flash */
 311
 312                 set = 1;
 313
 314                 if (protection & (1 << 31))
 315                         set = 0;
 316
 317                 /* bit 31 controls sector 62 - 255 protection */
 318                 for (s = 62; s < bank->num_sectors; s++)
 319                 {
 320                         bank->sectors[s].is_protected = set;
 321                 }
 322
 323                 if (bank->num_sectors > 61)
 324                         num_bits = 31;
 325
 326                 for (i = 0; i < num_bits; i++)
 327                 {
 328                         set = 1;
 329
 330                         if (protection & (1 << i))
 331                                 set = 0;
 332
 333                         for (s = 0; s < stm32x_info->ppage_size; s++)
 334                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 335                 }
 336         }
 337         else
 338         {
 339                 /* medium density flash */
 340                 for (i = 0; i < num_bits; i++)
 341                 {
 342                         set = 1;
 343
 344                         if( protection & (1 << i))
 345                                 set = 0;
 346
 347                         for (s = 0; s < stm32x_info->ppage_size; s++)
 348                                 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 349                 }
 350         }
 351
 352         return ERROR_OK;
 353 }
 354
 355 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 356 {
 357         target_t *target = bank->target;
 358         int i;
 359         u32 status;
 360
 361         if (bank->target->state != TARGET_HALTED)
 362         {
 363                 LOG_ERROR("Target not halted");
 364                 return ERROR_TARGET_NOT_HALTED;
 365         }
 366
 367         if ((first == 0) && (last == (bank->num_sectors - 1)))
 368         {
 369                 return stm32x_mass_erase(bank);
 370         }
 371
 372         /* unlock flash registers */
 373         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 374         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 375
 376         for (i = first; i <= last; i++)
 377         {
 378                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
 379                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
 380                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
 381
 382                 status = stm32x_wait_status_busy(bank, 10);
 383
 384                 if( status & FLASH_WRPRTERR )
 385                         return ERROR_FLASH_OPERATION_FAILED;
 386                 if( status & FLASH_PGERR )
 387                         return ERROR_FLASH_OPERATION_FAILED;
 388                 bank->sectors[i].is_erased = 1;
 389         }
 390
 391         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 392
 393         return ERROR_OK;
 394 }
 395
 396 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 397 {
 398         stm32x_flash_bank_t *stm32x_info = NULL;
 399         target_t *target = bank->target;
 400         u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 401         int i, reg, bit;
 402         int status;
 403         u32 protection;
 404
 405         stm32x_info = bank->driver_priv;
 406
 407         if (target->state != TARGET_HALTED)
 408         {
 409                 LOG_ERROR("Target not halted");
 410                 return ERROR_TARGET_NOT_HALTED;
 411         }
 412
 413         if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
 414         {
 415                 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
 416                 return ERROR_FLASH_SECTOR_INVALID;
 417         }
 418
 419         /* medium density - each bit refers to a 4bank protection
 420          * high density - each bit refers to a 2bank protection */
 421         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 422
 423         prot_reg[0] = (u16)protection;
 424         prot_reg[1] = (u16)(protection >> 8);
 425         prot_reg[2] = (u16)(protection >> 16);
 426         prot_reg[3] = (u16)(protection >> 24);
 427
 428         if (stm32x_info->ppage_size == 2)
 429         {
 430                 /* high density flash */
 431
 432                 /* bit 7 controls sector 62 - 255 protection */
 433                 if (last > 61)
 434                 {
 435                         if (set)
 436                                 prot_reg[3] &= ~(1 << 7);
 437                         else
 438                                 prot_reg[3] |= (1 << 7);
 439                 }
 440
 441                 if (first > 61)
 442                         first = 62;
 443                 if (last > 61)
 444                         last = 61;
 445
 446                 for (i = first; i <= last; i++)
 447                 {
 448                         reg = (i / stm32x_info->ppage_size) / 8;
 449                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 450
 451                         if( set )
 452                                 prot_reg[reg] &= ~(1 << bit);
 453                         else
 454                                 prot_reg[reg] |= (1 << bit);
 455                 }
 456         }
 457         else
 458         {
 459                 /* medium density flash */
 460                 for (i = first; i <= last; i++)
 461                 {
 462                         reg = (i / stm32x_info->ppage_size) / 8;
 463                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 464
 465                         if( set )
 466                                 prot_reg[reg] &= ~(1 << bit);
 467                         else
 468                                 prot_reg[reg] |= (1 << bit);
 469                 }
 470         }
 471
 472         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 473                 return status;
 474
 475         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 476         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 477         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 478         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 479
 480         return stm32x_write_options(bank);
 481 }
 482
 483 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 484 {
 485         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 486         target_t *target = bank->target;
 487         u32 buffer_size = 16384;
 488         working_area_t *source;
 489         u32 address = bank->base + offset;
 490         reg_param_t reg_params[4];
 491         armv7m_algorithm_t armv7m_info;
 492         int retval = ERROR_OK;
 493
 494         u8 stm32x_flash_write_code[] = {
 495                                                                         /* write: */
 496                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
 497                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
 498                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
 499                 0x23, 0x60,                                     /* str  r3, [r4, #0] */
 500                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
 501                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
 502                                                                         /* busy: */
 503                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
 504                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
 505                 0xFB, 0xD0,                                     /* beq  busy */
 506                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
 507                 0x01, 0xD1,                                     /* bne  exit */
 508                 0x01, 0x3A,                                     /* subs r2, r2, #1 */
 509                 0xED, 0xD1,                                     /* bne  write */
 510                                                                         /* exit: */
 511                 0xFE, 0xE7,                                     /* b exit */
 512                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
 513                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
 514         };
 515
 516         /* flash write code */
 517         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 518         {
 519                 LOG_WARNING("no working area available, can't do block memory writes");
 520                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 521         };
 522
 523         if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
 524                 return retval;
 525
 526         /* memory buffer */
 527         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 528         {
 529                 buffer_size /= 2;
 530                 if (buffer_size <= 256)
 531                 {
 532                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 533                         if (stm32x_info->write_algorithm)
 534                                 target_free_working_area(target, stm32x_info->write_algorithm);
 535
 536                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 537                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 538                 }
 539         };
 540
 541         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 542         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 543
 544         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 545         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 546         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 547         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
 548
 549         while (count > 0)
 550         {
 551                 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
 552
 553                 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
 554                         break;
 555
 556                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 557                 buf_set_u32(reg_params[1].value, 0, 32, address);
 558                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 559
 560                 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 561                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 562                 {
 563                         LOG_ERROR("error executing stm32x flash write algorithm");
 564                         retval = ERROR_FLASH_OPERATION_FAILED;
 565                         break;
 566                 }
 567
 568                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR)
 569                 {
 570                         LOG_ERROR("flash memory not erased before writing");
 571                         retval = ERROR_FLASH_OPERATION_FAILED;
 572                         break;
 573                 }
 574
 575                 if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR)
 576                 {
 577                         LOG_ERROR("flash memory write protected");
 578                         retval = ERROR_FLASH_OPERATION_FAILED;
 579                         break;
 580                 }
 581
 582                 buffer += thisrun_count * 2;
 583                 address += thisrun_count * 2;
 584                 count -= thisrun_count;
 585         }
 586
 587         target_free_working_area(target, source);
 588         target_free_working_area(target, stm32x_info->write_algorithm);
 589
 590         destroy_reg_param(&reg_params[0]);
 591         destroy_reg_param(&reg_params[1]);
 592         destroy_reg_param(&reg_params[2]);
 593         destroy_reg_param(&reg_params[3]);
 594
 595         return retval;
 596 }
 597
 598 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 599 {
 600         target_t *target = bank->target;
 601         u32 words_remaining = (count / 2);
 602         u32 bytes_remaining = (count & 0x00000001);
 603         u32 address = bank->base + offset;
 604         u32 bytes_written = 0;
 605         u8 status;
 606         u32 retval;
 607
 608         if (bank->target->state != TARGET_HALTED)
 609         {
 610                 LOG_ERROR("Target not halted");
 611                 return ERROR_TARGET_NOT_HALTED;
 612         }
 613
 614         if (offset & 0x1)
 615         {
 616                 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
 617                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 618         }
 619
 620         /* unlock flash registers */
 621         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 622         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 623
 624         /* multiple half words (2-byte) to be programmed? */
 625         if (words_remaining > 0)
 626         {
 627                 /* try using a block write */
 628                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 629                 {
 630                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 631                         {
 632                                 /* if block write failed (no sufficient working area),
 633                                  * we use normal (slow) single dword accesses */
 634                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 635                         }
 636                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 637                         {
 638                                 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
 639                                 return ERROR_FLASH_OPERATION_FAILED;
 640                         }
 641                 }
 642                 else
 643                 {
 644                         buffer += words_remaining * 2;
 645                         address += words_remaining * 2;
 646                         words_remaining = 0;
 647                 }
 648         }
 649
 650         while (words_remaining > 0)
 651         {
 652                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 653                 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
 654
 655                 status = stm32x_wait_status_busy(bank, 5);
 656
 657                 if( status & FLASH_WRPRTERR )
 658                 {
 659                         LOG_ERROR("flash memory not erased before writing");
 660                         return ERROR_FLASH_OPERATION_FAILED;
 661                 }
 662                 if( status & FLASH_PGERR )
 663                 {
 664                         LOG_ERROR("flash memory write protected");
 665                         return ERROR_FLASH_OPERATION_FAILED;
 666                 }
 667
 668                 bytes_written += 2;
 669                 words_remaining--;
 670                 address += 2;
 671         }
 672
 673         if (bytes_remaining)
 674         {
 675                 u8 last_halfword[2] = {0xff, 0xff};
 676                 int i = 0;
 677
 678                 while(bytes_remaining > 0)
 679                 {
 680                         last_halfword[i++] = *(buffer + bytes_written);
 681                         bytes_remaining--;
 682                         bytes_written++;
 683                 }
 684
 685                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 686                 target_write_u16(target, address, *(u16*)last_halfword);
 687
 688                 status = stm32x_wait_status_busy(bank, 5);
 689
 690                 if( status & FLASH_WRPRTERR )
 691                 {
 692                         LOG_ERROR("flash memory not erased before writing");
 693                         return ERROR_FLASH_OPERATION_FAILED;
 694                 }
 695                 if( status & FLASH_PGERR )
 696                 {
 697                         LOG_ERROR("flash memory write protected");
 698                         return ERROR_FLASH_OPERATION_FAILED;
 699                 }
 700         }
 701
 702         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 703
 704         return ERROR_OK;
 705 }
 706
 707 int stm32x_probe(struct flash_bank_s *bank)
 708 {
 709         target_t *target = bank->target;
 710         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 711         int i;
 712         u16 num_pages;
 713         u32 device_id;
 714         int page_size;
 715
 716         if (bank->target->state != TARGET_HALTED)
 717         {
 718                 LOG_ERROR("Target not halted");
 719                 return ERROR_TARGET_NOT_HALTED;
 720         }
 721
 722         stm32x_info->probed = 0;
 723
 724         /* read stm32 device id register */
 725         target_read_u32(target, 0xE0042000, &device_id);
 726         LOG_INFO( "device id = 0x%08x", device_id );
 727
 728         /* get flash size from target */
 729         if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
 730         {
 731                 /* failed reading flash size, default to max target family */
 732                 num_pages = 0xffff;
 733         }
 734
 735         if ((device_id & 0x7ff) == 0x410)
 736         {
 737                 /* medium density - we have 1k pages
 738                  * 4 pages for a protection area */
 739                 page_size = 1024;
 740                 stm32x_info->ppage_size = 4;
 741
 742                 /* check for early silicon */
 743                 if (num_pages == 0xffff)
 744                 {
 745                         /* number of sectors incorrect on revA */
 746                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
 747                         num_pages = 128;
 748                 }
 749         }
 750         else if ((device_id & 0x7ff) == 0x412)
 751         {
 752                 /* low density - we have 1k pages
 753                  * 4 pages for a protection area */
 754                 page_size = 1024;
 755                 stm32x_info->ppage_size = 4;
 756
 757                 /* check for early silicon */
 758                 if (num_pages == 0xffff)
 759                 {
 760                         /* number of sectors incorrect on revA */
 761                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 32k flash" );
 762                         num_pages = 32;
 763                 }
 764         }
 765         else if ((device_id & 0x7ff) == 0x414)
 766         {
 767                 /* high density - we have 2k pages
 768                  * 2 pages for a protection area */
 769                 page_size = 2048;
 770                 stm32x_info->ppage_size = 2;
 771
 772                 /* check for early silicon */
 773                 if (num_pages == 0xffff)
 774                 {
 775                         /* number of sectors incorrect on revZ */
 776                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
 777                         num_pages = 512;
 778                 }
 779         }
 780         else if ((device_id & 0x7ff) == 0x418)
 781         {
 782                 /* connectivity line density - we have 1k pages
 783                  * 4 pages for a protection area */
 784                 page_size = 1024;
 785                 stm32x_info->ppage_size = 4;
 786
 787                 /* check for early silicon */
 788                 if (num_pages == 0xffff)
 789                 {
 790                         /* number of sectors incorrect on revZ */
 791                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 256k flash" );
 792                         num_pages = 256;
 793                 }
 794         }
 795         else
 796         {
 797                 LOG_WARNING( "Cannot identify target as a STM32 family." );
 798                 return ERROR_FLASH_OPERATION_FAILED;
 799         }
 800
 801         LOG_INFO( "flash size = %dkbytes", num_pages );
 802
 803         /* calculate numbers of pages */
 804         num_pages /= (page_size / 1024);
 805
 806         bank->base = 0x08000000;
 807         bank->size = (num_pages * page_size);
 808         bank->num_sectors = num_pages;
 809         bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
 810
 811         for (i = 0; i < num_pages; i++)
 812         {
 813                 bank->sectors[i].offset = i * page_size;
 814                 bank->sectors[i].size = page_size;
 815                 bank->sectors[i].is_erased = -1;
 816                 bank->sectors[i].is_protected = 1;
 817         }
 818
 819         stm32x_info->probed = 1;
 820
 821         return ERROR_OK;
 822 }
 823
 824 int stm32x_auto_probe(struct flash_bank_s *bank)
 825 {
 826         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 827         if (stm32x_info->probed)
 828                 return ERROR_OK;
 829         return stm32x_probe(bank);
 830 }
 831
 832 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 833 {
 834         return ERROR_OK;
 835 }
 836
 837 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
 838 {
 839         target_t *target = bank->target;
 840         u32 device_id;
 841         int printed;
 842
 843         /* read stm32 device id register */
 844         target_read_u32(target, 0xE0042000, &device_id);
 845
 846         if ((device_id & 0x7ff) == 0x410)
 847         {
 848                 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
 849                 buf += printed;
 850                 buf_size -= printed;
 851
 852                 switch(device_id >> 16)
 853                 {
 854                         case 0x0000:
 855                                 snprintf(buf, buf_size, "A");
 856                                 break;
 857
 858                         case 0x2000:
 859                                 snprintf(buf, buf_size, "B");
 860                                 break;
 861
 862                         case 0x2001:
 863                                 snprintf(buf, buf_size, "Z");
 864                                 break;
 865
 866                         case 0x2003:
 867                                 snprintf(buf, buf_size, "Y");
 868                                 break;
 869
 870                         default:
 871                                 snprintf(buf, buf_size, "unknown");
 872                                 break;
 873                 }
 874         }
 875         else if ((device_id & 0x7ff) == 0x412)
 876         {
 877                 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
 878                 buf += printed;
 879                 buf_size -= printed;
 880
 881                 switch(device_id >> 16)
 882                 {
 883                         case 0x1000:
 884                                 snprintf(buf, buf_size, "A");
 885                                 break;
 886
 887                         default:
 888                                 snprintf(buf, buf_size, "unknown");
 889                                 break;
 890                 }
 891         }
 892         else if ((device_id & 0x7ff) == 0x414)
 893         {
 894                 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
 895                 buf += printed;
 896                 buf_size -= printed;
 897
 898                 switch(device_id >> 16)
 899                 {
 900                         case 0x1000:
 901                                 snprintf(buf, buf_size, "A");
 902                                 break;
 903
 904                         case 0x1001:
 905                                 snprintf(buf, buf_size, "Z");
 906                                 break;
 907
 908                         default:
 909                                 snprintf(buf, buf_size, "unknown");
 910                                 break;
 911                 }
 912         }
 913         else if ((device_id & 0x7ff) == 0x418)
 914         {
 915                 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
 916                 buf += printed;
 917                 buf_size -= printed;
 918
 919                 switch(device_id >> 16)
 920                 {
 921                         case 0x1000:
 922                                 snprintf(buf, buf_size, "A");
 923                                 break;
 924
 925                         default:
 926                                 snprintf(buf, buf_size, "unknown");
 927                                 break;
 928                 }
 929         }
 930         else
 931         {
 932                 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
 933                 return ERROR_FLASH_OPERATION_FAILED;
 934         }
 935
 936         return ERROR_OK;
 937 }
 938
 939 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 940 {
 941         flash_bank_t *bank;
 942         target_t *target = NULL;
 943         stm32x_flash_bank_t *stm32x_info = NULL;
 944
 945         if (argc < 1)
 946         {
 947                 command_print(cmd_ctx, "stm32x lock <bank>");
 948                 return ERROR_OK;
 949         }
 950
 951         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 952         if (!bank)
 953         {
 954                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 955                 return ERROR_OK;
 956         }
 957
 958         stm32x_info = bank->driver_priv;
 959
 960         target = bank->target;
 961
 962         if (target->state != TARGET_HALTED)
 963         {
 964                 LOG_ERROR("Target not halted");
 965                 return ERROR_TARGET_NOT_HALTED;
 966         }
 967
 968         if (stm32x_erase_options(bank) != ERROR_OK)
 969         {
 970                 command_print(cmd_ctx, "stm32x failed to erase options");
 971                 return ERROR_OK;
 972         }
 973
 974         /* set readout protection */
 975         stm32x_info->option_bytes.RDP = 0;
 976
 977         if (stm32x_write_options(bank) != ERROR_OK)
 978         {
 979                 command_print(cmd_ctx, "stm32x failed to lock device");
 980                 return ERROR_OK;
 981         }
 982
 983         command_print(cmd_ctx, "stm32x locked");
 984
 985         return ERROR_OK;
 986 }
 987
 988 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 989 {
 990         flash_bank_t *bank;
 991         target_t *target = NULL;
 992         stm32x_flash_bank_t *stm32x_info = NULL;
 993
 994         if (argc < 1)
 995         {
 996                 command_print(cmd_ctx, "stm32x unlock <bank>");
 997                 return ERROR_OK;
 998         }
 999
1000         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1001         if (!bank)
1002         {
1003                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1004                 return ERROR_OK;
1005         }
1006
1007         stm32x_info = bank->driver_priv;
1008
1009         target = bank->target;
1010
1011         if (target->state != TARGET_HALTED)
1012         {
1013                 LOG_ERROR("Target not halted");
1014                 return ERROR_TARGET_NOT_HALTED;
1015         }
1016
1017         if (stm32x_erase_options(bank) != ERROR_OK)
1018         {
1019                 command_print(cmd_ctx, "stm32x failed to unlock device");
1020                 return ERROR_OK;
1021         }
1022
1023         if (stm32x_write_options(bank) != ERROR_OK)
1024         {
1025                 command_print(cmd_ctx, "stm32x failed to lock device");
1026                 return ERROR_OK;
1027         }
1028
1029         command_print(cmd_ctx, "stm32x unlocked");
1030
1031         return ERROR_OK;
1032 }
1033
1034 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1035 {
1036         flash_bank_t *bank;
1037         u32 optionbyte;
1038         target_t *target = NULL;
1039         stm32x_flash_bank_t *stm32x_info = NULL;
1040
1041         if (argc < 1)
1042         {
1043                 command_print(cmd_ctx, "stm32x options_read <bank>");
1044                 return ERROR_OK;
1045         }
1046
1047         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1048         if (!bank)
1049         {
1050                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1051                 return ERROR_OK;
1052         }
1053
1054         stm32x_info = bank->driver_priv;
1055
1056         target = bank->target;
1057
1058         if (target->state != TARGET_HALTED)
1059         {
1060                 LOG_ERROR("Target not halted");
1061                 return ERROR_TARGET_NOT_HALTED;
1062         }
1063
1064         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
1065         command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
1066
1067         if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
1068                 command_print(cmd_ctx, "Option Byte Complement Error");
1069
1070         if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
1071                 command_print(cmd_ctx, "Readout Protection On");
1072         else
1073                 command_print(cmd_ctx, "Readout Protection Off");
1074
1075         if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
1076                 command_print(cmd_ctx, "Software Watchdog");
1077         else
1078                 command_print(cmd_ctx, "Hardware Watchdog");
1079
1080         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
1081                 command_print(cmd_ctx, "Stop: No reset generated");
1082         else
1083                 command_print(cmd_ctx, "Stop: Reset generated");
1084
1085         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
1086                 command_print(cmd_ctx, "Standby: No reset generated");
1087         else
1088                 command_print(cmd_ctx, "Standby: Reset generated");
1089
1090         return ERROR_OK;
1091 }
1092
1093 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1094 {
1095         flash_bank_t *bank;
1096         target_t *target = NULL;
1097         stm32x_flash_bank_t *stm32x_info = NULL;
1098         u16 optionbyte = 0xF8;
1099
1100         if (argc < 4)
1101         {
1102                 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
1103                 return ERROR_OK;
1104         }
1105
1106         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1107         if (!bank)
1108         {
1109                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1110                 return ERROR_OK;
1111         }
1112
1113         stm32x_info = bank->driver_priv;
1114
1115         target = bank->target;
1116
1117         if (target->state != TARGET_HALTED)
1118         {
1119                 LOG_ERROR("Target not halted");
1120                 return ERROR_TARGET_NOT_HALTED;
1121         }
1122
1123         if (strcmp(args[1], "SWWDG") == 0)
1124         {
1125                 optionbyte |= (1<<0);
1126         }
1127         else
1128         {
1129                 optionbyte &= ~(1<<0);
1130         }
1131
1132         if (strcmp(args[2], "NORSTSTNDBY") == 0)
1133         {
1134                 optionbyte |= (1<<1);
1135         }
1136         else
1137         {
1138                 optionbyte &= ~(1<<1);
1139         }
1140
1141         if (strcmp(args[3], "NORSTSTOP") == 0)
1142         {
1143                 optionbyte |= (1<<2);
1144         }
1145         else
1146         {
1147                 optionbyte &= ~(1<<2);
1148         }
1149
1150         if (stm32x_erase_options(bank) != ERROR_OK)
1151         {
1152                 command_print(cmd_ctx, "stm32x failed to erase options");
1153                 return ERROR_OK;
1154         }
1155
1156         stm32x_info->option_bytes.user_options = optionbyte;
1157
1158         if (stm32x_write_options(bank) != ERROR_OK)
1159         {
1160                 command_print(cmd_ctx, "stm32x failed to write options");
1161                 return ERROR_OK;
1162         }
1163
1164         command_print(cmd_ctx, "stm32x write options complete");
1165
1166         return ERROR_OK;
1167 }
1168
1169 int stm32x_mass_erase(struct flash_bank_s *bank)
1170 {
1171         target_t *target = bank->target;
1172         u32 status;
1173
1174         if (target->state != TARGET_HALTED)
1175         {
1176                 LOG_ERROR("Target not halted");
1177                 return ERROR_TARGET_NOT_HALTED;
1178         }
1179
1180         /* unlock option flash registers */
1181         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
1182         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
1183
1184         /* mass erase flash memory */
1185         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
1186         target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
1187
1188         status = stm32x_wait_status_busy(bank, 10);
1189
1190         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
1191
1192         if( status & FLASH_WRPRTERR )
1193         {
1194                 LOG_ERROR("stm32x device protected");
1195                 return ERROR_OK;
1196         }
1197
1198         if( status & FLASH_PGERR )
1199         {
1200                 LOG_ERROR("stm32x device programming failed");
1201                 return ERROR_OK;
1202         }
1203
1204         return ERROR_OK;
1205 }
1206
1207 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1208 {
1209         flash_bank_t *bank;
1210         int i;
1211
1212         if (argc < 1)
1213         {
1214                 command_print(cmd_ctx, "stm32x mass_erase <bank>");
1215                 return ERROR_OK;
1216         }
1217
1218         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1219         if (!bank)
1220         {
1221                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1222                 return ERROR_OK;
1223         }
1224
1225         if (stm32x_mass_erase(bank) == ERROR_OK)
1226         {
1227                 /* set all sectors as erased */
1228                 for (i = 0; i < bank->num_sectors; i++)
1229                 {
1230                         bank->sectors[i].is_erased = 1;
1231                 }
1232
1233                 command_print(cmd_ctx, "stm32x mass erase complete");
1234         }
1235         else
1236         {
1237                 command_print(cmd_ctx, "stm32x mass erase failed");
1238         }
1239
1240         return ERROR_OK;
1241 }