git.sur5r.net Git - openocd/blob - src/flash/stm32x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "stm32x.h"
  27 #include "flash.h"
  28 #include "target.h"
  29 #include "log.h"
  30 #include "armv7m.h"
  31 #include "algorithm.h"
  32 #include "binarybuffer.h"
  33
  34 #include <stdlib.h>
  35 #include <string.h>
  36
  37 int stm32x_register_commands(struct command_context_s *cmd_ctx);
  38 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  39 int stm32x_erase(struct flash_bank_s *bank, int first, int last);
  40 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last);
  41 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  42 int stm32x_probe(struct flash_bank_s *bank);
  43 int stm32x_auto_probe(struct flash_bank_s *bank);
  44 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45 int stm32x_protect_check(struct flash_bank_s *bank);
  46 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size);
  47
  48 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  49 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  51 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  53 int stm32x_mass_erase(struct flash_bank_s *bank);
  54
  55 flash_driver_t stm32x_flash =
  56 {
  57         .name = "stm32x",
  58         .register_commands = stm32x_register_commands,
  59         .flash_bank_command = stm32x_flash_bank_command,
  60         .erase = stm32x_erase,
  61         .protect = stm32x_protect,
  62         .write = stm32x_write,
  63         .probe = stm32x_probe,
  64         .auto_probe = stm32x_auto_probe,
  65         .erase_check = default_flash_mem_blank_check,
  66         .protect_check = stm32x_protect_check,
  67         .info = stm32x_info
  68 };
  69
  70 int stm32x_register_commands(struct command_context_s *cmd_ctx)
  71 {
  72         command_t *stm32x_cmd = register_command(cmd_ctx, NULL, "stm32x", NULL, COMMAND_ANY, "stm32x flash specific commands");
  73
  74         register_command(cmd_ctx, stm32x_cmd, "lock", stm32x_handle_lock_command, COMMAND_EXEC,
  75                                          "lock device");
  76         register_command(cmd_ctx, stm32x_cmd, "unlock", stm32x_handle_unlock_command, COMMAND_EXEC,
  77                                          "unlock protected device");
  78         register_command(cmd_ctx, stm32x_cmd, "mass_erase", stm32x_handle_mass_erase_command, COMMAND_EXEC,
  79                                          "mass erase device");
  80         register_command(cmd_ctx, stm32x_cmd, "options_read", stm32x_handle_options_read_command, COMMAND_EXEC,
  81                                          "read device option bytes");
  82         register_command(cmd_ctx, stm32x_cmd, "options_write", stm32x_handle_options_write_command, COMMAND_EXEC,
  83                                          "write device option bytes");
  84         return ERROR_OK;
  85 }
  86
  87 /* flash bank stm32x <base> <size> 0 0 <target#>
  88  */
  89 int stm32x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
  90 {
  91         stm32x_flash_bank_t *stm32x_info;
  92
  93         if (argc < 6)
  94         {
  95                 LOG_WARNING("incomplete flash_bank stm32x configuration");
  96                 return ERROR_FLASH_BANK_INVALID;
  97         }
  98
  99         stm32x_info = malloc(sizeof(stm32x_flash_bank_t));
 100         bank->driver_priv = stm32x_info;
 101
 102         stm32x_info->write_algorithm = NULL;
 103         stm32x_info->probed = 0;
 104
 105         return ERROR_OK;
 106 }
 107
 108 u32 stm32x_get_flash_status(flash_bank_t *bank)
 109 {
 110         target_t *target = bank->target;
 111         u32 status;
 112
 113         target_read_u32(target, STM32_FLASH_SR, &status);
 114
 115         return status;
 116 }
 117
 118 u32 stm32x_wait_status_busy(flash_bank_t *bank, int timeout)
 119 {
 120         u32 status;
 121
 122         /* wait for busy to clear */
 123         while (((status = stm32x_get_flash_status(bank)) & FLASH_BSY) && (timeout-- > 0))
 124         {
 125                 LOG_DEBUG("status: 0x%x", status);
 126                 usleep(1000);
 127         }
 128
 129         return status;
 130 }
 131
 132 int stm32x_read_options(struct flash_bank_s *bank)
 133 {
 134         u32 optiondata;
 135         stm32x_flash_bank_t *stm32x_info = NULL;
 136         target_t *target = bank->target;
 137
 138         stm32x_info = bank->driver_priv;
 139
 140         /* read current option bytes */
 141         target_read_u32(target, STM32_FLASH_OBR, &optiondata);
 142
 143         stm32x_info->option_bytes.user_options = (u16)0xFFF8|((optiondata >> 2) & 0x07);
 144         stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
 145
 146         if (optiondata & (1 << OPT_READOUT))
 147                 LOG_INFO("Device Security Bit Set");
 148
 149         /* each bit refers to a 4bank protection */
 150         target_read_u32(target, STM32_FLASH_WRPR, &optiondata);
 151
 152         stm32x_info->option_bytes.protection[0] = (u16)optiondata;
 153         stm32x_info->option_bytes.protection[1] = (u16)(optiondata >> 8);
 154         stm32x_info->option_bytes.protection[2] = (u16)(optiondata >> 16);
 155         stm32x_info->option_bytes.protection[3] = (u16)(optiondata >> 24);
 156
 157         return ERROR_OK;
 158 }
 159
 160 int stm32x_erase_options(struct flash_bank_s *bank)
 161 {
 162         stm32x_flash_bank_t *stm32x_info = NULL;
 163         target_t *target = bank->target;
 164         u32 status;
 165
 166         stm32x_info = bank->driver_priv;
 167
 168         /* read current options */
 169         stm32x_read_options(bank);
 170
 171         /* unlock flash registers */
 172         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 173         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 174
 175         /* unlock option flash registers */
 176         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 177         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 178
 179         /* erase option bytes */
 180         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_OPTWRE);
 181         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTER|FLASH_STRT|FLASH_OPTWRE);
 182
 183         status = stm32x_wait_status_busy(bank, 10);
 184
 185         if( status & FLASH_WRPRTERR )
 186                 return ERROR_FLASH_OPERATION_FAILED;
 187         if( status & FLASH_PGERR )
 188                 return ERROR_FLASH_OPERATION_FAILED;
 189
 190         /* clear readout protection and complementary option bytes
 191          * this will also force a device unlock if set */
 192         stm32x_info->option_bytes.RDP = 0x5AA5;
 193
 194         return ERROR_OK;
 195 }
 196
 197 int stm32x_write_options(struct flash_bank_s *bank)
 198 {
 199         stm32x_flash_bank_t *stm32x_info = NULL;
 200         target_t *target = bank->target;
 201         u32 status;
 202
 203         stm32x_info = bank->driver_priv;
 204
 205         /* unlock flash registers */
 206         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 207         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 208
 209         /* unlock option flash registers */
 210         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY1);
 211         target_write_u32(target, STM32_FLASH_OPTKEYR, KEY2);
 212
 213         /* program option bytes */
 214         target_write_u32(target, STM32_FLASH_CR, FLASH_OPTPG|FLASH_OPTWRE);
 215
 216         /* write user option byte */
 217         target_write_u16(target, STM32_OB_USER, stm32x_info->option_bytes.user_options);
 218
 219         status = stm32x_wait_status_busy(bank, 10);
 220
 221         if( status & FLASH_WRPRTERR )
 222                 return ERROR_FLASH_OPERATION_FAILED;
 223         if( status & FLASH_PGERR )
 224                 return ERROR_FLASH_OPERATION_FAILED;
 225
 226         /* write protection byte 1 */
 227         target_write_u16(target, STM32_OB_WRP0, stm32x_info->option_bytes.protection[0]);
 228
 229         status = stm32x_wait_status_busy(bank, 10);
 230
 231         if( status & FLASH_WRPRTERR )
 232                 return ERROR_FLASH_OPERATION_FAILED;
 233         if( status & FLASH_PGERR )
 234                 return ERROR_FLASH_OPERATION_FAILED;
 235
 236         /* write protection byte 2 */
 237         target_write_u16(target, STM32_OB_WRP1, stm32x_info->option_bytes.protection[1]);
 238
 239         status = stm32x_wait_status_busy(bank, 10);
 240
 241         if( status & FLASH_WRPRTERR )
 242                 return ERROR_FLASH_OPERATION_FAILED;
 243         if( status & FLASH_PGERR )
 244                 return ERROR_FLASH_OPERATION_FAILED;
 245
 246         /* write protection byte 3 */
 247         target_write_u16(target, STM32_OB_WRP2, stm32x_info->option_bytes.protection[2]);
 248
 249         status = stm32x_wait_status_busy(bank, 10);
 250
 251         if( status & FLASH_WRPRTERR )
 252                 return ERROR_FLASH_OPERATION_FAILED;
 253         if( status & FLASH_PGERR )
 254                 return ERROR_FLASH_OPERATION_FAILED;
 255
 256         /* write protection byte 4 */
 257         target_write_u16(target, STM32_OB_WRP3, stm32x_info->option_bytes.protection[3]);
 258
 259         status = stm32x_wait_status_busy(bank, 10);
 260
 261         if( status & FLASH_WRPRTERR )
 262                 return ERROR_FLASH_OPERATION_FAILED;
 263         if( status & FLASH_PGERR )
 264                 return ERROR_FLASH_OPERATION_FAILED;
 265
 266         /* write readout protection bit */
 267         target_write_u16(target, STM32_OB_RDP, stm32x_info->option_bytes.RDP);
 268
 269         status = stm32x_wait_status_busy(bank, 10);
 270
 271         if( status & FLASH_WRPRTERR )
 272                 return ERROR_FLASH_OPERATION_FAILED;
 273         if( status & FLASH_PGERR )
 274                 return ERROR_FLASH_OPERATION_FAILED;
 275
 276         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 277
 278         return ERROR_OK;
 279 }
 280
 281 int stm32x_protect_check(struct flash_bank_s *bank)
 282 {
 283         target_t *target = bank->target;
 284         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 285
 286         u32 protection;
 287         int i, s;
 288         int num_bits;
 289
 290         if (target->state != TARGET_HALTED)
 291         {
 292                 return ERROR_TARGET_NOT_HALTED;
 293         }
 294
 295         /* medium density - each bit refers to a 4bank protection
 296          * high density - each bit refers to a 2bank protection */
 297         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 298
 299         /* medium density - each protection bit is for 4 * 1K pages
 300          * high density - each protection bit is for 2 * 2K pages */
 301         num_bits = (bank->num_sectors / stm32x_info->ppage_size);
 302
 303         for (i = 0; i < num_bits; i++)
 304         {
 305                 int set = 1;
 306
 307                 if( protection & (1 << i))
 308                         set = 0;
 309
 310                 for (s = 0; s < stm32x_info->ppage_size; s++)
 311                         bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
 312         }
 313
 314         return ERROR_OK;
 315 }
 316
 317 int stm32x_erase(struct flash_bank_s *bank, int first, int last)
 318 {
 319         target_t *target = bank->target;
 320         int i;
 321         u32 status;
 322
 323         if (bank->target->state != TARGET_HALTED)
 324         {
 325                 return ERROR_TARGET_NOT_HALTED;
 326         }
 327
 328         if ((first == 0) && (last == (bank->num_sectors - 1)))
 329         {
 330                 return stm32x_mass_erase(bank);
 331         }
 332
 333         /* unlock flash registers */
 334         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 335         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 336
 337         for (i = first; i <= last; i++)
 338         {
 339                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER);
 340                 target_write_u32(target, STM32_FLASH_AR, bank->base + bank->sectors[i].offset);
 341                 target_write_u32(target, STM32_FLASH_CR, FLASH_PER|FLASH_STRT);
 342
 343                 status = stm32x_wait_status_busy(bank, 10);
 344
 345                 if( status & FLASH_WRPRTERR )
 346                         return ERROR_FLASH_OPERATION_FAILED;
 347                 if( status & FLASH_PGERR )
 348                         return ERROR_FLASH_OPERATION_FAILED;
 349                 bank->sectors[i].is_erased = 1;
 350         }
 351
 352         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 353
 354         return ERROR_OK;
 355 }
 356
 357 int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 358 {
 359         stm32x_flash_bank_t *stm32x_info = NULL;
 360         target_t *target = bank->target;
 361         u16 prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
 362         int i, reg, bit;
 363         int status;
 364         u32 protection;
 365
 366         stm32x_info = bank->driver_priv;
 367
 368         if (target->state != TARGET_HALTED)
 369         {
 370                 return ERROR_TARGET_NOT_HALTED;
 371         }
 372
 373         if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
 374         {
 375                 LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
 376                 return ERROR_FLASH_SECTOR_INVALID;
 377         }
 378
 379         /* medium density - each bit refers to a 4bank protection
 380          * high density - each bit refers to a 2bank protection */
 381         target_read_u32(target, STM32_FLASH_WRPR, &protection);
 382
 383         prot_reg[0] = (u16)protection;
 384         prot_reg[1] = (u16)(protection >> 8);
 385         prot_reg[2] = (u16)(protection >> 16);
 386         prot_reg[3] = (u16)(protection >> 24);
 387
 388         if (stm32x_info->ppage_size == 2)
 389         {
 390                 /* high density flash */
 391
 392                 /* bit 7 controls sector 62 - 255 protection */
 393                 if (first > 61 || last <= 255)
 394                         prot_reg[3] |= (1 << 7);
 395
 396                 if (first > 61)
 397                         first = 61;
 398                 if (last > 61)
 399                         last = 61;
 400
 401                 for (i = first; i <= last; i++)
 402                 {
 403                         reg = (i / stm32x_info->ppage_size) / 8;
 404                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 405
 406                         if( set )
 407                                 prot_reg[reg] &= ~(1 << bit);
 408                         else
 409                                 prot_reg[reg] |= (1 << bit);
 410                 }
 411         }
 412         else
 413         {
 414                 /* medium density flash */
 415                 for (i = first; i <= last; i++)
 416                 {
 417                         reg = (i / stm32x_info->ppage_size) / 8;
 418                         bit = (i / stm32x_info->ppage_size) - (reg * 8);
 419
 420                         if( set )
 421                                 prot_reg[reg] &= ~(1 << bit);
 422                         else
 423                                 prot_reg[reg] |= (1 << bit);
 424                 }
 425         }
 426
 427         if ((status = stm32x_erase_options(bank)) != ERROR_OK)
 428                 return status;
 429
 430         stm32x_info->option_bytes.protection[0] = prot_reg[0];
 431         stm32x_info->option_bytes.protection[1] = prot_reg[1];
 432         stm32x_info->option_bytes.protection[2] = prot_reg[2];
 433         stm32x_info->option_bytes.protection[3] = prot_reg[3];
 434
 435         return stm32x_write_options(bank);
 436 }
 437
 438 int stm32x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 439 {
 440         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 441         target_t *target = bank->target;
 442         u32 buffer_size = 8192;
 443         working_area_t *source;
 444         u32 address = bank->base + offset;
 445         reg_param_t reg_params[4];
 446         armv7m_algorithm_t armv7m_info;
 447         int retval = ERROR_OK;
 448
 449         u8 stm32x_flash_write_code[] = {
 450                                                                         /* write: */
 451                 0xDF, 0xF8, 0x24, 0x40,         /* ldr  r4, STM32_FLASH_CR */
 452                 0x09, 0x4D,                                     /* ldr  r5, STM32_FLASH_SR */
 453                 0x4F, 0xF0, 0x01, 0x03,         /* mov  r3, #1 */
 454                 0x23, 0x60,                                     /* str  r3, [r4, #0] */
 455                 0x30, 0xF8, 0x02, 0x3B,         /* ldrh r3, [r0], #2 */
 456                 0x21, 0xF8, 0x02, 0x3B,         /* strh r3, [r1], #2 */
 457                                                                         /* busy: */
 458                 0x2B, 0x68,                                     /* ldr  r3, [r5, #0] */
 459                 0x13, 0xF0, 0x01, 0x0F,         /* tst  r3, #0x01 */
 460                 0xFB, 0xD0,                                     /* beq  busy */
 461                 0x13, 0xF0, 0x14, 0x0F,         /* tst  r3, #0x14 */
 462                 0x01, 0xD1,                                     /* bne  exit */
 463                 0x01, 0x3A,                                     /* subs r2, r2, #1 */
 464                 0xED, 0xD1,                                     /* bne  write */
 465                                                                         /* exit: */
 466                 0xFE, 0xE7,                                     /* b exit */
 467                 0x10, 0x20, 0x02, 0x40,         /* STM32_FLASH_CR:      .word 0x40022010 */
 468                 0x0C, 0x20, 0x02, 0x40          /* STM32_FLASH_SR:      .word 0x4002200C */
 469         };
 470
 471         /* flash write code */
 472         if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code), &stm32x_info->write_algorithm) != ERROR_OK)
 473         {
 474                 LOG_WARNING("no working area available, can't do block memory writes");
 475                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 476         };
 477
 478         if ((retval=target_write_buffer(target, stm32x_info->write_algorithm->address, sizeof(stm32x_flash_write_code), stm32x_flash_write_code))!=ERROR_OK)
 479                 return retval;
 480
 481         /* memory buffer */
 482         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
 483         {
 484                 buffer_size /= 2;
 485                 if (buffer_size <= 256)
 486                 {
 487                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
 488                         if (stm32x_info->write_algorithm)
 489                                 target_free_working_area(target, stm32x_info->write_algorithm);
 490
 491                         LOG_WARNING("no large enough working area available, can't do block memory writes");
 492                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 493                 }
 494         };
 495
 496         armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
 497         armv7m_info.core_mode = ARMV7M_MODE_ANY;
 498
 499         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
 500         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
 501         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
 502         init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
 503
 504         while (count > 0)
 505         {
 506                 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
 507
 508                 if ((retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer))!=ERROR_OK)
 509                         break;
 510
 511                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
 512                 buf_set_u32(reg_params[1].value, 0, 32, address);
 513                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
 514
 515                 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, stm32x_info->write_algorithm->address, \
 516                                 stm32x_info->write_algorithm->address + (sizeof(stm32x_flash_write_code) - 10), 10000, &armv7m_info)) != ERROR_OK)
 517                 {
 518                         LOG_ERROR("error executing stm32x flash write algorithm");
 519                         retval = ERROR_FLASH_OPERATION_FAILED;
 520                         break;
 521                 }
 522
 523                 if (buf_get_u32(reg_params[3].value, 0, 32) & 0x14)
 524                 {
 525                         retval = ERROR_FLASH_OPERATION_FAILED;
 526                         break;
 527                 }
 528
 529                 buffer += thisrun_count * 2;
 530                 address += thisrun_count * 2;
 531                 count -= thisrun_count;
 532         }
 533
 534         target_free_working_area(target, source);
 535         target_free_working_area(target, stm32x_info->write_algorithm);
 536
 537         destroy_reg_param(&reg_params[0]);
 538         destroy_reg_param(&reg_params[1]);
 539         destroy_reg_param(&reg_params[2]);
 540         destroy_reg_param(&reg_params[3]);
 541
 542         return retval;
 543 }
 544
 545 int stm32x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
 546 {
 547         target_t *target = bank->target;
 548         u32 words_remaining = (count / 2);
 549         u32 bytes_remaining = (count & 0x00000001);
 550         u32 address = bank->base + offset;
 551         u32 bytes_written = 0;
 552         u8 status;
 553         u32 retval;
 554
 555         if (bank->target->state != TARGET_HALTED)
 556         {
 557                 return ERROR_TARGET_NOT_HALTED;
 558         }
 559
 560         if (offset & 0x1)
 561         {
 562                 LOG_WARNING("offset 0x%x breaks required 2-byte alignment", offset);
 563                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 564         }
 565
 566         /* unlock flash registers */
 567         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 568         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 569
 570         /* multiple half words (2-byte) to be programmed? */
 571         if (words_remaining > 0)
 572         {
 573                 /* try using a block write */
 574                 if ((retval = stm32x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
 575                 {
 576                         if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 577                         {
 578                                 /* if block write failed (no sufficient working area),
 579                                  * we use normal (slow) single dword accesses */
 580                                 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 581                         }
 582                         else if (retval == ERROR_FLASH_OPERATION_FAILED)
 583                         {
 584                                 LOG_ERROR("flash writing failed with error code: 0x%x", retval);
 585                                 return ERROR_FLASH_OPERATION_FAILED;
 586                         }
 587                 }
 588                 else
 589                 {
 590                         buffer += words_remaining * 2;
 591                         address += words_remaining * 2;
 592                         words_remaining = 0;
 593                 }
 594         }
 595
 596         while (words_remaining > 0)
 597         {
 598                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 599                 target_write_u16(target, address, *(u16*)(buffer + bytes_written));
 600
 601                 status = stm32x_wait_status_busy(bank, 5);
 602
 603                 if( status & FLASH_WRPRTERR )
 604                         return ERROR_FLASH_OPERATION_FAILED;
 605                 if( status & FLASH_PGERR )
 606                         return ERROR_FLASH_OPERATION_FAILED;
 607
 608                 bytes_written += 2;
 609                 words_remaining--;
 610                 address += 2;
 611         }
 612
 613         if (bytes_remaining)
 614         {
 615                 u8 last_halfword[2] = {0xff, 0xff};
 616                 int i = 0;
 617
 618                 while(bytes_remaining > 0)
 619                 {
 620                         last_halfword[i++] = *(buffer + bytes_written);
 621                         bytes_remaining--;
 622                         bytes_written++;
 623                 }
 624
 625                 target_write_u32(target, STM32_FLASH_CR, FLASH_PG);
 626                 target_write_u16(target, address, *(u16*)last_halfword);
 627
 628                 status = stm32x_wait_status_busy(bank, 5);
 629
 630                 if( status & FLASH_WRPRTERR )
 631                         return ERROR_FLASH_OPERATION_FAILED;
 632                 if( status & FLASH_PGERR )
 633                         return ERROR_FLASH_OPERATION_FAILED;
 634         }
 635
 636         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 637
 638         return ERROR_OK;
 639 }
 640
 641 int stm32x_probe(struct flash_bank_s *bank)
 642 {
 643         target_t *target = bank->target;
 644         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 645         int i;
 646         u16 num_pages;
 647         u32 device_id;
 648         int page_size;
 649
 650         if (bank->target->state != TARGET_HALTED)
 651         {
 652                 return ERROR_TARGET_NOT_HALTED;
 653         }
 654
 655         stm32x_info->probed = 0;
 656
 657         /* read stm32 device id register */
 658         target_read_u32(target, 0xE0042000, &device_id);
 659         LOG_INFO( "device id = 0x%08x", device_id );
 660
 661         /* get flash size from target */
 662         if (target_read_u16(target, 0x1FFFF7E0, &num_pages) != ERROR_OK)
 663         {
 664                 /* failed reading flash size, default to max target family */
 665                 num_pages = 0xffff;
 666         }
 667
 668         if ((device_id & 0x7ff) == 0x410)
 669         {
 670                 /* medium density - we have 1k pages
 671                  * 4 pages for a protection area */
 672                 page_size = 1024;
 673                 stm32x_info->ppage_size = 4;
 674
 675                 /* check for early silicon */
 676                 if (num_pages == 0xffff)
 677                 {
 678                         /* number of sectors incorrect on revA */
 679                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 128k flash" );
 680                         num_pages = 128;
 681                 }
 682         }
 683         else if ((device_id & 0x7ff) == 0x414)
 684         {
 685                 /* high density - we have 2k pages
 686                  * 2 pages for a protection area */
 687                 page_size = 2048;
 688                 stm32x_info->ppage_size = 2;
 689
 690                 /* check for early silicon */
 691                 if (num_pages == 0xffff)
 692                 {
 693                         /* number of sectors incorrect on revZ */
 694                         LOG_WARNING( "STM32 flash size failed, probe inaccurate - assuming 512k flash" );
 695                         num_pages = 512;
 696                 }
 697         }
 698         else
 699         {
 700                 LOG_WARNING( "Cannot identify target as a STM32 family." );
 701                 return ERROR_FLASH_OPERATION_FAILED;
 702         }
 703
 704         LOG_INFO( "flash size = %dkbytes", num_pages );
 705
 706         /* calculate numbers of pages */
 707         num_pages /= (page_size / 1024);
 708
 709         bank->base = 0x08000000;
 710         bank->size = (num_pages * page_size);
 711         bank->num_sectors = num_pages;
 712         bank->sectors = malloc(sizeof(flash_sector_t) * num_pages);
 713
 714         for (i = 0; i < num_pages; i++)
 715         {
 716                 bank->sectors[i].offset = i * page_size;
 717                 bank->sectors[i].size = page_size;
 718                 bank->sectors[i].is_erased = -1;
 719                 bank->sectors[i].is_protected = 1;
 720         }
 721
 722         stm32x_info->probed = 1;
 723
 724         return ERROR_OK;
 725 }
 726
 727 int stm32x_auto_probe(struct flash_bank_s *bank)
 728 {
 729         stm32x_flash_bank_t *stm32x_info = bank->driver_priv;
 730         if (stm32x_info->probed)
 731                 return ERROR_OK;
 732         return stm32x_probe(bank);
 733 }
 734
 735 int stm32x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 736 {
 737         return ERROR_OK;
 738 }
 739
 740 int stm32x_info(struct flash_bank_s *bank, char *buf, int buf_size)
 741 {
 742         snprintf(buf, buf_size, "stm32x flash driver info" );
 743         return ERROR_OK;
 744 }
 745
 746 int stm32x_handle_lock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 747 {
 748         flash_bank_t *bank;
 749         target_t *target = NULL;
 750         stm32x_flash_bank_t *stm32x_info = NULL;
 751
 752         if (argc < 1)
 753         {
 754                 command_print(cmd_ctx, "stm32x lock <bank>");
 755                 return ERROR_OK;
 756         }
 757
 758         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 759         if (!bank)
 760         {
 761                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 762                 return ERROR_OK;
 763         }
 764
 765         stm32x_info = bank->driver_priv;
 766
 767         target = bank->target;
 768
 769         if (target->state != TARGET_HALTED)
 770         {
 771                 return ERROR_TARGET_NOT_HALTED;
 772         }
 773
 774         if (stm32x_erase_options(bank) != ERROR_OK)
 775         {
 776                 command_print(cmd_ctx, "stm32x failed to erase options");
 777                 return ERROR_OK;
 778         }
 779
 780         /* set readout protection */
 781         stm32x_info->option_bytes.RDP = 0;
 782
 783         if (stm32x_write_options(bank) != ERROR_OK)
 784         {
 785                 command_print(cmd_ctx, "stm32x failed to lock device");
 786                 return ERROR_OK;
 787         }
 788
 789         command_print(cmd_ctx, "stm32x locked");
 790
 791         return ERROR_OK;
 792 }
 793
 794 int stm32x_handle_unlock_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 795 {
 796         flash_bank_t *bank;
 797         target_t *target = NULL;
 798         stm32x_flash_bank_t *stm32x_info = NULL;
 799
 800         if (argc < 1)
 801         {
 802                 command_print(cmd_ctx, "stm32x unlock <bank>");
 803                 return ERROR_OK;
 804         }
 805
 806         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 807         if (!bank)
 808         {
 809                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 810                 return ERROR_OK;
 811         }
 812
 813         stm32x_info = bank->driver_priv;
 814
 815         target = bank->target;
 816
 817         if (target->state != TARGET_HALTED)
 818         {
 819                 return ERROR_TARGET_NOT_HALTED;
 820         }
 821
 822         if (stm32x_erase_options(bank) != ERROR_OK)
 823         {
 824                 command_print(cmd_ctx, "stm32x failed to unlock device");
 825                 return ERROR_OK;
 826         }
 827
 828         if (stm32x_write_options(bank) != ERROR_OK)
 829         {
 830                 command_print(cmd_ctx, "stm32x failed to lock device");
 831                 return ERROR_OK;
 832         }
 833
 834         command_print(cmd_ctx, "stm32x unlocked");
 835
 836         return ERROR_OK;
 837 }
 838
 839 int stm32x_handle_options_read_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 840 {
 841         flash_bank_t *bank;
 842         u32 optionbyte;
 843         target_t *target = NULL;
 844         stm32x_flash_bank_t *stm32x_info = NULL;
 845
 846         if (argc < 1)
 847         {
 848                 command_print(cmd_ctx, "stm32x options_read <bank>");
 849                 return ERROR_OK;
 850         }
 851
 852         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 853         if (!bank)
 854         {
 855                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 856                 return ERROR_OK;
 857         }
 858
 859         stm32x_info = bank->driver_priv;
 860
 861         target = bank->target;
 862
 863         if (target->state != TARGET_HALTED)
 864         {
 865                 return ERROR_TARGET_NOT_HALTED;
 866         }
 867
 868         target_read_u32(target, STM32_FLASH_OBR, &optionbyte);
 869         command_print(cmd_ctx, "Option Byte: 0x%x", optionbyte);
 870
 871         if (buf_get_u32((u8*)&optionbyte, OPT_ERROR, 1))
 872                 command_print(cmd_ctx, "Option Byte Complement Error");
 873
 874         if (buf_get_u32((u8*)&optionbyte, OPT_READOUT, 1))
 875                 command_print(cmd_ctx, "Readout Protection On");
 876         else
 877                 command_print(cmd_ctx, "Readout Protection Off");
 878
 879         if (buf_get_u32((u8*)&optionbyte, OPT_RDWDGSW, 1))
 880                 command_print(cmd_ctx, "Software Watchdog");
 881         else
 882                 command_print(cmd_ctx, "Hardware Watchdog");
 883
 884         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTOP, 1))
 885                 command_print(cmd_ctx, "Stop: No reset generated");
 886         else
 887                 command_print(cmd_ctx, "Stop: Reset generated");
 888
 889         if (buf_get_u32((u8*)&optionbyte, OPT_RDRSTSTDBY, 1))
 890                 command_print(cmd_ctx, "Standby: No reset generated");
 891         else
 892                 command_print(cmd_ctx, "Standby: Reset generated");
 893
 894         return ERROR_OK;
 895 }
 896
 897 int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 898 {
 899         flash_bank_t *bank;
 900         target_t *target = NULL;
 901         stm32x_flash_bank_t *stm32x_info = NULL;
 902         u16 optionbyte = 0xF8;
 903
 904         if (argc < 4)
 905         {
 906                 command_print(cmd_ctx, "stm32x options_write <bank> <SWWDG|HWWDG> <RSTSTNDBY|NORSTSTNDBY> <RSTSTOP|NORSTSTOP>");
 907                 return ERROR_OK;
 908         }
 909
 910         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
 911         if (!bank)
 912         {
 913                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 914                 return ERROR_OK;
 915         }
 916
 917         stm32x_info = bank->driver_priv;
 918
 919         target = bank->target;
 920
 921         if (target->state != TARGET_HALTED)
 922         {
 923                 return ERROR_TARGET_NOT_HALTED;
 924         }
 925
 926         if (strcmp(args[1], "SWWDG") == 0)
 927         {
 928                 optionbyte |= (1<<0);
 929         }
 930         else
 931         {
 932                 optionbyte &= ~(1<<0);
 933         }
 934
 935         if (strcmp(args[2], "NORSTSTNDBY") == 0)
 936         {
 937                 optionbyte |= (1<<1);
 938         }
 939         else
 940         {
 941                 optionbyte &= ~(1<<1);
 942         }
 943
 944         if (strcmp(args[3], "NORSTSTOP") == 0)
 945         {
 946                 optionbyte |= (1<<2);
 947         }
 948         else
 949         {
 950                 optionbyte &= ~(1<<2);
 951         }
 952
 953         if (stm32x_erase_options(bank) != ERROR_OK)
 954         {
 955                 command_print(cmd_ctx, "stm32x failed to erase options");
 956                 return ERROR_OK;
 957         }
 958
 959         stm32x_info->option_bytes.user_options = optionbyte;
 960
 961         if (stm32x_write_options(bank) != ERROR_OK)
 962         {
 963                 command_print(cmd_ctx, "stm32x failed to write options");
 964                 return ERROR_OK;
 965         }
 966
 967         command_print(cmd_ctx, "stm32x write options complete");
 968
 969         return ERROR_OK;
 970 }
 971
 972 int stm32x_mass_erase(struct flash_bank_s *bank)
 973 {
 974         target_t *target = bank->target;
 975         u32 status;
 976
 977         if (target->state != TARGET_HALTED)
 978         {
 979                 return ERROR_TARGET_NOT_HALTED;
 980         }
 981
 982         /* unlock option flash registers */
 983         target_write_u32(target, STM32_FLASH_KEYR, KEY1);
 984         target_write_u32(target, STM32_FLASH_KEYR, KEY2);
 985
 986         /* mass erase flash memory */
 987         target_write_u32(target, STM32_FLASH_CR, FLASH_MER);
 988         target_write_u32(target, STM32_FLASH_CR, FLASH_MER|FLASH_STRT);
 989
 990         status = stm32x_wait_status_busy(bank, 10);
 991
 992         target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
 993
 994         if( status & FLASH_WRPRTERR )
 995         {
 996                 LOG_ERROR("stm32x device protected");
 997                 return ERROR_OK;
 998         }
 999
1000         if( status & FLASH_PGERR )
1001         {
1002                 LOG_ERROR("stm32x device programming failed");
1003                 return ERROR_OK;
1004         }
1005
1006         return ERROR_OK;
1007 }
1008
1009 int stm32x_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1010 {
1011         flash_bank_t *bank;
1012         int i;
1013
1014         if (argc < 1)
1015         {
1016                 command_print(cmd_ctx, "stm32x mass_erase <bank>");
1017                 return ERROR_OK;
1018         }
1019
1020         bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
1021         if (!bank)
1022         {
1023                 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
1024                 return ERROR_OK;
1025         }
1026
1027         if (stm32x_mass_erase(bank) == ERROR_OK)
1028         {
1029                 /* set all sectors as erased */
1030                 for (i = 0; i < bank->num_sectors; i++)
1031                 {
1032                         bank->sectors[i].is_erased = 1;
1033                 }
1034
1035                 command_print(cmd_ctx, "stm32x mass erase complete");
1036         }
1037         else
1038         {
1039                 command_print(cmd_ctx, "stm32x mass erase failed");
1040         }
1041
1042         return ERROR_OK;
1043 }