1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
39 str9x_mem_layout_t mem_layout_str9bank0[] = {
40 {0x00000000, 0x10000, 0x01},
41 {0x00010000, 0x10000, 0x02},
42 {0x00020000, 0x10000, 0x04},
43 {0x00030000, 0x10000, 0x08},
44 {0x00040000, 0x10000, 0x10},
45 {0x00050000, 0x10000, 0x20},
46 {0x00060000, 0x10000, 0x40},
47 {0x00070000, 0x10000, 0x80},
50 str9x_mem_layout_t mem_layout_str9bank1[] = {
51 {0x00000000, 0x02000, 0x100},
52 {0x00002000, 0x02000, 0x200},
53 {0x00004000, 0x02000, 0x400},
54 {0x00006000, 0x02000, 0x800}
57 static u32 bank1start = 0x00080000;
59 int str9x_register_commands(struct command_context_s *cmd_ctx);
60 int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
61 int str9x_erase(struct flash_bank_s *bank, int first, int last);
62 int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
63 int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
64 int str9x_probe(struct flash_bank_s *bank);
65 int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
66 int str9x_protect_check(struct flash_bank_s *bank);
67 int str9x_erase_check(struct flash_bank_s *bank);
68 int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
70 int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
72 flash_driver_t str9x_flash =
75 .register_commands = str9x_register_commands,
76 .flash_bank_command = str9x_flash_bank_command,
78 .protect = str9x_protect,
81 .erase_check = str9x_erase_check,
82 .protect_check = str9x_protect_check,
86 int str9x_register_commands(struct command_context_s *cmd_ctx)
88 command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
90 register_command(cmd_ctx, str9x_cmd, "flash_config", str9x_handle_flash_config_command, COMMAND_EXEC,
91 "configure str9 flash controller");
96 int str9x_build_block_list(struct flash_bank_s *bank)
98 str9x_flash_bank_t *str9x_info = bank->driver_priv;
102 int b0_sectors = 0, b1_sectors = 0;
114 bank1start = bank->base;
117 ERROR("BUG: unknown bank->size encountered");
121 num_sectors = b0_sectors + b1_sectors;
123 bank->num_sectors = num_sectors;
124 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
125 str9x_info->sector_bits = malloc(sizeof(u32) * num_sectors);
129 for (i = 0; i < b0_sectors; i++)
131 bank->sectors[num_sectors].offset = mem_layout_str9bank0[i].sector_start;
132 bank->sectors[num_sectors].size = mem_layout_str9bank0[i].sector_size;
133 bank->sectors[num_sectors].is_erased = -1;
134 bank->sectors[num_sectors].is_protected = 1;
135 str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank0[i].sector_bit;
138 for (i = 0; i < b1_sectors; i++)
140 bank->sectors[num_sectors].offset = mem_layout_str9bank1[i].sector_start;
141 bank->sectors[num_sectors].size = mem_layout_str9bank1[i].sector_size;
142 bank->sectors[num_sectors].is_erased = -1;
143 bank->sectors[num_sectors].is_protected = 1;
144 str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank1[i].sector_bit;
150 /* flash bank str9x <base> <size> 0 0 <target#>
152 int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
154 str9x_flash_bank_t *str9x_info;
158 WARNING("incomplete flash_bank str9x configuration");
159 return ERROR_FLASH_BANK_INVALID;
162 str9x_info = malloc(sizeof(str9x_flash_bank_t));
163 bank->driver_priv = str9x_info;
165 str9x_build_block_list(bank);
167 str9x_info->write_algorithm = NULL;
172 int str9x_blank_check(struct flash_bank_s *bank, int first, int last)
174 target_t *target = bank->target;
179 if ((first < 0) || (last > bank->num_sectors))
180 return ERROR_FLASH_SECTOR_INVALID;
182 if (bank->target->state != TARGET_HALTED)
184 return ERROR_TARGET_NOT_HALTED;
187 buffer = malloc(256);
189 for (i = first; i <= last; i++)
191 bank->sectors[i].is_erased = 1;
193 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
195 for (nBytes = 0; nBytes < 256; nBytes++)
197 if (buffer[nBytes] != 0xFF)
199 bank->sectors[i].is_erased = 0;
210 int str9x_protect_check(struct flash_bank_s *bank)
212 str9x_flash_bank_t *str9x_info = bank->driver_priv;
213 target_t *target = bank->target;
219 if (bank->target->state != TARGET_HALTED)
221 return ERROR_TARGET_NOT_HALTED;
224 /* read level one protection */
226 adr = bank1start + 0x10;
228 target_write_u16(target, adr, 0x90);
229 target_read_u16(target, adr, &status);
230 target_write_u16(target, adr, 0xFF);
232 for (i = 0; i < bank->num_sectors; i++)
234 if (status & str9x_info->sector_bits[i])
235 bank->sectors[i].is_protected = 1;
237 bank->sectors[i].is_protected = 0;
243 int str9x_erase(struct flash_bank_s *bank, int first, int last)
245 target_t *target = bank->target;
250 if (bank->target->state != TARGET_HALTED)
252 return ERROR_TARGET_NOT_HALTED;
255 for (i = first; i <= last; i++)
257 adr = bank->base + bank->sectors[i].offset;
260 target_write_u16(target, adr, 0x20);
261 target_write_u16(target, adr, 0xD0);
264 target_write_u16(target, adr, 0x70);
267 target_read_u8(target, adr, &status);
273 /* clear status, also clear read array */
274 target_write_u16(target, adr, 0x50);
276 /* read array command */
277 target_write_u16(target, adr, 0xFF);
281 ERROR("error erasing flash bank, status: 0x%x", status);
282 return ERROR_FLASH_OPERATION_FAILED;
286 for (i = first; i <= last; i++)
287 bank->sectors[i].is_erased = 1;
292 int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)
294 target_t *target = bank->target;
299 if (bank->target->state != TARGET_HALTED)
301 return ERROR_TARGET_NOT_HALTED;
304 for (i = first; i <= last; i++)
306 /* Level One Protection */
308 adr = bank->base + bank->sectors[i].offset;
310 target_write_u16(target, adr, 0x60);
312 target_write_u16(target, adr, 0x01);
314 target_write_u16(target, adr, 0xD0);
317 target_read_u8(target, adr, &status);
323 int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
325 str9x_flash_bank_t *str9x_info = bank->driver_priv;
326 target_t *target = bank->target;
327 u32 buffer_size = 8192;
328 working_area_t *source;
329 u32 address = bank->base + offset;
330 reg_param_t reg_params[4];
331 armv4_5_algorithm_t armv4_5_info;
334 u32 str9x_flash_write_code[] = {
336 0xe3c14003, /* bic r4, r1, #3 */
337 0xe3a03040, /* mov r3, #0x40 */
338 0xe1c430b0, /* strh r3, [r4, #0] */
339 0xe0d030b2, /* ldrh r3, [r0], #2 */
340 0xe0c130b2, /* strh r3, [r1], #2 */
341 0xe3a03070, /* mov r3, #0x70 */
342 0xe1c430b0, /* strh r3, [r4, #0] */
344 0xe5d43000, /* ldrb r3, [r4, #0] */
345 0xe3130080, /* tst r3, #0x80 */
346 0x0afffffc, /* beq busy */
347 0xe3a05050, /* mov r5, #0x50 */
348 0xe1c450b0, /* strh r5, [r4, #0] */
349 0xe3a050ff, /* mov r5, #0xFF */
350 0xe1c450b0, /* strh r5, [r4, #0] */
351 0xe3130012, /* tst r3, #0x12 */
352 0x1a000001, /* bne exit */
353 0xe2522001, /* subs r2, r2, #1 */
354 0x1affffed, /* bne write */
356 0xeafffffe, /* b exit */
359 /* flash write code */
360 if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
362 WARNING("no working area available, can't do block memory writes");
363 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
366 target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (u8*)str9x_flash_write_code);
369 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
372 if (buffer_size <= 256)
374 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
375 if (str9x_info->write_algorithm)
376 target_free_working_area(target, str9x_info->write_algorithm);
378 WARNING("no large enough working area available, can't do block memory writes");
379 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
383 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
384 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
385 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
387 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
388 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
389 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
390 init_reg_param(®_params[3], "r3", 32, PARAM_IN);
394 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
396 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
398 buf_set_u32(reg_params[0].value, 0, 32, source->address);
399 buf_set_u32(reg_params[1].value, 0, 32, address);
400 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
402 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
404 target_free_working_area(target, source);
405 target_free_working_area(target, str9x_info->write_algorithm);
406 ERROR("error executing str9x flash write algorithm");
407 return ERROR_FLASH_OPERATION_FAILED;
410 if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
412 return ERROR_FLASH_OPERATION_FAILED;
415 buffer += thisrun_count * 2;
416 address += thisrun_count * 2;
417 count -= thisrun_count;
420 target_free_working_area(target, source);
421 target_free_working_area(target, str9x_info->write_algorithm);
423 destroy_reg_param(®_params[0]);
424 destroy_reg_param(®_params[1]);
425 destroy_reg_param(®_params[2]);
426 destroy_reg_param(®_params[3]);
431 int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
433 target_t *target = bank->target;
434 u32 words_remaining = (count / 2);
435 u32 bytes_remaining = (count & 0x00000001);
436 u32 address = bank->base + offset;
437 u32 bytes_written = 0;
440 u32 check_address = offset;
444 if (bank->target->state != TARGET_HALTED)
446 return ERROR_TARGET_NOT_HALTED;
451 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
452 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
455 for (i = 0; i < bank->num_sectors; i++)
457 u32 sec_start = bank->sectors[i].offset;
458 u32 sec_end = sec_start + bank->sectors[i].size;
460 /* check if destination falls within the current sector */
461 if ((check_address >= sec_start) && (check_address < sec_end))
463 /* check if destination ends in the current sector */
464 if (offset + count < sec_end)
465 check_address = offset + count;
467 check_address = sec_end;
471 if (check_address != offset + count)
472 return ERROR_FLASH_DST_OUT_OF_BANK;
474 /* multiple half words (2-byte) to be programmed? */
475 if (words_remaining > 0)
477 /* try using a block write */
478 if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
480 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
482 /* if block write failed (no sufficient working area),
483 * we use normal (slow) single dword accesses */
484 WARNING("couldn't use block writes, falling back to single memory accesses");
486 else if (retval == ERROR_FLASH_OPERATION_FAILED)
488 ERROR("flash writing failed with error code: 0x%x", retval);
489 return ERROR_FLASH_OPERATION_FAILED;
494 buffer += words_remaining * 2;
495 address += words_remaining * 2;
500 while (words_remaining > 0)
502 bank_adr = address & ~0x03;
504 /* write data command */
505 target_write_u16(target, bank_adr, 0x40);
506 target->type->write_memory(target, address, 2, 1, buffer + bytes_written);
508 /* get status command */
509 target_write_u16(target, bank_adr, 0x70);
512 target_read_u8(target, bank_adr, &status);
518 /* clear status reg and read array */
519 target_write_u16(target, bank_adr, 0x50);
520 target_write_u16(target, bank_adr, 0xFF);
523 return ERROR_FLASH_OPERATION_FAILED;
524 else if (status & 0x02)
525 return ERROR_FLASH_OPERATION_FAILED;
534 u8 last_halfword[2] = {0xff, 0xff};
537 while(bytes_remaining > 0)
539 last_halfword[i++] = *(buffer + bytes_written);
544 bank_adr = address & ~0x03;
546 /* write data comamnd */
547 target_write_u16(target, bank_adr, 0x40);
548 target->type->write_memory(target, address, 2, 1, last_halfword);
550 /* query status command */
551 target_write_u16(target, bank_adr, 0x70);
554 target_read_u8(target, bank_adr, &status);
560 /* clear status reg and read array */
561 target_write_u16(target, bank_adr, 0x50);
562 target_write_u16(target, bank_adr, 0xFF);
565 return ERROR_FLASH_OPERATION_FAILED;
566 else if (status & 0x02)
567 return ERROR_FLASH_OPERATION_FAILED;
573 int str9x_probe(struct flash_bank_s *bank)
578 int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
583 int str9x_erase_check(struct flash_bank_s *bank)
585 return str9x_blank_check(bank, 0, bank->num_sectors - 1);
588 int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
590 snprintf(buf, buf_size, "str9x flash driver info" );
594 int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
596 str9x_flash_bank_t *str9x_info;
598 target_t *target = NULL;
602 command_print(cmd_ctx, "usage: str9x flash_config <bank> <bbsize> <nbsize> <bbstart> <nbstart>");
606 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
609 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
613 str9x_info = bank->driver_priv;
615 target = bank->target;
617 if (bank->target->state != TARGET_HALTED)
619 return ERROR_TARGET_NOT_HALTED;
622 /* config flash controller */
623 target_write_u32(target, FLASH_BBSR, strtoul(args[1], NULL, 0));
624 target_write_u32(target, FLASH_NBBSR, strtoul(args[2], NULL, 0));
625 target_write_u32(target, FLASH_BBADR, (strtoul(args[3], NULL, 0) >> 2));
626 target_write_u32(target, FLASH_NBBADR, (strtoul(args[4], NULL, 0) >> 2));
628 /* set bit 18 instruction TCM order as per flash programming manual */
629 arm966e_write_cp15(target, 62, 0x40000);
631 /* enable flash bank 1 */
632 target_write_u32(target, FLASH_CR, 0x18);