1 /***************************************************************************
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2 * Copyright (C) 2005 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * This program is free software; you can redistribute it and/or modify *
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6 * it under the terms of the GNU General Public License as published by *
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7 * the Free Software Foundation; either version 2 of the License, or *
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8 * (at your option) any later version. *
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10 * This program is distributed in the hope that it will be useful, *
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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13 * GNU General Public License for more details. *
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15 * You should have received a copy of the GNU General Public License *
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16 * along with this program; if not, write to the *
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17 * Free Software Foundation, Inc., *
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18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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19 ***************************************************************************/
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20 #ifdef HAVE_CONFIG_H
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24 #include "replacements.h"
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30 #include "armv4_5.h"
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31 #include "arm966e.h"
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32 #include "algorithm.h"
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33 #include "binarybuffer.h"
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39 str9x_mem_layout_t mem_layout_str9bank0[] = {
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40 {0x00000000, 0x10000, 0x01},
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41 {0x00010000, 0x10000, 0x02},
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42 {0x00020000, 0x10000, 0x04},
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43 {0x00030000, 0x10000, 0x08},
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44 {0x00040000, 0x10000, 0x10},
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45 {0x00050000, 0x10000, 0x20},
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46 {0x00060000, 0x10000, 0x40},
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47 {0x00070000, 0x10000, 0x80},
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50 str9x_mem_layout_t mem_layout_str9bank1[] = {
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51 {0x00000000, 0x02000, 0x100},
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52 {0x00002000, 0x02000, 0x200},
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53 {0x00004000, 0x02000, 0x400},
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54 {0x00006000, 0x02000, 0x800}
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57 static u32 bank1start = 0x00080000;
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59 int str9x_register_commands(struct command_context_s *cmd_ctx);
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60 int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
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61 int str9x_erase(struct flash_bank_s *bank, int first, int last);
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62 int str9x_protect(struct flash_bank_s *bank, int set, int first, int last);
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63 int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
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64 int str9x_probe(struct flash_bank_s *bank);
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65 int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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66 int str9x_protect_check(struct flash_bank_s *bank);
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67 int str9x_erase_check(struct flash_bank_s *bank);
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68 int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size);
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70 int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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72 flash_driver_t str9x_flash =
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75 .register_commands = str9x_register_commands,
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76 .flash_bank_command = str9x_flash_bank_command,
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77 .erase = str9x_erase,
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78 .protect = str9x_protect,
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79 .write = str9x_write,
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80 .probe = str9x_probe,
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81 .auto_probe = str9x_probe,
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82 .erase_check = str9x_erase_check,
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83 .protect_check = str9x_protect_check,
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87 int str9x_register_commands(struct command_context_s *cmd_ctx)
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89 command_t *str9x_cmd = register_command(cmd_ctx, NULL, "str9x", NULL, COMMAND_ANY, NULL);
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91 register_command(cmd_ctx, str9x_cmd, "flash_config", str9x_handle_flash_config_command, COMMAND_EXEC,
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92 "configure str9 flash controller");
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97 int str9x_build_block_list(struct flash_bank_s *bank)
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99 str9x_flash_bank_t *str9x_info = bank->driver_priv;
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102 int num_sectors = 0;
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103 int b0_sectors = 0, b1_sectors = 0;
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105 switch (bank->size)
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115 bank1start = bank->base;
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118 ERROR("BUG: unknown bank->size encountered");
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122 num_sectors = b0_sectors + b1_sectors;
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124 bank->num_sectors = num_sectors;
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125 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
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126 str9x_info->sector_bits = malloc(sizeof(u32) * num_sectors);
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130 for (i = 0; i < b0_sectors; i++)
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132 bank->sectors[num_sectors].offset = mem_layout_str9bank0[i].sector_start;
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133 bank->sectors[num_sectors].size = mem_layout_str9bank0[i].sector_size;
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134 bank->sectors[num_sectors].is_erased = -1;
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135 bank->sectors[num_sectors].is_protected = 1;
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136 str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank0[i].sector_bit;
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139 for (i = 0; i < b1_sectors; i++)
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141 bank->sectors[num_sectors].offset = mem_layout_str9bank1[i].sector_start;
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142 bank->sectors[num_sectors].size = mem_layout_str9bank1[i].sector_size;
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143 bank->sectors[num_sectors].is_erased = -1;
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144 bank->sectors[num_sectors].is_protected = 1;
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145 str9x_info->sector_bits[num_sectors++] = mem_layout_str9bank1[i].sector_bit;
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151 /* flash bank str9x <base> <size> 0 0 <target#>
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153 int str9x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
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155 str9x_flash_bank_t *str9x_info;
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159 WARNING("incomplete flash_bank str9x configuration");
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160 return ERROR_FLASH_BANK_INVALID;
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163 str9x_info = malloc(sizeof(str9x_flash_bank_t));
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164 bank->driver_priv = str9x_info;
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166 str9x_build_block_list(bank);
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168 str9x_info->write_algorithm = NULL;
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173 int str9x_blank_check(struct flash_bank_s *bank, int first, int last)
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175 target_t *target = bank->target;
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180 if ((first < 0) || (last > bank->num_sectors))
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181 return ERROR_FLASH_SECTOR_INVALID;
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183 if (bank->target->state != TARGET_HALTED)
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185 return ERROR_TARGET_NOT_HALTED;
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188 buffer = malloc(256);
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190 for (i = first; i <= last; i++)
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192 bank->sectors[i].is_erased = 1;
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194 target->type->read_memory(target, bank->base + bank->sectors[i].offset, 4, 256/4, buffer);
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196 for (nBytes = 0; nBytes < 256; nBytes++)
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198 if (buffer[nBytes] != 0xFF)
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200 bank->sectors[i].is_erased = 0;
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211 int str9x_protect_check(struct flash_bank_s *bank)
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213 str9x_flash_bank_t *str9x_info = bank->driver_priv;
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214 target_t *target = bank->target;
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220 if (bank->target->state != TARGET_HALTED)
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222 return ERROR_TARGET_NOT_HALTED;
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225 /* read level one protection */
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227 adr = bank1start + 0x10;
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229 target_write_u16(target, adr, 0x90);
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230 target_read_u16(target, adr, &status);
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231 target_write_u16(target, adr, 0xFF);
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233 for (i = 0; i < bank->num_sectors; i++)
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235 if (status & str9x_info->sector_bits[i])
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236 bank->sectors[i].is_protected = 1;
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238 bank->sectors[i].is_protected = 0;
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244 int str9x_erase(struct flash_bank_s *bank, int first, int last)
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246 target_t *target = bank->target;
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251 for (i = first; i <= last; i++)
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253 adr = bank->base + bank->sectors[i].offset;
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255 /* erase sectors */
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256 target_write_u16(target, adr, 0x20);
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257 target_write_u16(target, adr, 0xD0);
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260 target_write_u16(target, adr, 0x70);
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263 target_read_u8(target, adr, &status);
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264 if( status & 0x80 )
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269 /* clear status, also clear read array */
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270 target_write_u16(target, adr, 0x50);
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272 /* read array command */
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273 target_write_u16(target, adr, 0xFF);
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275 if( status & 0x22 )
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277 ERROR("error erasing flash bank, status: 0x%x", status);
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278 return ERROR_FLASH_OPERATION_FAILED;
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282 for (i = first; i <= last; i++)
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283 bank->sectors[i].is_erased = 1;
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288 int str9x_protect(struct flash_bank_s *bank, int set, int first, int last)
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290 target_t *target = bank->target;
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295 if (bank->target->state != TARGET_HALTED)
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297 return ERROR_TARGET_NOT_HALTED;
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300 for (i = first; i <= last; i++)
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302 /* Level One Protection */
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304 adr = bank->base + bank->sectors[i].offset;
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306 target_write_u16(target, adr, 0x60);
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308 target_write_u16(target, adr, 0x01);
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310 target_write_u16(target, adr, 0xD0);
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313 target_read_u8(target, adr, &status);
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319 int str9x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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321 str9x_flash_bank_t *str9x_info = bank->driver_priv;
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322 target_t *target = bank->target;
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323 u32 buffer_size = 8192;
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324 working_area_t *source;
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325 u32 address = bank->base + offset;
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326 reg_param_t reg_params[4];
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327 armv4_5_algorithm_t armv4_5_info;
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330 u32 str9x_flash_write_code[] = {
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332 0xe3c14003, /* bic r4, r1, #3 */
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333 0xe3a03040, /* mov r3, #0x40 */
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334 0xe1c430b0, /* strh r3, [r4, #0] */
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335 0xe0d030b2, /* ldrh r3, [r0], #2 */
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336 0xe0c130b2, /* strh r3, [r1], #2 */
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337 0xe3a03070, /* mov r3, #0x70 */
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338 0xe1c430b0, /* strh r3, [r4, #0] */
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340 0xe5d43000, /* ldrb r3, [r4, #0] */
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341 0xe3130080, /* tst r3, #0x80 */
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342 0x0afffffc, /* beq busy */
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343 0xe3a05050, /* mov r5, #0x50 */
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344 0xe1c450b0, /* strh r5, [r4, #0] */
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345 0xe3a050ff, /* mov r5, #0xFF */
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346 0xe1c450b0, /* strh r5, [r4, #0] */
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347 0xe3130012, /* tst r3, #0x12 */
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348 0x1a000001, /* bne exit */
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349 0xe2522001, /* subs r2, r2, #1 */
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350 0x1affffed, /* bne write */
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352 0xeafffffe, /* b exit */
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355 /* flash write code */
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356 if (target_alloc_working_area(target, 4 * 19, &str9x_info->write_algorithm) != ERROR_OK)
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358 WARNING("no working area available, can't do block memory writes");
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359 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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362 target_write_buffer(target, str9x_info->write_algorithm->address, 19 * 4, (u8*)str9x_flash_write_code);
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364 /* memory buffer */
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365 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
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368 if (buffer_size <= 256)
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370 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
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371 if (str9x_info->write_algorithm)
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372 target_free_working_area(target, str9x_info->write_algorithm);
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374 WARNING("no large enough working area available, can't do block memory writes");
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375 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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379 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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380 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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381 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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383 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
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384 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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385 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
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386 init_reg_param(®_params[3], "r3", 32, PARAM_IN);
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390 u32 thisrun_count = (count > (buffer_size / 2)) ? (buffer_size / 2) : count;
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392 target_write_buffer(target, source->address, thisrun_count * 2, buffer);
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394 buf_set_u32(reg_params[0].value, 0, 32, source->address);
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395 buf_set_u32(reg_params[1].value, 0, 32, address);
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396 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
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398 if ((retval = target->type->run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, str9x_info->write_algorithm->address + (18 * 4), 10000, &armv4_5_info)) != ERROR_OK)
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400 target_free_working_area(target, source);
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401 target_free_working_area(target, str9x_info->write_algorithm);
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402 ERROR("error executing str9x flash write algorithm");
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403 return ERROR_FLASH_OPERATION_FAILED;
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406 if (buf_get_u32(reg_params[3].value, 0, 32) != 0x80)
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408 return ERROR_FLASH_OPERATION_FAILED;
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411 buffer += thisrun_count * 2;
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412 address += thisrun_count * 2;
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413 count -= thisrun_count;
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416 target_free_working_area(target, source);
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417 target_free_working_area(target, str9x_info->write_algorithm);
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419 destroy_reg_param(®_params[0]);
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420 destroy_reg_param(®_params[1]);
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421 destroy_reg_param(®_params[2]);
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422 destroy_reg_param(®_params[3]);
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427 int str9x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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429 target_t *target = bank->target;
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430 u32 words_remaining = (count / 2);
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431 u32 bytes_remaining = (count & 0x00000001);
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432 u32 address = bank->base + offset;
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433 u32 bytes_written = 0;
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436 u32 check_address = offset;
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442 WARNING("offset 0x%x breaks required 2-byte alignment", offset);
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443 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
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446 for (i = 0; i < bank->num_sectors; i++)
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448 u32 sec_start = bank->sectors[i].offset;
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449 u32 sec_end = sec_start + bank->sectors[i].size;
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451 /* check if destination falls within the current sector */
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452 if ((check_address >= sec_start) && (check_address < sec_end))
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454 /* check if destination ends in the current sector */
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455 if (offset + count < sec_end)
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456 check_address = offset + count;
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458 check_address = sec_end;
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462 if (check_address != offset + count)
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463 return ERROR_FLASH_DST_OUT_OF_BANK;
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465 /* multiple half words (2-byte) to be programmed? */
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466 if (words_remaining > 0)
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468 /* try using a block write */
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469 if ((retval = str9x_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
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471 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
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473 /* if block write failed (no sufficient working area),
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474 * we use normal (slow) single dword accesses */
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475 WARNING("couldn't use block writes, falling back to single memory accesses");
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477 else if (retval == ERROR_FLASH_OPERATION_FAILED)
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479 ERROR("flash writing failed with error code: 0x%x", retval);
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480 return ERROR_FLASH_OPERATION_FAILED;
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485 buffer += words_remaining * 2;
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486 address += words_remaining * 2;
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487 words_remaining = 0;
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491 while (words_remaining > 0)
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493 bank_adr = address & ~0x03;
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495 /* write data command */
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496 target_write_u16(target, bank_adr, 0x40);
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497 target->type->write_memory(target, address, 2, 1, buffer + bytes_written);
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499 /* get status command */
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500 target_write_u16(target, bank_adr, 0x70);
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503 target_read_u8(target, bank_adr, &status);
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504 if( status & 0x80 )
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509 /* clear status reg and read array */
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510 target_write_u16(target, bank_adr, 0x50);
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511 target_write_u16(target, bank_adr, 0xFF);
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514 return ERROR_FLASH_OPERATION_FAILED;
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515 else if (status & 0x02)
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516 return ERROR_FLASH_OPERATION_FAILED;
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518 bytes_written += 2;
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523 if (bytes_remaining)
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525 u8 last_halfword[2] = {0xff, 0xff};
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528 while(bytes_remaining > 0)
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530 last_halfword[i++] = *(buffer + bytes_written);
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535 bank_adr = address & ~0x03;
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537 /* write data comamnd */
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538 target_write_u16(target, bank_adr, 0x40);
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539 target->type->write_memory(target, address, 2, 1, last_halfword);
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541 /* query status command */
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542 target_write_u16(target, bank_adr, 0x70);
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545 target_read_u8(target, bank_adr, &status);
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546 if( status & 0x80 )
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551 /* clear status reg and read array */
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552 target_write_u16(target, bank_adr, 0x50);
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553 target_write_u16(target, bank_adr, 0xFF);
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556 return ERROR_FLASH_OPERATION_FAILED;
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557 else if (status & 0x02)
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558 return ERROR_FLASH_OPERATION_FAILED;
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564 int str9x_probe(struct flash_bank_s *bank)
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569 int str9x_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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574 int str9x_erase_check(struct flash_bank_s *bank)
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576 return str9x_blank_check(bank, 0, bank->num_sectors - 1);
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579 int str9x_info(struct flash_bank_s *bank, char *buf, int buf_size)
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581 snprintf(buf, buf_size, "str9x flash driver info" );
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585 int str9x_handle_flash_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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587 str9x_flash_bank_t *str9x_info;
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588 flash_bank_t *bank;
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589 target_t *target = NULL;
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593 return ERROR_COMMAND_SYNTAX_ERROR;
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596 bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
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599 command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
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603 str9x_info = bank->driver_priv;
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605 target = bank->target;
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607 if (bank->target->state != TARGET_HALTED)
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609 return ERROR_TARGET_NOT_HALTED;
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612 /* config flash controller */
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613 target_write_u32(target, FLASH_BBSR, strtoul(args[1], NULL, 0));
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614 target_write_u32(target, FLASH_NBBSR, strtoul(args[2], NULL, 0));
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615 target_write_u32(target, FLASH_BBADR, (strtoul(args[3], NULL, 0) >> 2));
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616 target_write_u32(target, FLASH_NBBADR, (strtoul(args[4], NULL, 0) >> 2));
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618 /* set bit 18 instruction TCM order as per flash programming manual */
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619 arm966e_write_cp15(target, 62, 0x40000);
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621 /* enable flash bank 1 */
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622 target_write_u32(target, FLASH_CR, 0x18);
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