2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the
23 * Free Software Foundation, Inc.,
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 #include <helper/command.h>
35 * Holds the interface to ARM cores.
37 * At this writing, only "classic ARM" cores built on the ARMv4 register
38 * and mode model are supported. The Thumb2-only microcontroller profile
39 * support has not yet been integrated, affecting Cortex-M parts.
43 * These numbers match the five low bits of the *PSR registers on
44 * "classic ARM" processors, which build on the ARMv4 processor
45 * modes and register set.
59 const char *arm_mode_name(unsigned psr_mode);
60 bool is_arm_mode(unsigned psr_mode);
62 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
70 extern const char *arm_state_strings[];
72 #define ARM_COMMON_MAGIC 0x0A450A45
75 * Represents a generic ARM core, with standard application registers.
77 * There are sixteen application registers (including PC, SP, LR) and a PSR.
78 * Cortex-M series cores do not support as many core states or shadowed
79 * registers as traditional ARM cores, and only support Thumb2 instructions.
83 struct reg_cache *core_cache;
85 /** Handle to the CPSR; valid in all core modes. */
88 /** Handle to the SPSR; valid only in core modes with an SPSR. */
91 /** Support for arm_reg_current() */
95 * Indicates what registers are in the ARM state core register set.
96 * ARM_MODE_ANY indicates the standard set of 37 registers,
97 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
98 * more registers are shadowed, for "Secure Monitor" mode.
100 enum arm_mode core_type;
102 /** Record the current core mode: SVC, USR, or some other mode. */
103 enum arm_mode core_mode;
105 /** Record the current core state: ARM, Thumb, or otherwise. */
106 enum arm_state core_state;
108 /** Flag reporting unavailability of the BKPT instruction. */
111 /** Flag reporting whether semihosting is active. */
114 /** Value to be returned by semihosting SYS_ERRNO request. */
115 int semihosting_errno;
117 /** Backpointer to the target. */
118 struct target *target;
120 /** Handle for the debug module, if one is present. */
123 /** Handle for the Embedded Trace Module, if one is present. */
124 struct etm_context *etm;
126 /* FIXME all these methods should take "struct arm *" not target */
128 /** Retrieve all core registers, for display. */
129 int (*full_context)(struct target *target);
131 /** Retrieve a single core register. */
132 int (*read_core_reg)(struct target *target, struct reg *reg,
133 int num, enum arm_mode mode);
134 int (*write_core_reg)(struct target *target, struct reg *reg,
135 int num, enum arm_mode mode, uint32_t value);
137 /** Read coprocessor register. */
138 int (*mrc)(struct target *target, int cpnum,
139 uint32_t op1, uint32_t op2,
140 uint32_t CRn, uint32_t CRm,
143 /** Write coprocessor register. */
144 int (*mcr)(struct target *target, int cpnum,
145 uint32_t op1, uint32_t op2,
146 uint32_t CRn, uint32_t CRm,
152 /** Convert target handle to generic ARM target state handle. */
153 static inline struct arm *target_to_arm(struct target *target)
155 return target->arch_info;
158 static inline bool is_arm(struct arm *arm)
160 return arm && arm->common_magic == ARM_COMMON_MAGIC;
163 struct arm_algorithm {
166 enum arm_mode core_mode;
167 enum arm_state core_state;
173 struct target *target;
174 struct arm *armv4_5_common;
178 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
180 extern const struct command_registration arm_command_handlers[];
182 int arm_arch_state(struct target *target);
183 int arm_get_gdb_reg_list(struct target *target,
184 struct reg **reg_list[], int *reg_list_size);
186 int arm_init_arch_info(struct target *target, struct arm *arm);
188 /* REVISIT rename this once it's usable by ARMv7-M */
189 int armv4_5_run_algorithm(struct target *target,
190 int num_mem_params, struct mem_param *mem_params,
191 int num_reg_params, struct reg_param *reg_params,
192 uint32_t entry_point, uint32_t exit_point,
193 int timeout_ms, void *arch_info);
194 int armv4_5_run_algorithm_inner(struct target *target,
195 int num_mem_params, struct mem_param *mem_params,
196 int num_reg_params, struct reg_param *reg_params,
197 uint32_t entry_point, uint32_t exit_point,
198 int timeout_ms, void *arch_info,
199 int (*run_it)(struct target *target, uint32_t exit_point,
200 int timeout_ms, void *arch_info));
202 int arm_checksum_memory(struct target *target,
203 uint32_t address, uint32_t count, uint32_t *checksum);
204 int arm_blank_check_memory(struct target *target,
205 uint32_t address, uint32_t count, uint32_t *blank);
207 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
208 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
210 void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
212 extern struct reg arm_gdb_dummy_fp_reg;
213 extern struct reg arm_gdb_dummy_fps_reg;