2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2008 by Spencer Oliver
8 * Copyright (C) 2009 by Øyvind Harboe
9 * oyvind.harboe@zylin.com
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
25 #ifndef OPENOCD_TARGET_ARM_H
26 #define OPENOCD_TARGET_ARM_H
28 #include <helper/command.h>
34 * Holds the interface to ARM cores.
36 * At this writing, only "classic ARM" cores built on the ARMv4 register
37 * and mode model are supported. The Thumb2-only microcontroller profile
38 * support has not yet been integrated, affecting Cortex-M parts.
42 * Represent state of an ARM core.
44 * Most numbers match the five low bits of the *PSR registers on
45 * "classic ARM" processors, which build on the ARMv4 processor
46 * modes and register set.
48 * ARM_MODE_ANY is a magic value, often used as a wildcard.
50 * Only the microcontroller cores (ARMv6-M, ARMv7-M) support ARM_MODE_THREAD,
51 * ARM_MODE_USER_THREAD, and ARM_MODE_HANDLER. Those are the only modes
62 ARM_MODE_1176_MON = 28,
66 ARM_MODE_USER_THREAD = 1,
80 const char *arm_mode_name(unsigned psr_mode);
81 bool is_arm_mode(unsigned psr_mode);
83 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
92 #define ARM_COMMON_MAGIC 0x0A450A45
95 * Represents a generic ARM core, with standard application registers.
97 * There are sixteen application registers (including PC, SP, LR) and a PSR.
98 * Cortex-M series cores do not support as many core states or shadowed
99 * registers as traditional ARM cores, and only support Thumb2 instructions.
103 struct reg_cache *core_cache;
105 /** Handle to the PC; valid in all core modes. */
108 /** Handle to the CPSR/xPSR; valid in all core modes. */
111 /** Handle to the SPSR; valid only in core modes with an SPSR. */
114 /** Support for arm_reg_current() */
118 * Indicates what registers are in the ARM state core register set.
119 * ARM_MODE_ANY indicates the standard set of 37 registers,
120 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
121 * more registers are shadowed, for "Secure Monitor" mode.
122 * ARM_MODE_THREAD indicates a microcontroller profile core,
123 * which only shadows SP.
125 enum arm_mode core_type;
127 /** Record the current core mode: SVC, USR, or some other mode. */
128 enum arm_mode core_mode;
130 /** Record the current core state: ARM, Thumb, or otherwise. */
131 enum arm_state core_state;
133 /** Flag reporting unavailability of the BKPT instruction. */
136 /** Flag reporting armv6m based core. */
139 /** Flag reporting whether semihosting is active. */
142 /** Flag reporting whether semihosting fileio is active. */
143 bool is_semihosting_fileio;
145 /** Flag reporting whether semihosting fileio operation is active. */
146 bool semihosting_hit_fileio;
148 /** Current semihosting operation. */
151 /** Current semihosting result. */
152 int semihosting_result;
154 /** Value to be returned by semihosting SYS_ERRNO request. */
155 int semihosting_errno;
157 int (*setup_semihosting)(struct target *target, int enable);
159 /** Semihosting command line. */
160 char *semihosting_cmdline;
162 /** Backpointer to the target. */
163 struct target *target;
165 /** Handle for the debug module, if one is present. */
168 /** Handle for the Embedded Trace Module, if one is present. */
169 struct etm_context *etm;
171 /* FIXME all these methods should take "struct arm *" not target */
173 /** Retrieve all core registers, for display. */
174 int (*full_context)(struct target *target);
176 /** Retrieve a single core register. */
177 int (*read_core_reg)(struct target *target, struct reg *reg,
178 int num, enum arm_mode mode);
179 int (*write_core_reg)(struct target *target, struct reg *reg,
180 int num, enum arm_mode mode, uint8_t *value);
182 /** Read coprocessor register. */
183 int (*mrc)(struct target *target, int cpnum,
184 uint32_t op1, uint32_t op2,
185 uint32_t CRn, uint32_t CRm,
188 /** Write coprocessor register. */
189 int (*mcr)(struct target *target, int cpnum,
190 uint32_t op1, uint32_t op2,
191 uint32_t CRn, uint32_t CRm,
196 /** For targets conforming to ARM Debug Interface v5,
197 * this handle references the Debug Access Port (DAP)
198 * used to make requests to the target.
200 struct adiv5_dap *dap;
203 /** Convert target handle to generic ARM target state handle. */
204 static inline struct arm *target_to_arm(struct target *target)
206 assert(target != NULL);
207 return target->arch_info;
210 static inline bool is_arm(struct arm *arm)
213 return arm->common_magic == ARM_COMMON_MAGIC;
216 struct arm_algorithm {
219 enum arm_mode core_mode;
220 enum arm_state core_state;
226 struct target *target;
231 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
232 struct reg_cache *armv8_build_reg_cache(struct target *target);
234 extern const struct command_registration arm_command_handlers[];
236 int arm_arch_state(struct target *target);
237 int arm_get_gdb_reg_list(struct target *target,
238 struct reg **reg_list[], int *reg_list_size,
239 enum target_register_class reg_class);
240 int armv8_get_gdb_reg_list(struct target *target,
241 struct reg **reg_list[], int *reg_list_size,
242 enum target_register_class reg_class);
244 int arm_init_arch_info(struct target *target, struct arm *arm);
246 /* REVISIT rename this once it's usable by ARMv7-M */
247 int armv4_5_run_algorithm(struct target *target,
248 int num_mem_params, struct mem_param *mem_params,
249 int num_reg_params, struct reg_param *reg_params,
250 target_addr_t entry_point, target_addr_t exit_point,
251 int timeout_ms, void *arch_info);
252 int armv4_5_run_algorithm_inner(struct target *target,
253 int num_mem_params, struct mem_param *mem_params,
254 int num_reg_params, struct reg_param *reg_params,
255 uint32_t entry_point, uint32_t exit_point,
256 int timeout_ms, void *arch_info,
257 int (*run_it)(struct target *target, uint32_t exit_point,
258 int timeout_ms, void *arch_info));
260 int arm_checksum_memory(struct target *target,
261 target_addr_t address, uint32_t count, uint32_t *checksum);
262 int arm_blank_check_memory(struct target *target,
263 target_addr_t address, uint32_t count, uint32_t *blank, uint8_t erased_value);
265 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
266 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
267 struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
269 extern struct reg arm_gdb_dummy_fp_reg;
270 extern struct reg arm_gdb_dummy_fps_reg;
272 #endif /* OPENOCD_TARGET_ARM_H */