git.sur5r.net Git - openocd/blob - src/target/arm11.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com              *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "arm11.h"
  30 #include "armv4_5.h"
  31 #include "arm_simulator.h"
  32 #include "target_type.h"
  33
  34
  35 #if 0
  36 #define _DEBUG_INSTRUCTION_EXECUTION_
  37 #endif
  38
  39 #if 0
  40 #define FNC_INFO        LOG_DEBUG("-")
  41 #else
  42 #define FNC_INFO
  43 #endif
  44
  45 #if 1
  46 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
  47 #else
  48 #define FNC_INFO_NOTIMPLEMENTED
  49 #endif
  50
  51 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
  52
  53 bool    arm11_config_memwrite_burst                             = true;
  54 bool    arm11_config_memwrite_error_fatal               = true;
  55 uint32_t                arm11_vcr                                                               = 0;
  56 bool    arm11_config_memrw_no_increment                 = false;
  57 bool    arm11_config_step_irq_enable                    = false;
  58
  59 #define ARM11_HANDLER(x)        \
  60         .x                              = arm11_##x
  61
  62 target_type_t arm11_target =
  63 {
  64         .name                   = "arm11",
  65
  66         ARM11_HANDLER(poll),
  67         ARM11_HANDLER(arch_state),
  68
  69         ARM11_HANDLER(target_request_data),
  70
  71         ARM11_HANDLER(halt),
  72         ARM11_HANDLER(resume),
  73         ARM11_HANDLER(step),
  74
  75         ARM11_HANDLER(assert_reset),
  76         ARM11_HANDLER(deassert_reset),
  77         ARM11_HANDLER(soft_reset_halt),
  78
  79         ARM11_HANDLER(get_gdb_reg_list),
  80
  81         ARM11_HANDLER(read_memory),
  82         ARM11_HANDLER(write_memory),
  83
  84         ARM11_HANDLER(bulk_write_memory),
  85
  86         ARM11_HANDLER(checksum_memory),
  87
  88         ARM11_HANDLER(add_breakpoint),
  89         ARM11_HANDLER(remove_breakpoint),
  90         ARM11_HANDLER(add_watchpoint),
  91         ARM11_HANDLER(remove_watchpoint),
  92
  93         ARM11_HANDLER(run_algorithm),
  94
  95         ARM11_HANDLER(register_commands),
  96         ARM11_HANDLER(target_create),
  97         ARM11_HANDLER(init_target),
  98         ARM11_HANDLER(examine),
  99         ARM11_HANDLER(quit),
 100 };
 101
 102 int arm11_regs_arch_type = -1;
 103
 104
 105 enum arm11_regtype
 106 {
 107         ARM11_REGISTER_CORE,
 108         ARM11_REGISTER_CPSR,
 109
 110         ARM11_REGISTER_FX,
 111         ARM11_REGISTER_FPS,
 112
 113         ARM11_REGISTER_FIQ,
 114         ARM11_REGISTER_SVC,
 115         ARM11_REGISTER_ABT,
 116         ARM11_REGISTER_IRQ,
 117         ARM11_REGISTER_UND,
 118         ARM11_REGISTER_MON,
 119
 120         ARM11_REGISTER_SPSR_FIQ,
 121         ARM11_REGISTER_SPSR_SVC,
 122         ARM11_REGISTER_SPSR_ABT,
 123         ARM11_REGISTER_SPSR_IRQ,
 124         ARM11_REGISTER_SPSR_UND,
 125         ARM11_REGISTER_SPSR_MON,
 126
 127         /* debug regs */
 128         ARM11_REGISTER_DSCR,
 129         ARM11_REGISTER_WDTR,
 130         ARM11_REGISTER_RDTR,
 131 };
 132
 133
 134 typedef struct arm11_reg_defs_s
 135 {
 136         char *                                  name;
 137         uint32_t                                                num;
 138         int                                             gdb_num;
 139         enum arm11_regtype              type;
 140 } arm11_reg_defs_t;
 141
 142 /* update arm11_regcache_ids when changing this */
 143 static const arm11_reg_defs_t arm11_reg_defs[] =
 144 {
 145         {"r0",  0,      0,      ARM11_REGISTER_CORE},
 146         {"r1",  1,      1,      ARM11_REGISTER_CORE},
 147         {"r2",  2,      2,      ARM11_REGISTER_CORE},
 148         {"r3",  3,      3,      ARM11_REGISTER_CORE},
 149         {"r4",  4,      4,      ARM11_REGISTER_CORE},
 150         {"r5",  5,      5,      ARM11_REGISTER_CORE},
 151         {"r6",  6,      6,      ARM11_REGISTER_CORE},
 152         {"r7",  7,      7,      ARM11_REGISTER_CORE},
 153         {"r8",  8,      8,      ARM11_REGISTER_CORE},
 154         {"r9",  9,      9,      ARM11_REGISTER_CORE},
 155         {"r10", 10,     10,     ARM11_REGISTER_CORE},
 156         {"r11", 11,     11,     ARM11_REGISTER_CORE},
 157         {"r12", 12,     12,     ARM11_REGISTER_CORE},
 158         {"sp",  13,     13,     ARM11_REGISTER_CORE},
 159         {"lr",  14,     14,     ARM11_REGISTER_CORE},
 160         {"pc",  15,     15,     ARM11_REGISTER_CORE},
 161
 162 #if ARM11_REGCACHE_FREGS
 163         {"f0",  0,      16,     ARM11_REGISTER_FX},
 164         {"f1",  1,      17,     ARM11_REGISTER_FX},
 165         {"f2",  2,      18,     ARM11_REGISTER_FX},
 166         {"f3",  3,      19,     ARM11_REGISTER_FX},
 167         {"f4",  4,      20,     ARM11_REGISTER_FX},
 168         {"f5",  5,      21,     ARM11_REGISTER_FX},
 169         {"f6",  6,      22,     ARM11_REGISTER_FX},
 170         {"f7",  7,      23,     ARM11_REGISTER_FX},
 171         {"fps", 0,      24,     ARM11_REGISTER_FPS},
 172 #endif
 173
 174         {"cpsr",        0,      25,     ARM11_REGISTER_CPSR},
 175
 176 #if ARM11_REGCACHE_MODEREGS
 177         {"r8_fiq",      8,      -1,     ARM11_REGISTER_FIQ},
 178         {"r9_fiq",      9,      -1,     ARM11_REGISTER_FIQ},
 179         {"r10_fiq",     10,     -1,     ARM11_REGISTER_FIQ},
 180         {"r11_fiq",     11,     -1,     ARM11_REGISTER_FIQ},
 181         {"r12_fiq",     12,     -1,     ARM11_REGISTER_FIQ},
 182         {"r13_fiq",     13,     -1,     ARM11_REGISTER_FIQ},
 183         {"r14_fiq",     14,     -1,     ARM11_REGISTER_FIQ},
 184         {"spsr_fiq", 0, -1,     ARM11_REGISTER_SPSR_FIQ},
 185
 186         {"r13_svc",     13,     -1,     ARM11_REGISTER_SVC},
 187         {"r14_svc",     14,     -1,     ARM11_REGISTER_SVC},
 188         {"spsr_svc", 0, -1,     ARM11_REGISTER_SPSR_SVC},
 189
 190         {"r13_abt",     13,     -1,     ARM11_REGISTER_ABT},
 191         {"r14_abt",     14,     -1,     ARM11_REGISTER_ABT},
 192         {"spsr_abt", 0, -1,     ARM11_REGISTER_SPSR_ABT},
 193
 194         {"r13_irq",     13,     -1,     ARM11_REGISTER_IRQ},
 195         {"r14_irq",     14,     -1,     ARM11_REGISTER_IRQ},
 196         {"spsr_irq", 0, -1,     ARM11_REGISTER_SPSR_IRQ},
 197
 198         {"r13_und",     13,     -1,     ARM11_REGISTER_UND},
 199         {"r14_und",     14,     -1,     ARM11_REGISTER_UND},
 200         {"spsr_und", 0, -1,     ARM11_REGISTER_SPSR_UND},
 201
 202         /* ARM1176 only */
 203         {"r13_mon",     13,     -1,     ARM11_REGISTER_MON},
 204         {"r14_mon",     14,     -1,     ARM11_REGISTER_MON},
 205         {"spsr_mon", 0, -1,     ARM11_REGISTER_SPSR_MON},
 206 #endif
 207
 208         /* Debug Registers */
 209         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
 210         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
 211         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
 212 };
 213
 214 enum arm11_regcache_ids
 215 {
 216         ARM11_RC_R0,
 217         ARM11_RC_RX                     = ARM11_RC_R0,
 218
 219         ARM11_RC_R1,
 220         ARM11_RC_R2,
 221         ARM11_RC_R3,
 222         ARM11_RC_R4,
 223         ARM11_RC_R5,
 224         ARM11_RC_R6,
 225         ARM11_RC_R7,
 226         ARM11_RC_R8,
 227         ARM11_RC_R9,
 228         ARM11_RC_R10,
 229         ARM11_RC_R11,
 230         ARM11_RC_R12,
 231         ARM11_RC_R13,
 232         ARM11_RC_SP                     = ARM11_RC_R13,
 233         ARM11_RC_R14,
 234         ARM11_RC_LR                     = ARM11_RC_R14,
 235         ARM11_RC_R15,
 236         ARM11_RC_PC                     = ARM11_RC_R15,
 237
 238 #if ARM11_REGCACHE_FREGS
 239         ARM11_RC_F0,
 240         ARM11_RC_FX                     = ARM11_RC_F0,
 241         ARM11_RC_F1,
 242         ARM11_RC_F2,
 243         ARM11_RC_F3,
 244         ARM11_RC_F4,
 245         ARM11_RC_F5,
 246         ARM11_RC_F6,
 247         ARM11_RC_F7,
 248         ARM11_RC_FPS,
 249 #endif
 250
 251         ARM11_RC_CPSR,
 252
 253 #if ARM11_REGCACHE_MODEREGS
 254         ARM11_RC_R8_FIQ,
 255         ARM11_RC_R9_FIQ,
 256         ARM11_RC_R10_FIQ,
 257         ARM11_RC_R11_FIQ,
 258         ARM11_RC_R12_FIQ,
 259         ARM11_RC_R13_FIQ,
 260         ARM11_RC_R14_FIQ,
 261         ARM11_RC_SPSR_FIQ,
 262
 263         ARM11_RC_R13_SVC,
 264         ARM11_RC_R14_SVC,
 265         ARM11_RC_SPSR_SVC,
 266
 267         ARM11_RC_R13_ABT,
 268         ARM11_RC_R14_ABT,
 269         ARM11_RC_SPSR_ABT,
 270
 271         ARM11_RC_R13_IRQ,
 272         ARM11_RC_R14_IRQ,
 273         ARM11_RC_SPSR_IRQ,
 274
 275         ARM11_RC_R13_UND,
 276         ARM11_RC_R14_UND,
 277         ARM11_RC_SPSR_UND,
 278
 279         ARM11_RC_R13_MON,
 280         ARM11_RC_R14_MON,
 281         ARM11_RC_SPSR_MON,
 282 #endif
 283
 284         ARM11_RC_DSCR,
 285         ARM11_RC_WDTR,
 286         ARM11_RC_RDTR,
 287
 288         ARM11_RC_MAX,
 289 };
 290
 291 #define ARM11_GDB_REGISTER_COUNT        26
 292
 293 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 294
 295 reg_t arm11_gdb_dummy_fp_reg =
 296 {
 297         "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 298 };
 299
 300 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 301
 302 reg_t arm11_gdb_dummy_fps_reg =
 303 {
 304         "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 305 };
 306
 307
 308
 309 /** Check and if necessary take control of the system
 310  *
 311  * \param arm11         Target state variable.
 312  * \param dscr          If the current DSCR content is
 313  *                                      available a pointer to a word holding the
 314  *                                      DSCR can be passed. Otherwise use NULL.
 315  */
 316 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
 317 {
 318         FNC_INFO;
 319
 320         uint32_t                        dscr_local_tmp_copy;
 321
 322         if (!dscr)
 323         {
 324                 dscr = &dscr_local_tmp_copy;
 325
 326                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 327         }
 328
 329         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 330         {
 331                 LOG_DEBUG("Bringing target into debug mode");
 332
 333                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 334                 arm11_write_DSCR(arm11, *dscr);
 335
 336                 /* add further reset initialization here */
 337
 338                 arm11->simulate_reset_on_next_halt = true;
 339
 340                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 341                 {
 342                         /** \todo TODO: this needs further scrutiny because
 343                           * arm11_on_enter_debug_state() never gets properly called.
 344                           * As a result we don't read the actual register states from
 345                           * the target.
 346                           */
 347
 348                         arm11->target->state    = TARGET_HALTED;
 349                         arm11->target->debug_reason     = arm11_get_DSCR_debug_reason(*dscr);
 350                 }
 351                 else
 352                 {
 353                         arm11->target->state    = TARGET_RUNNING;
 354                         arm11->target->debug_reason     = DBG_REASON_NOTHALTED;
 355                 }
 356
 357                 arm11_sc7_clear_vbw(arm11);
 358         }
 359
 360         return ERROR_OK;
 361 }
 362
 363
 364
 365 #define R(x) \
 366         (arm11->reg_values[ARM11_RC_##x])
 367
 368 /** Save processor state.
 369   *
 370   * This is called when the HALT instruction has succeeded
 371   * or on other occasions that stop the processor.
 372   *
 373   */
 374 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 375 {
 376         FNC_INFO;
 377
 378         for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
 379         {
 380                 arm11->reg_list[i].valid        = 1;
 381                 arm11->reg_list[i].dirty        = 0;
 382         }
 383
 384         /* Save DSCR */
 385         CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
 386
 387         /* Save wDTR */
 388
 389         if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
 390         {
 391                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 392
 393                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 394
 395                 scan_field_t    chain5_fields[3];
 396
 397                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 398                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 399                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 400
 401                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 402         }
 403         else
 404         {
 405                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 406         }
 407
 408
 409         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
 410         /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
 411            ARM1136 seems to require this to issue ITR's as well */
 412
 413         uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 414
 415         /* this executes JTAG queue: */
 416
 417         arm11_write_DSCR(arm11, new_dscr);
 418
 419
 420         /* From the spec:
 421            Before executing any instruction in debug state you have to drain the write buffer.
 422            This ensures that no imprecise Data Aborts can return at a later point:*/
 423
 424         /** \todo TODO: Test drain write buffer. */
 425
 426 #if 0
 427         while (1)
 428         {
 429                 /* MRC p14,0,R0,c5,c10,0 */
 430                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 431
 432                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 433                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 434
 435                 uint32_t dscr = arm11_read_DSCR(arm11);
 436
 437                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 438
 439                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 440                 {
 441                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 442
 443                         dscr = arm11_read_DSCR(arm11);
 444
 445                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 446
 447                         break;
 448                 }
 449         }
 450 #endif
 451
 452         arm11_run_instr_data_prepare(arm11);
 453
 454         /* save r0 - r14 */
 455
 456         /** \todo TODO: handle other mode registers */
 457
 458         for (size_t i = 0; i < 15; i++)
 459         {
 460                 /* MCR p14,0,R?,c0,c5,0 */
 461                 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
 462         }
 463
 464         /* save rDTR */
 465
 466         /* check rDTRfull in DSCR */
 467
 468         if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
 469         {
 470                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 471                 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 472         }
 473         else
 474         {
 475                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 476         }
 477
 478         /* save CPSR */
 479
 480         /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
 481         arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
 482
 483         /* save PC */
 484
 485         /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
 486         arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
 487
 488         /* adjust PC depending on ARM state */
 489
 490         if (R(CPSR) & ARM11_CPSR_J)     /* Java state */
 491         {
 492                 arm11->reg_values[ARM11_RC_PC] -= 0;
 493         }
 494         else if (R(CPSR) & ARM11_CPSR_T)        /* Thumb state */
 495         {
 496                 arm11->reg_values[ARM11_RC_PC] -= 4;
 497         }
 498         else                                    /* ARM state */
 499         {
 500                 arm11->reg_values[ARM11_RC_PC] -= 8;
 501         }
 502
 503         if (arm11->simulate_reset_on_next_halt)
 504         {
 505                 arm11->simulate_reset_on_next_halt = false;
 506
 507                 LOG_DEBUG("Reset c1 Control Register");
 508
 509                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 510
 511                 /* MCR p15,0,R0,c1,c0,0 */
 512                 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 513
 514         }
 515
 516         arm11_run_instr_data_finish(arm11);
 517
 518         arm11_dump_reg_changes(arm11);
 519
 520         return ERROR_OK;
 521 }
 522
 523 void arm11_dump_reg_changes(arm11_common_t * arm11)
 524 {
 525
 526         if (!(debug_level >= LOG_LVL_DEBUG))
 527         {
 528                 return;
 529         }
 530
 531         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 532         {
 533                 if (!arm11->reg_list[i].valid)
 534                 {
 535                         if (arm11->reg_history[i].valid)
 536                                 LOG_DEBUG("%8s INVALID   (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 537                 }
 538                 else
 539                 {
 540                         if (arm11->reg_history[i].valid)
 541                         {
 542                                 if (arm11->reg_history[i].value != arm11->reg_values[i])
 543                                         LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 544                         }
 545                         else
 546                         {
 547                                 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 548                         }
 549                 }
 550         }
 551 }
 552
 553 /** Restore processor state
 554   *
 555   * This is called in preparation for the RESTART function.
 556   *
 557   */
 558 int arm11_leave_debug_state(arm11_common_t * arm11)
 559 {
 560         FNC_INFO;
 561
 562         arm11_run_instr_data_prepare(arm11);
 563
 564         /** \todo TODO: handle other mode registers */
 565
 566         /* restore R1 - R14 */
 567
 568         for (size_t i = 1; i < 15; i++)
 569         {
 570                 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
 571                         continue;
 572
 573                 /* MRC p14,0,r?,c0,c5,0 */
 574                 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
 575
 576                 //      LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
 577         }
 578
 579         arm11_run_instr_data_finish(arm11);
 580
 581         /* spec says clear wDTR and rDTR; we assume they are clear as
 582            otherwise our programming would be sloppy */
 583         {
 584                 uint32_t DSCR;
 585
 586                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 587
 588                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 589                 {
 590                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 591                 }
 592         }
 593
 594         arm11_run_instr_data_prepare(arm11);
 595
 596         /* restore original wDTR */
 597
 598         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 599         {
 600                 /* MCR p14,0,R0,c0,c5,0 */
 601                 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 602         }
 603
 604         /* restore CPSR */
 605
 606         /* MSR CPSR,R0*/
 607         arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
 608
 609         /* restore PC */
 610
 611         /* MOV PC,R0 */
 612         arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
 613
 614         /* restore R0 */
 615
 616         /* MRC p14,0,r0,c0,c5,0 */
 617         arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
 618
 619         arm11_run_instr_data_finish(arm11);
 620
 621         /* restore DSCR */
 622
 623         arm11_write_DSCR(arm11, R(DSCR));
 624
 625         /* restore rDTR */
 626
 627         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 628         {
 629                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 630
 631                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 632
 633                 scan_field_t    chain5_fields[3];
 634
 635                 uint8_t                 Ready           = 0;    /* ignored */
 636                 uint8_t                 Valid           = 0;    /* ignored */
 637
 638                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 639                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 640                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 641
 642                 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 643         }
 644
 645         arm11_record_register_history(arm11);
 646
 647         return ERROR_OK;
 648 }
 649
 650 void arm11_record_register_history(arm11_common_t * arm11)
 651 {
 652         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
 653         {
 654                 arm11->reg_history[i].value     = arm11->reg_values[i];
 655                 arm11->reg_history[i].valid     = arm11->reg_list[i].valid;
 656
 657                 arm11->reg_list[i].valid        = 0;
 658                 arm11->reg_list[i].dirty        = 0;
 659         }
 660 }
 661
 662
 663 /* poll current target status */
 664 int arm11_poll(struct target_s *target)
 665 {
 666         FNC_INFO;
 667
 668         arm11_common_t * arm11 = target->arch_info;
 669
 670         if (arm11->trst_active)
 671                 return ERROR_OK;
 672
 673         uint32_t        dscr;
 674
 675         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 676
 677         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 678
 679         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 680
 681         if (dscr & ARM11_DSCR_CORE_HALTED)
 682         {
 683                 if (target->state != TARGET_HALTED)
 684                 {
 685                         enum target_state old_state = target->state;
 686
 687                         LOG_DEBUG("enter TARGET_HALTED");
 688                         target->state                   = TARGET_HALTED;
 689                         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 690                         arm11_on_enter_debug_state(arm11);
 691
 692                         target_call_event_callbacks(target,
 693                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 694                 }
 695         }
 696         else
 697         {
 698                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 699                 {
 700                         LOG_DEBUG("enter TARGET_RUNNING");
 701                         target->state                   = TARGET_RUNNING;
 702                         target->debug_reason    = DBG_REASON_NOTHALTED;
 703                 }
 704         }
 705
 706         return ERROR_OK;
 707 }
 708 /* architecture specific status reply */
 709 int arm11_arch_state(struct target_s *target)
 710 {
 711         arm11_common_t * arm11 = target->arch_info;
 712
 713         LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 714                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 715                          R(CPSR),
 716                          R(PC));
 717
 718         return ERROR_OK;
 719 }
 720
 721 /* target request support */
 722 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
 723 {
 724         FNC_INFO_NOTIMPLEMENTED;
 725
 726         return ERROR_OK;
 727 }
 728
 729 /* target execution control */
 730 int arm11_halt(struct target_s *target)
 731 {
 732         FNC_INFO;
 733
 734         arm11_common_t * arm11 = target->arch_info;
 735
 736         LOG_DEBUG("target->state: %s",
 737                 target_state_name(target));
 738
 739         if (target->state == TARGET_UNKNOWN)
 740         {
 741                 arm11->simulate_reset_on_next_halt = true;
 742         }
 743
 744         if (target->state == TARGET_HALTED)
 745         {
 746                 LOG_DEBUG("target was already halted");
 747                 return ERROR_OK;
 748         }
 749
 750         if (arm11->trst_active)
 751         {
 752                 arm11->halt_requested = true;
 753                 return ERROR_OK;
 754         }
 755
 756         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 757
 758         CHECK_RETVAL(jtag_execute_queue());
 759
 760         uint32_t dscr;
 761
 762         while (1)
 763         {
 764                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 765
 766                 if (dscr & ARM11_DSCR_CORE_HALTED)
 767                         break;
 768         }
 769
 770         arm11_on_enter_debug_state(arm11);
 771
 772         enum target_state old_state     = target->state;
 773
 774         target->state           = TARGET_HALTED;
 775         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 776
 777         CHECK_RETVAL(
 778                 target_call_event_callbacks(target,
 779                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 780
 781         return ERROR_OK;
 782 }
 783
 784 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
 785 {
 786         FNC_INFO;
 787
 788         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 789         //      current, address, handle_breakpoints, debug_execution);
 790
 791         arm11_common_t * arm11 = target->arch_info;
 792
 793         LOG_DEBUG("target->state: %s",
 794                 target_state_name(target));
 795
 796
 797         if (target->state != TARGET_HALTED)
 798         {
 799                 LOG_ERROR("Target not halted");
 800                 return ERROR_TARGET_NOT_HALTED;
 801         }
 802
 803         if (!current)
 804                 R(PC) = address;
 805
 806         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 807
 808         /* clear breakpoints/watchpoints and VCR*/
 809         arm11_sc7_clear_vbw(arm11);
 810
 811         /* Set up breakpoints */
 812         if (!debug_execution)
 813         {
 814                 /* check if one matches PC and step over it if necessary */
 815
 816                 breakpoint_t *  bp;
 817
 818                 for (bp = target->breakpoints; bp; bp = bp->next)
 819                 {
 820                         if (bp->address == R(PC))
 821                         {
 822                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 823                                 arm11_step(target, 1, 0, 0);
 824                                 break;
 825                         }
 826                 }
 827
 828                 /* set all breakpoints */
 829
 830                 size_t          brp_num = 0;
 831
 832                 for (bp = target->breakpoints; bp; bp = bp->next)
 833                 {
 834                         arm11_sc7_action_t      brp[2];
 835
 836                         brp[0].write    = 1;
 837                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 838                         brp[0].value    = bp->address;
 839                         brp[1].write    = 1;
 840                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 841                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 842
 843                         arm11_sc7_run(arm11, brp, asizeof(brp));
 844
 845                         LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
 846
 847                         brp_num++;
 848                 }
 849
 850                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 851         }
 852
 853         arm11_leave_debug_state(arm11);
 854
 855         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 856
 857         CHECK_RETVAL(jtag_execute_queue());
 858
 859         while (1)
 860         {
 861                 uint32_t dscr;
 862
 863                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 864
 865                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 866
 867                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 868                         break;
 869         }
 870
 871         if (!debug_execution)
 872         {
 873                 target->state                   = TARGET_RUNNING;
 874                 target->debug_reason    = DBG_REASON_NOTHALTED;
 875
 876                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 877         }
 878         else
 879         {
 880                 target->state                   = TARGET_DEBUG_RUNNING;
 881                 target->debug_reason    = DBG_REASON_NOTHALTED;
 882
 883                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 884         }
 885
 886         return ERROR_OK;
 887 }
 888
 889
 890 static int armv4_5_to_arm11(int reg)
 891 {
 892         if (reg < 16)
 893                 return reg;
 894         switch (reg)
 895         {
 896         case ARMV4_5_CPSR:
 897                 return ARM11_RC_CPSR;
 898         case 16:
 899                 /* FIX!!! handle thumb better! */
 900                 return ARM11_RC_CPSR;
 901         default:
 902                 LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
 903                 exit(-1);
 904         }
 905 }
 906
 907
 908 static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
 909 {
 910         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 911
 912         reg=armv4_5_to_arm11(reg);
 913
 914         return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
 915 }
 916
 917 static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
 918 {
 919         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 920
 921         reg=armv4_5_to_arm11(reg);
 922
 923         buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
 924 }
 925
 926 static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
 927 {
 928         arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 929
 930         return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
 931 }
 932
 933 static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
 934 {
 935 //      arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 936
 937         /* FIX!!!! we should implement thumb for arm11 */
 938         return ARMV4_5_STATE_ARM;
 939 }
 940
 941 static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
 942 {
 943 //      arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 944
 945         /* FIX!!!! we should implement thumb for arm11 */
 946         LOG_ERROR("Not implemetned!");
 947 }
 948
 949
 950 static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
 951 {
 952         //arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
 953
 954         /* FIX!!!! we should implement something that returns the current mode here!!! */
 955         return ARMV4_5_MODE_USR;
 956 }
 957
 958 static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
 959 {
 960         struct arm_sim_interface sim;
 961
 962         sim.user_data=target->arch_info;
 963         sim.get_reg=&arm11_sim_get_reg;
 964         sim.set_reg=&arm11_sim_set_reg;
 965         sim.get_reg_mode=&arm11_sim_get_reg;
 966         sim.set_reg_mode=&arm11_sim_set_reg;
 967         sim.get_cpsr=&arm11_sim_get_cpsr;
 968         sim.get_mode=&arm11_sim_get_mode;
 969         sim.get_state=&arm11_sim_get_state;
 970         sim.set_state=&arm11_sim_set_state;
 971
 972         return arm_simulate_step_core(target, dry_run_pc, &sim);
 973
 974 }
 975
 976 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 977 {
 978         FNC_INFO;
 979         int retval;
 980
 981         LOG_DEBUG("target->state: %s",
 982                 target_state_name(target));
 983
 984         if (target->state != TARGET_HALTED)
 985         {
 986                 LOG_WARNING("target was not halted");
 987                 return ERROR_TARGET_NOT_HALTED;
 988         }
 989
 990         arm11_common_t * arm11 = target->arch_info;
 991
 992         if (!current)
 993                 R(PC) = address;
 994
 995         LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 996
 997
 998         /* TODO: to implement single stepping on arm11 devices that can't
 999          * do single stepping in hardware we need to calculate the next
1000          * pc and set up breakpoints accordingingly. */
1001         uint32_t next_pc;
1002         retval = arm11_simulate_step(target, &next_pc);
1003         if (retval != ERROR_OK)
1004                 return retval;
1005
1006
1007         /** \todo TODO: Thumb not supported here */
1008
1009         uint32_t        next_instruction;
1010
1011         CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
1012
1013         /* skip over BKPT */
1014         if ((next_instruction & 0xFFF00070) == 0xe1200070)
1015         {
1016                 R(PC) += 4;
1017                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1018                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1019                 LOG_DEBUG("Skipping BKPT");
1020         }
1021         /* skip over Wait for interrupt / Standby */
1022         /* mcr  15, 0, r?, cr7, cr0, {4} */
1023         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
1024         {
1025                 R(PC) += 4;
1026                 arm11->reg_list[ARM11_RC_PC].valid = 1;
1027                 arm11->reg_list[ARM11_RC_PC].dirty = 0;
1028                 LOG_DEBUG("Skipping WFI");
1029         }
1030         /* ignore B to self */
1031         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
1032         {
1033                 LOG_DEBUG("Not stepping jump to self");
1034         }
1035         else
1036         {
1037                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
1038                 * with this. */
1039
1040                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
1041                 * the VCR might be something worth looking into. */
1042
1043
1044                 /* Set up breakpoint for stepping */
1045
1046                 arm11_sc7_action_t      brp[2];
1047
1048                 brp[0].write    = 1;
1049                 brp[0].address  = ARM11_SC7_BVR0;
1050                 brp[0].value    = R(PC);
1051                 brp[1].write    = 1;
1052                 brp[1].address  = ARM11_SC7_BCR0;
1053                 brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
1054
1055                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
1056
1057                 /* resume */
1058
1059
1060                 if (arm11_config_step_irq_enable)
1061                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
1062                 else
1063                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
1064
1065
1066                 CHECK_RETVAL(arm11_leave_debug_state(arm11));
1067
1068                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
1069
1070                 CHECK_RETVAL(jtag_execute_queue());
1071
1072                 /** \todo TODO: add a timeout */
1073
1074                 /* wait for halt */
1075
1076                 while (1)
1077                 {
1078                         uint32_t dscr;
1079
1080                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
1081
1082                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
1083
1084                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
1085                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
1086                                 break;
1087                 }
1088
1089                 /* clear breakpoint */
1090                 arm11_sc7_clear_vbw(arm11);
1091
1092                 /* save state */
1093                 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
1094
1095             /* restore default state */
1096                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1097
1098         }
1099
1100         //        target->state         = TARGET_HALTED;
1101         target->debug_reason    = DBG_REASON_SINGLESTEP;
1102
1103         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1104
1105         if (R(PC) != next_pc)
1106         {
1107                 LOG_WARNING("next pc != simulated address %08" PRIx32 "!=%08" PRIx32, R(PC), next_pc);
1108         }
1109
1110         return ERROR_OK;
1111 }
1112
1113 /* target reset control */
1114 int arm11_assert_reset(struct target_s *target)
1115 {
1116         FNC_INFO;
1117
1118 #if 0
1119         /* assert reset lines */
1120         /* resets only the DBGTAP, not the ARM */
1121
1122         jtag_add_reset(1, 0);
1123         jtag_add_sleep(5000);
1124
1125         arm11_common_t * arm11 = target->arch_info;
1126         arm11->trst_active = true;
1127 #endif
1128
1129         if (target->reset_halt)
1130         {
1131                 CHECK_RETVAL(target_halt(target));
1132         }
1133
1134         return ERROR_OK;
1135 }
1136
1137 int arm11_deassert_reset(struct target_s *target)
1138 {
1139         FNC_INFO;
1140
1141 #if 0
1142         LOG_DEBUG("target->state: %s",
1143                 target_state_name(target));
1144
1145
1146         /* deassert reset lines */
1147         jtag_add_reset(0, 0);
1148
1149         arm11_common_t * arm11 = target->arch_info;
1150         arm11->trst_active = false;
1151
1152         if (arm11->halt_requested)
1153                 return arm11_halt(target);
1154 #endif
1155
1156         return ERROR_OK;
1157 }
1158
1159 int arm11_soft_reset_halt(struct target_s *target)
1160 {
1161         FNC_INFO_NOTIMPLEMENTED;
1162
1163         return ERROR_OK;
1164 }
1165
1166 /* target register access for gdb */
1167 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1168 {
1169         FNC_INFO;
1170
1171         arm11_common_t * arm11 = target->arch_info;
1172
1173         *reg_list_size  = ARM11_GDB_REGISTER_COUNT;
1174         *reg_list               = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1175
1176         for (size_t i = 16; i < 24; i++)
1177         {
1178                 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1179         }
1180
1181         (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1182
1183         for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1184         {
1185                 if (arm11_reg_defs[i].gdb_num == -1)
1186                         continue;
1187
1188                 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1189         }
1190
1191         return ERROR_OK;
1192 }
1193
1194 /* target memory access
1195  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1196  * count: number of items of <size>
1197  */
1198 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1199 {
1200         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1201
1202         FNC_INFO;
1203
1204         if (target->state != TARGET_HALTED)
1205         {
1206                 LOG_WARNING("target was not halted");
1207                 return ERROR_TARGET_NOT_HALTED;
1208         }
1209
1210         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1211
1212         arm11_common_t * arm11 = target->arch_info;
1213
1214         arm11_run_instr_data_prepare(arm11);
1215
1216         /* MRC p14,0,r0,c0,c5,0 */
1217         arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1218
1219         switch (size)
1220         {
1221         case 1:
1222                 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1223                 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1224
1225                 for (size_t i = 0; i < count; i++)
1226                 {
1227                         /* ldrb    r1, [r0], #1 */
1228                         /* ldrb    r1, [r0] */
1229                         arm11_run_instr_no_data1(arm11,
1230                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1231
1232                         uint32_t res;
1233                         /* MCR p14,0,R1,c0,c5,0 */
1234                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1235
1236                         *buffer++ = res;
1237                 }
1238
1239                 break;
1240
1241         case 2:
1242                 {
1243                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1244
1245                         for (size_t i = 0; i < count; i++)
1246                         {
1247                                 /* ldrh    r1, [r0], #2 */
1248                                 arm11_run_instr_no_data1(arm11,
1249                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1250
1251                                 uint32_t res;
1252
1253                                 /* MCR p14,0,R1,c0,c5,0 */
1254                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1255
1256                                 uint16_t svalue = res;
1257                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1258                         }
1259
1260                         break;
1261                 }
1262
1263         case 4:
1264                 {
1265                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1266                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1267                 uint32_t *words = (uint32_t *)buffer;
1268
1269                 /* LDC p14,c5,[R0],#4 */
1270                 /* LDC p14,c5,[R0] */
1271                 arm11_run_instr_data_from_core(arm11, instr, words, count);
1272                 break;
1273                 }
1274         }
1275
1276         arm11_run_instr_data_finish(arm11);
1277
1278         return ERROR_OK;
1279 }
1280
1281 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1282 {
1283         FNC_INFO;
1284
1285         if (target->state != TARGET_HALTED)
1286         {
1287                 LOG_WARNING("target was not halted");
1288                 return ERROR_TARGET_NOT_HALTED;
1289         }
1290
1291         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1292
1293         arm11_common_t * arm11 = target->arch_info;
1294
1295         arm11_run_instr_data_prepare(arm11);
1296
1297         /* MRC p14,0,r0,c0,c5,0 */
1298         arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1299
1300         switch (size)
1301         {
1302         case 1:
1303                 {
1304                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1305
1306                         for (size_t i = 0; i < count; i++)
1307                         {
1308                                 /* MRC p14,0,r1,c0,c5,0 */
1309                                 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1310
1311                                 /* strb    r1, [r0], #1 */
1312                                 /* strb    r1, [r0] */
1313                                 arm11_run_instr_no_data1(arm11,
1314                                         !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1315                         }
1316
1317                         break;
1318                 }
1319
1320         case 2:
1321                 {
1322                         arm11->reg_list[ARM11_RC_R1].dirty = 1;
1323
1324                         for (size_t i = 0; i < count; i++)
1325                         {
1326                                 uint16_t value;
1327                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1328
1329                                 /* MRC p14,0,r1,c0,c5,0 */
1330                                 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1331
1332                                 /* strh    r1, [r0], #2 */
1333                                 /* strh    r1, [r0] */
1334                                 arm11_run_instr_no_data1(arm11,
1335                                         !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1336                         }
1337
1338                         break;
1339                 }
1340
1341         case 4: {
1342                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1343
1344                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1345                 uint32_t *words = (uint32_t*)buffer;
1346
1347                 if (!arm11_config_memwrite_burst)
1348                 {
1349                         /* STC p14,c5,[R0],#4 */
1350                         /* STC p14,c5,[R0]*/
1351                         arm11_run_instr_data_to_core(arm11, instr, words, count);
1352                 }
1353                 else
1354                 {
1355                         /* STC p14,c5,[R0],#4 */
1356                         /* STC p14,c5,[R0]*/
1357                         arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1358                 }
1359
1360                 break;
1361         }
1362         }
1363
1364 #if 1
1365         /* r0 verification */
1366         if (!arm11_config_memrw_no_increment)
1367         {
1368                 uint32_t r0;
1369
1370                 /* MCR p14,0,R0,c0,c5,0 */
1371                 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1372
1373                 if (address + size * count != r0)
1374                 {
1375                         LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
1376
1377                         if (arm11_config_memwrite_burst)
1378                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1379
1380                         if (arm11_config_memwrite_error_fatal)
1381                                 return ERROR_FAIL;
1382                 }
1383         }
1384 #endif
1385
1386         arm11_run_instr_data_finish(arm11);
1387
1388         return ERROR_OK;
1389 }
1390
1391
1392 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1393 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1394 {
1395         FNC_INFO;
1396
1397         if (target->state != TARGET_HALTED)
1398         {
1399                 LOG_WARNING("target was not halted");
1400                 return ERROR_TARGET_NOT_HALTED;
1401         }
1402
1403         return arm11_write_memory(target, address, 4, count, buffer);
1404 }
1405
1406 /* here we have nothing target specific to contribute, so we fail and then the
1407  * fallback code will read data from the target and calculate the CRC on the
1408  * host.
1409  */
1410 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1411 {
1412         return ERROR_FAIL;
1413 }
1414
1415 /* target break-/watchpoint control
1416 * rw: 0 = write, 1 = read, 2 = access
1417 */
1418 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1419 {
1420         FNC_INFO;
1421
1422         arm11_common_t * arm11 = target->arch_info;
1423
1424 #if 0
1425         if (breakpoint->type == BKPT_SOFT)
1426         {
1427                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1428                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1429         }
1430 #endif
1431
1432         if (!arm11->free_brps)
1433         {
1434                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1435                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1436         }
1437
1438         if (breakpoint->length != 4)
1439         {
1440                 LOG_DEBUG("only breakpoints of four bytes length supported");
1441                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1442         }
1443
1444         arm11->free_brps--;
1445
1446         return ERROR_OK;
1447 }
1448
1449 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1450 {
1451         FNC_INFO;
1452
1453         arm11_common_t * arm11 = target->arch_info;
1454
1455         arm11->free_brps++;
1456
1457         return ERROR_OK;
1458 }
1459
1460 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1461 {
1462         FNC_INFO_NOTIMPLEMENTED;
1463
1464         return ERROR_OK;
1465 }
1466
1467 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1468 {
1469         FNC_INFO_NOTIMPLEMENTED;
1470
1471         return ERROR_OK;
1472 }
1473
1474 // HACKHACKHACK - FIXME mode/state
1475 /* target algorithm support */
1476 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1477                         int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1478                         int timeout_ms, void *arch_info)
1479 {
1480                 arm11_common_t *arm11 = target->arch_info;
1481 //      enum armv4_5_state core_state = arm11->core_state;
1482 //      enum armv4_5_mode core_mode = arm11->core_mode;
1483         uint32_t context[16];
1484         uint32_t cpsr;
1485         int exit_breakpoint_size = 0;
1486         int retval = ERROR_OK;
1487                 LOG_DEBUG("Running algorithm");
1488
1489
1490         if (target->state != TARGET_HALTED)
1491         {
1492                 LOG_WARNING("target not halted");
1493                 return ERROR_TARGET_NOT_HALTED;
1494         }
1495
1496         // FIXME
1497 //      if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1498 //              return ERROR_FAIL;
1499
1500         // Save regs
1501         for (size_t i = 0; i < 16; i++)
1502         {
1503                 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1504                 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1505         }
1506
1507         cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1508         LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1509
1510         for (int i = 0; i < num_mem_params; i++)
1511         {
1512                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1513         }
1514
1515         // Set register parameters
1516         for (int i = 0; i < num_reg_params; i++)
1517         {
1518                 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1519                 if (!reg)
1520                 {
1521                         LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1522                         exit(-1);
1523                 }
1524
1525                 if (reg->size != reg_params[i].size)
1526                 {
1527                         LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1528                         exit(-1);
1529                 }
1530                 arm11_set_reg(reg,reg_params[i].value);
1531 //              printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1532         }
1533
1534         exit_breakpoint_size = 4;
1535
1536 /*      arm11->core_state = arm11_algorithm_info->core_state;
1537         if (arm11->core_state == ARMV4_5_STATE_ARM)
1538                                 exit_breakpoint_size = 4;
1539         else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1540                 exit_breakpoint_size = 2;
1541         else
1542         {
1543                 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1544                 exit(-1);
1545         }
1546 */
1547
1548
1549 /* arm11 at this point only supports ARM not THUMB mode
1550    however if this test needs to be reactivated the current state can be read back
1551    from CPSR */
1552 #if 0
1553         if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1554         {
1555                 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1556                 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1557                 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1558                 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1559         }
1560 #endif
1561
1562         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1563         {
1564                 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1565                 retval = ERROR_TARGET_FAILURE;
1566                 goto restore;
1567         }
1568
1569         // no debug, otherwise breakpoint is not set
1570         CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1571
1572         CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1573
1574         if (target->state != TARGET_HALTED)
1575         {
1576                 CHECK_RETVAL(target_halt(target));
1577
1578                 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1579
1580                 retval = ERROR_TARGET_TIMEOUT;
1581
1582                 goto del_breakpoint;
1583         }
1584
1585         if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1586         {
1587                 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1588                         buf_get_u32(arm11->reg_list[15].value, 0, 32));
1589                 retval = ERROR_TARGET_TIMEOUT;
1590                 goto del_breakpoint;
1591         }
1592
1593         for (int i = 0; i < num_mem_params; i++)
1594         {
1595                 if (mem_params[i].direction != PARAM_OUT)
1596                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1597         }
1598
1599         for (int i = 0; i < num_reg_params; i++)
1600         {
1601                 if (reg_params[i].direction != PARAM_OUT)
1602                 {
1603                         reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1604                         if (!reg)
1605                         {
1606                                 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1607                                 exit(-1);
1608                         }
1609
1610                         if (reg->size != reg_params[i].size)
1611                         {
1612                                 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1613                                 exit(-1);
1614                         }
1615
1616                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1617                 }
1618         }
1619
1620 del_breakpoint:
1621         breakpoint_remove(target, exit_point);
1622
1623 restore:
1624         // Restore context
1625         for (size_t i = 0; i < 16; i++)
1626         {
1627                 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1628                          arm11->reg_list[i].name, context[i]);
1629                 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1630         }
1631         LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1632         arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1633
1634 //      arm11->core_state = core_state;
1635 //      arm11->core_mode = core_mode;
1636
1637         return retval;
1638 }
1639
1640 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1641 {
1642         FNC_INFO;
1643
1644         NEW(arm11_common_t, arm11, 1);
1645
1646         arm11->target = target;
1647
1648         if (target->tap == NULL)
1649                 return ERROR_FAIL;
1650
1651         if (target->tap->ir_length != 5)
1652         {
1653                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1654                 return ERROR_COMMAND_SYNTAX_ERROR;
1655         }
1656
1657         target->arch_info = arm11;
1658
1659         return ERROR_OK;
1660 }
1661
1662 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1663 {
1664         /* Initialize anything we can set up without talking to the target */
1665         return arm11_build_reg_cache(target);
1666 }
1667
1668 /* talk to the target and set things up */
1669 int arm11_examine(struct target_s *target)
1670 {
1671         FNC_INFO;
1672
1673         arm11_common_t * arm11 = target->arch_info;
1674
1675         /* check IDCODE */
1676
1677         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1678
1679         scan_field_t            idcode_field;
1680
1681         arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1682
1683         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1684
1685         /* check DIDR */
1686
1687         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1688
1689         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1690
1691         scan_field_t            chain0_fields[2];
1692
1693         arm11_setup_field(arm11, 32, NULL,      &arm11->didr,           chain0_fields + 0);
1694         arm11_setup_field(arm11,  8, NULL,      &arm11->implementor,    chain0_fields + 1);
1695
1696         arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1697
1698         CHECK_RETVAL(jtag_execute_queue());
1699
1700         switch (arm11->device_id & 0x0FFFF000)
1701         {
1702         case 0x07B36000:        LOG_INFO("found ARM1136"); break;
1703         case 0x07B56000:        LOG_INFO("found ARM1156"); break;
1704         case 0x07B76000:        LOG_INFO("found ARM1176"); break;
1705         default:
1706         {
1707                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1708                 return ERROR_FAIL;
1709         }
1710         }
1711
1712         arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1713
1714         if (arm11->debug_version != ARM11_DEBUG_V6 &&
1715                 arm11->debug_version != ARM11_DEBUG_V61)
1716         {
1717                 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1718                 return ERROR_FAIL;
1719         }
1720
1721         arm11->brp      = ((arm11->didr >> 24) & 0x0F) + 1;
1722         arm11->wrp      = ((arm11->didr >> 28) & 0x0F) + 1;
1723
1724         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1725         arm11->free_brps = arm11->brp;
1726         arm11->free_wrps = arm11->wrp;
1727
1728         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1729                 arm11->device_id,
1730                 (int)(arm11->implementor),
1731                 arm11->didr);
1732
1733         /* as a side-effect this reads DSCR and thus
1734          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1735          * as suggested by the spec.
1736          */
1737
1738         arm11_check_init(arm11, NULL);
1739
1740         target_set_examined(target);
1741
1742         return ERROR_OK;
1743 }
1744
1745 int arm11_quit(void)
1746 {
1747         FNC_INFO_NOTIMPLEMENTED;
1748
1749         return ERROR_OK;
1750 }
1751
1752 /** Load a register that is marked !valid in the register cache */
1753 int arm11_get_reg(reg_t *reg)
1754 {
1755         FNC_INFO;
1756
1757         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1758
1759         if (target->state != TARGET_HALTED)
1760         {
1761                 LOG_WARNING("target was not halted");
1762                 return ERROR_TARGET_NOT_HALTED;
1763         }
1764
1765         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1766
1767 #if 0
1768         arm11_common_t *arm11 = target->arch_info;
1769         const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1770 #endif
1771
1772         return ERROR_OK;
1773 }
1774
1775 /** Change a value in the register cache */
1776 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1777 {
1778         FNC_INFO;
1779
1780         target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1781         arm11_common_t *arm11 = target->arch_info;
1782 //        const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1783
1784         arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1785         reg->valid      = 1;
1786         reg->dirty      = 1;
1787
1788         return ERROR_OK;
1789 }
1790
1791 int arm11_build_reg_cache(target_t *target)
1792 {
1793         arm11_common_t *arm11 = target->arch_info;
1794
1795         NEW(reg_cache_t,                cache,                          1);
1796         NEW(reg_t,                              reg_list,                       ARM11_REGCACHE_COUNT);
1797         NEW(arm11_reg_state_t,  arm11_reg_states,       ARM11_REGCACHE_COUNT);
1798
1799         if (arm11_regs_arch_type == -1)
1800                 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1801
1802         register_init_dummy(&arm11_gdb_dummy_fp_reg);
1803         register_init_dummy(&arm11_gdb_dummy_fps_reg);
1804
1805         arm11->reg_list = reg_list;
1806
1807         /* Build the process context cache */
1808         cache->name             = "arm11 registers";
1809         cache->next             = NULL;
1810         cache->reg_list = reg_list;
1811         cache->num_regs = ARM11_REGCACHE_COUNT;
1812
1813         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1814         (*cache_p) = cache;
1815
1816         arm11->core_cache = cache;
1817 //        armv7m->process_context = cache;
1818
1819         size_t i;
1820
1821         /* Not very elegant assertion */
1822         if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1823                 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1824                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1825         {
1826                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1827                 exit(-1);
1828         }
1829
1830         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1831         {
1832                 reg_t *                                         r       = reg_list                      + i;
1833                 const arm11_reg_defs_t *        rd      = arm11_reg_defs        + i;
1834                 arm11_reg_state_t *                     rs      = arm11_reg_states      + i;
1835
1836                 r->name                         = rd->name;
1837                 r->size                         = 32;
1838                 r->value                        = (uint8_t *)(arm11->reg_values + i);
1839                 r->dirty                        = 0;
1840                 r->valid                        = 0;
1841                 r->bitfield_desc        = NULL;
1842                 r->num_bitfields        = 0;
1843                 r->arch_type            = arm11_regs_arch_type;
1844                 r->arch_info            = rs;
1845
1846                 rs->def_index           = i;
1847                 rs->target                      = target;
1848         }
1849
1850         return ERROR_OK;
1851 }
1852
1853 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1854 {
1855         if (argc == 0)
1856         {
1857                 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1858                 return ERROR_OK;
1859         }
1860
1861         if (argc != 1)
1862                 return ERROR_COMMAND_SYNTAX_ERROR;
1863
1864         switch (args[0][0])
1865         {
1866         case '0':       /* 0 */
1867         case 'f':       /* false */
1868         case 'F':
1869         case 'd':       /* disable */
1870         case 'D':
1871                 *var = false;
1872                 break;
1873
1874         case '1':       /* 1 */
1875         case 't':       /* true */
1876         case 'T':
1877         case 'e':       /* enable */
1878         case 'E':
1879                 *var = true;
1880                 break;
1881         }
1882
1883         LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1884
1885         return ERROR_OK;
1886 }
1887
1888 #define BOOL_WRAPPER(name, print_name)  \
1889 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1890 { \
1891         return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1892 }
1893
1894 #define RC_TOP(name, descr, more)  \
1895 { \
1896         command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr);  \
1897         command_t * top_cmd = new_cmd; \
1898         more \
1899 }
1900
1901 #define RC_FINAL(name, descr, handler)  \
1902         register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1903
1904 #define RC_FINAL_BOOL(name, descr, var)  \
1905         register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1906
1907 BOOL_WRAPPER(memwrite_burst,                    "memory write burst mode")
1908 BOOL_WRAPPER(memwrite_error_fatal,              "fatal error mode for memory writes")
1909 BOOL_WRAPPER(memrw_no_increment,                "\"no increment\" mode for memory transfers")
1910 BOOL_WRAPPER(step_irq_enable,                   "IRQs while stepping")
1911
1912 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1913 {
1914         if (argc == 1)
1915         {
1916                 arm11_vcr = strtoul(args[0], NULL, 0);
1917         }
1918         else if (argc != 0)
1919         {
1920                 return ERROR_COMMAND_SYNTAX_ERROR;
1921         }
1922
1923         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1924         return ERROR_OK;
1925 }
1926
1927 const uint32_t arm11_coproc_instruction_limits[] =
1928 {
1929         15,                             /* coprocessor */
1930         7,                              /* opcode 1 */
1931         15,                             /* CRn */
1932         15,                             /* CRm */
1933         7,                              /* opcode 2 */
1934         0xFFFFFFFF,             /* value */
1935 };
1936
1937 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1938 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1939
1940 arm11_common_t * arm11_find_target(const char * arg)
1941 {
1942         jtag_tap_t *    tap;
1943         target_t *              t;
1944
1945         tap = jtag_tap_by_string(arg);
1946
1947         if (!tap)
1948                 return 0;
1949
1950         for (t = all_targets; t; t = t->next)
1951         {
1952                 if (t->tap != tap)
1953                         continue;
1954
1955                 /* if (t->type == arm11_target) */
1956                 if (0 == strcmp(target_get_name(t), "arm11"))
1957                         return t->arch_info;
1958         }
1959
1960         return 0;
1961 }
1962
1963 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1964 {
1965         if (argc != (read ? 6 : 7))
1966         {
1967                 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1968                 return -1;
1969         }
1970
1971         arm11_common_t * arm11 = arm11_find_target(args[0]);
1972
1973         if (!arm11)
1974         {
1975                 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1976                         read ? arm11_mrc_syntax : arm11_mcr_syntax);
1977
1978                 return -1;
1979         }
1980
1981         if (arm11->target->state != TARGET_HALTED)
1982         {
1983                 LOG_WARNING("target was not halted");
1984                 return ERROR_TARGET_NOT_HALTED;
1985         }
1986
1987         uint32_t        values[6];
1988
1989         for (size_t i = 0; i < (read ? 5 : 6); i++)
1990         {
1991                 values[i] = strtoul(args[i + 1], NULL, 0);
1992
1993                 if (values[i] > arm11_coproc_instruction_limits[i])
1994                 {
1995                         LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
1996                                   (long)(i + 2),
1997                                   arm11_coproc_instruction_limits[i],
1998                                 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1999                         return -1;
2000                 }
2001         }
2002
2003         uint32_t instr = 0xEE000010     |
2004                 (values[0] <<  8) |
2005                 (values[1] << 21) |
2006                 (values[2] << 16) |
2007                 (values[3] <<  0) |
2008                 (values[4] <<  5);
2009
2010         if (read)
2011                 instr |= 0x00100000;
2012
2013         arm11_run_instr_data_prepare(arm11);
2014
2015         if (read)
2016         {
2017                 uint32_t result;
2018                 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
2019
2020                 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
2021                          (int)(values[0]),
2022                          (int)(values[1]),
2023                          (int)(values[2]),
2024                          (int)(values[3]),
2025                          (int)(values[4]), result, result);
2026         }
2027         else
2028         {
2029                 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
2030
2031                 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
2032                          (int)(values[0]), (int)(values[1]),
2033                          values[5],
2034                          (int)(values[2]), (int)(values[3]), (int)(values[4]));
2035         }
2036
2037         arm11_run_instr_data_finish(arm11);
2038
2039
2040         return ERROR_OK;
2041 }
2042
2043 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2044 {
2045         return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
2046 }
2047
2048 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2049 {
2050         return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
2051 }
2052
2053 int arm11_register_commands(struct command_context_s *cmd_ctx)
2054 {
2055         FNC_INFO;
2056
2057         command_t * top_cmd = NULL;
2058
2059         RC_TOP("arm11",                         "arm11 specific commands",
2060
2061         RC_TOP("memwrite",                              "Control memory write transfer mode",
2062
2063                 RC_FINAL_BOOL("burst",                          "Enable/Disable non-standard but fast burst mode (default: enabled)",
2064                                                 memwrite_burst)
2065
2066                 RC_FINAL_BOOL("error_fatal",                    "Terminate program if transfer error was found (default: enabled)",
2067                                                 memwrite_error_fatal)
2068 ) /* memwrite */
2069
2070         RC_FINAL_BOOL("no_increment",                   "Don't increment address on multi-read/-write (default: disabled)",
2071                                                 memrw_no_increment)
2072
2073         RC_FINAL_BOOL("step_irq_enable",                "Enable interrupts while stepping (default: disabled)",
2074                                                 step_irq_enable)
2075
2076         RC_FINAL("vcr",                                 "Control (Interrupt) Vector Catch Register",
2077                                                 arm11_handle_vcr)
2078
2079         RC_FINAL("mrc",                                 "Read Coprocessor register",
2080                                                 arm11_handle_mrc)
2081
2082         RC_FINAL("mcr",                                 "Write Coprocessor register",
2083                                                 arm11_handle_mcr)
2084 ) /* arm11 */
2085
2086         return ERROR_OK;
2087 }