1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
31 #define _DEBUG_INSTRUCTION_EXECUTION_
36 #define FNC_INFO DEBUG("-")
42 #define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
44 #define FNC_INFO_NOTIMPLEMENTED
47 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
50 int arm11_config_memwrite_burst = 1;
51 int arm11_config_memwrite_error_fatal = 1;
55 #define ARM11_HANDLER(x) \
58 target_type_t arm11_target =
63 ARM11_HANDLER(arch_state),
65 ARM11_HANDLER(target_request_data),
68 ARM11_HANDLER(resume),
71 ARM11_HANDLER(assert_reset),
72 ARM11_HANDLER(deassert_reset),
73 ARM11_HANDLER(soft_reset_halt),
74 ARM11_HANDLER(prepare_reset_halt),
76 ARM11_HANDLER(get_gdb_reg_list),
78 ARM11_HANDLER(read_memory),
79 ARM11_HANDLER(write_memory),
81 ARM11_HANDLER(bulk_write_memory),
83 ARM11_HANDLER(checksum_memory),
85 ARM11_HANDLER(add_breakpoint),
86 ARM11_HANDLER(remove_breakpoint),
87 ARM11_HANDLER(add_watchpoint),
88 ARM11_HANDLER(remove_watchpoint),
90 ARM11_HANDLER(run_algorithm),
92 ARM11_HANDLER(register_commands),
93 ARM11_HANDLER(target_command),
94 ARM11_HANDLER(init_target),
98 int arm11_regs_arch_type = -1;
116 ARM11_REGISTER_SPSR_FIQ,
117 ARM11_REGISTER_SPSR_SVC,
118 ARM11_REGISTER_SPSR_ABT,
119 ARM11_REGISTER_SPSR_IRQ,
120 ARM11_REGISTER_SPSR_UND,
121 ARM11_REGISTER_SPSR_MON,
130 typedef struct arm11_reg_defs_s
135 enum arm11_regtype type;
138 /* update arm11_regcache_ids when changing this */
139 static const arm11_reg_defs_t arm11_reg_defs[] =
141 {"r0", 0, 0, ARM11_REGISTER_CORE},
142 {"r1", 1, 1, ARM11_REGISTER_CORE},
143 {"r2", 2, 2, ARM11_REGISTER_CORE},
144 {"r3", 3, 3, ARM11_REGISTER_CORE},
145 {"r4", 4, 4, ARM11_REGISTER_CORE},
146 {"r5", 5, 5, ARM11_REGISTER_CORE},
147 {"r6", 6, 6, ARM11_REGISTER_CORE},
148 {"r7", 7, 7, ARM11_REGISTER_CORE},
149 {"r8", 8, 8, ARM11_REGISTER_CORE},
150 {"r9", 9, 9, ARM11_REGISTER_CORE},
151 {"r10", 10, 10, ARM11_REGISTER_CORE},
152 {"r11", 11, 11, ARM11_REGISTER_CORE},
153 {"r12", 12, 12, ARM11_REGISTER_CORE},
154 {"sp", 13, 13, ARM11_REGISTER_CORE},
155 {"lr", 14, 14, ARM11_REGISTER_CORE},
156 {"pc", 15, 15, ARM11_REGISTER_CORE},
158 #if ARM11_REGCACHE_FREGS
159 {"f0", 0, 16, ARM11_REGISTER_FX},
160 {"f1", 1, 17, ARM11_REGISTER_FX},
161 {"f2", 2, 18, ARM11_REGISTER_FX},
162 {"f3", 3, 19, ARM11_REGISTER_FX},
163 {"f4", 4, 20, ARM11_REGISTER_FX},
164 {"f5", 5, 21, ARM11_REGISTER_FX},
165 {"f6", 6, 22, ARM11_REGISTER_FX},
166 {"f7", 7, 23, ARM11_REGISTER_FX},
167 {"fps", 0, 24, ARM11_REGISTER_FPS},
170 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
172 #if ARM11_REGCACHE_MODEREGS
173 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
174 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
175 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
176 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
177 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
178 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
179 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
180 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
182 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
183 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
184 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
186 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
187 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
188 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
190 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
191 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
192 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
194 {"r13_und", 13, -1, ARM11_REGISTER_UND},
195 {"r14_und", 14, -1, ARM11_REGISTER_UND},
196 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
199 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
200 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
201 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
204 /* Debug Registers */
205 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
206 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
207 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
210 enum arm11_regcache_ids
213 ARM11_RC_RX = ARM11_RC_R0,
228 ARM11_RC_SP = ARM11_RC_R13,
230 ARM11_RC_LR = ARM11_RC_R14,
232 ARM11_RC_PC = ARM11_RC_R15,
234 #if ARM11_REGCACHE_FREGS
236 ARM11_RC_FX = ARM11_RC_F0,
249 #if ARM11_REGCACHE_MODEREGS
288 #define ARM11_GDB_REGISTER_COUNT 26
290 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
292 reg_t arm11_gdb_dummy_fp_reg =
294 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
297 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
299 reg_t arm11_gdb_dummy_fps_reg =
301 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 /** Check and if necessary take control of the system
308 * \param arm11 Target state variable.
309 * \param dscr If the current DSCR content is
310 * available a pointer to a word holding the
311 * DSCR can be passed. Otherwise use NULL.
313 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
317 u32 dscr_local_tmp_copy;
321 dscr = &dscr_local_tmp_copy;
322 *dscr = arm11_read_DSCR(arm11);
325 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
327 DEBUG("Bringing target into debug mode");
329 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
330 arm11_write_DSCR(arm11, *dscr);
332 /* add further reset initialization here */
334 if (*dscr & ARM11_DSCR_CORE_HALTED)
336 arm11->target->state = TARGET_HALTED;
337 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
341 arm11->target->state = TARGET_RUNNING;
342 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
345 arm11_sc7_clear_vbw(arm11);
352 (arm11->reg_values[ARM11_RC_##x])
354 /** Save processor state.
356 * This is called when the HALT instruction has succeeded
357 * or on other occasions that stop the processor.
360 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
365 for(i = 0; i < asizeof(arm11->reg_values); i++)
367 arm11->reg_list[i].valid = 1;
368 arm11->reg_list[i].dirty = 0;
373 R(DSCR) = arm11_read_DSCR(arm11);
377 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
379 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
381 arm11_add_IR(arm11, ARM11_INTEST, -1);
383 scan_field_t chain5_fields[3];
385 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
386 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
387 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
389 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
393 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
397 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
398 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
399 ARM1136 seems to require this to issue ITR's as well */
401 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
403 /* this executes JTAG queue: */
405 arm11_write_DSCR(arm11, new_dscr);
407 // jtag_execute_queue();
411 // DEBUG("SAVE DSCR %08x", R(DSCR));
413 // if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
414 // DEBUG("SAVE wDTR %08x", R(WDTR));
418 Before executing any instruction in debug state you have to drain the write buffer.
419 This ensures that no imprecise Data Aborts can return at a later point:*/
421 /** \todo TODO: Test drain write buffer. */
426 /* MRC p14,0,R0,c5,c10,0 */
427 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
429 /* mcr 15, 0, r0, cr7, cr10, {4} */
430 arm11_run_instr_no_data1(arm11, 0xee070f9a);
432 u32 dscr = arm11_read_DSCR(arm11);
434 DEBUG("DRAIN, DSCR %08x", dscr);
436 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
438 arm11_run_instr_no_data1(arm11, 0xe320f000);
440 dscr = arm11_read_DSCR(arm11);
442 DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
450 arm11_run_instr_data_prepare(arm11);
455 /** \todo TODO: handle other mode registers */
458 for (i = 0; i < 15; i++)
460 /* MCR p14,0,R?,c0,c5,0 */
461 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
467 /* check rDTRfull in DSCR */
469 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
471 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
472 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
476 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
481 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
482 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
486 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
487 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
489 /* adjust PC depending on ARM state */
491 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
493 arm11->reg_values[ARM11_RC_PC] -= 0;
495 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
497 arm11->reg_values[ARM11_RC_PC] -= 4;
501 arm11->reg_values[ARM11_RC_PC] -= 8;
504 // DEBUG("SAVE PC %08x", R(PC));
506 arm11_run_instr_data_finish(arm11);
508 arm11_dump_reg_changes(arm11);
511 void arm11_dump_reg_changes(arm11_common_t * arm11)
514 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
516 if (!arm11->reg_list[i].valid)
518 if (arm11->reg_history[i].valid)
519 INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
523 if (arm11->reg_history[i].valid)
525 if (arm11->reg_history[i].value != arm11->reg_values[i])
526 INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
530 INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
537 /** Restore processor state
539 * This is called in preparation for the RESTART function.
542 void arm11_leave_debug_state(arm11_common_t * arm11)
546 arm11_run_instr_data_prepare(arm11);
548 /** \todo TODO: handle other mode registers */
550 /* restore R1 - R14 */
552 for (i = 1; i < 15; i++)
554 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
557 /* MRC p14,0,r?,c0,c5,0 */
558 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
560 // DEBUG("RESTORE R%d %08x", i, R(RX + i));
563 arm11_run_instr_data_finish(arm11);
566 /* spec says clear wDTR and rDTR; we assume they are clear as
567 otherwise our programming would be sloppy */
570 u32 DSCR = arm11_read_DSCR(arm11);
572 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
574 ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
578 arm11_run_instr_data_prepare(arm11);
580 /* restore original wDTR */
582 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
584 /* MCR p14,0,R0,c0,c5,0 */
585 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
591 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
597 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
602 /* MRC p14,0,r0,c0,c5,0 */
603 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
605 arm11_run_instr_data_finish(arm11);
610 arm11_write_DSCR(arm11, R(DSCR));
615 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
617 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
619 arm11_add_IR(arm11, ARM11_EXTEST, -1);
621 scan_field_t chain5_fields[3];
623 u8 Ready = 0; /* ignored */
624 u8 Valid = 0; /* ignored */
626 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
627 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
628 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
630 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
633 arm11_record_register_history(arm11);
636 void arm11_record_register_history(arm11_common_t * arm11)
639 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
641 arm11->reg_history[i].value = arm11->reg_values[i];
642 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
644 arm11->reg_list[i].valid = 0;
645 arm11->reg_list[i].dirty = 0;
650 /* poll current target status */
651 int arm11_poll(struct target_s *target)
655 arm11_common_t * arm11 = target->arch_info;
657 if (arm11->trst_active)
660 u32 dscr = arm11_read_DSCR(arm11);
662 DEBUG("DSCR %08x", dscr);
664 arm11_check_init(arm11, &dscr);
666 if (dscr & ARM11_DSCR_CORE_HALTED)
668 if (target->state != TARGET_HALTED)
670 enum target_state old_state = target->state;
672 DEBUG("enter TARGET_HALTED");
673 target->state = TARGET_HALTED;
674 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
675 arm11_on_enter_debug_state(arm11);
677 target_call_event_callbacks(target,
678 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
683 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
685 DEBUG("enter TARGET_RUNNING");
686 target->state = TARGET_RUNNING;
687 target->debug_reason = DBG_REASON_NOTHALTED;
693 /* architecture specific status reply */
694 int arm11_arch_state(struct target_s *target)
696 FNC_INFO_NOTIMPLEMENTED;
702 /* target request support */
703 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
705 FNC_INFO_NOTIMPLEMENTED;
712 /* target execution control */
713 int arm11_halt(struct target_s *target)
717 arm11_common_t * arm11 = target->arch_info;
719 DEBUG("target->state: %s", target_state_strings[target->state]);
721 if (target->state == TARGET_HALTED)
723 WARNING("target was already halted");
724 return ERROR_TARGET_ALREADY_HALTED;
727 if (arm11->trst_active)
729 arm11->halt_requested = 1;
733 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
735 jtag_execute_queue();
741 dscr = arm11_read_DSCR(arm11);
743 if (dscr & ARM11_DSCR_CORE_HALTED)
747 arm11_on_enter_debug_state(arm11);
749 enum target_state old_state = target->state;
751 target->state = TARGET_HALTED;
752 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
754 target_call_event_callbacks(target,
755 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
761 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
765 // DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
766 // current, address, handle_breakpoints, debug_execution);
768 arm11_common_t * arm11 = target->arch_info;
770 DEBUG("target->state: %s", target_state_strings[target->state]);
772 if (target->state != TARGET_HALTED)
774 WARNING("target was not halted");
775 return ERROR_TARGET_NOT_HALTED;
781 INFO("RESUME PC %08x", R(PC));
783 /* clear breakpoints/watchpoints and VCR*/
784 arm11_sc7_clear_vbw(arm11);
786 /* Set up breakpoints */
787 if (!debug_execution)
789 /* check if one matches PC and step over it if necessary */
793 for (bp = target->breakpoints; bp; bp = bp->next)
795 if (bp->address == R(PC))
797 DEBUG("must step over %08x", bp->address);
798 arm11_step(target, 1, 0, 0);
803 /* set all breakpoints */
807 for (bp = target->breakpoints; bp; bp = bp->next)
809 arm11_sc7_action_t brp[2];
812 brp[0].address = ARM11_SC7_BVR0 + brp_num;
813 brp[0].value = bp->address;
815 brp[1].address = ARM11_SC7_BCR0 + brp_num;
816 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
818 arm11_sc7_run(arm11, brp, asizeof(brp));
820 DEBUG("Add BP %d at %08x", brp_num, bp->address);
825 arm11_sc7_set_vcr(arm11, arm11_vcr);
829 arm11_leave_debug_state(arm11);
831 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
833 jtag_execute_queue();
837 u32 dscr = arm11_read_DSCR(arm11);
839 DEBUG("DSCR %08x", dscr);
841 if (dscr & ARM11_DSCR_CORE_RESTARTED)
845 if (!debug_execution)
847 target->state = TARGET_RUNNING;
848 target->debug_reason = DBG_REASON_NOTHALTED;
849 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
853 target->state = TARGET_DEBUG_RUNNING;
854 target->debug_reason = DBG_REASON_NOTHALTED;
855 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
861 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
865 DEBUG("target->state: %s", target_state_strings[target->state]);
867 if (target->state != TARGET_HALTED)
869 WARNING("target was not halted");
870 return ERROR_TARGET_NOT_HALTED;
873 arm11_common_t * arm11 = target->arch_info;
878 INFO("STEP PC %08x", R(PC));
880 /** \todo TODO: Thumb not supported here */
882 u32 next_instruction;
884 arm11_read_memory_word(arm11, R(PC), &next_instruction);
886 /** skip over BKPT */
887 if ((next_instruction & 0xFFF00070) == 0xe1200070)
890 arm11->reg_list[ARM11_RC_PC].valid = 1;
891 arm11->reg_list[ARM11_RC_PC].dirty = 0;
892 INFO("Skipping BKPT");
894 /* ignore B to self */
895 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
897 INFO("Not stepping jump to self");
901 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
904 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
905 * the VCR might be something worth looking into. */
908 /* Set up breakpoint for stepping */
910 arm11_sc7_action_t brp[2];
913 brp[0].address = ARM11_SC7_BVR0;
914 brp[0].value = R(PC);
916 brp[1].address = ARM11_SC7_BCR0;
917 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
919 arm11_sc7_run(arm11, brp, asizeof(brp));
923 arm11_leave_debug_state(arm11);
925 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
927 jtag_execute_queue();
929 /** \todo TODO: add a timeout */
935 u32 dscr = arm11_read_DSCR(arm11);
937 DEBUG("DSCR %08x", dscr);
939 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
940 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
944 /* clear breakpoint */
945 arm11_sc7_clear_vbw(arm11);
948 arm11_on_enter_debug_state(arm11);
951 // target->state = TARGET_HALTED;
952 target->debug_reason = DBG_REASON_SINGLESTEP;
954 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
960 /* target reset control */
961 int arm11_assert_reset(struct target_s *target)
966 /* assert reset lines */
967 /* resets only the DBGTAP, not the ARM */
969 jtag_add_reset(1, 0);
970 jtag_add_sleep(5000);
972 arm11_common_t * arm11 = target->arch_info;
973 arm11->trst_active = 1;
979 int arm11_deassert_reset(struct target_s *target)
984 DEBUG("target->state: %s", target_state_strings[target->state]);
986 /* deassert reset lines */
987 jtag_add_reset(0, 0);
989 arm11_common_t * arm11 = target->arch_info;
990 arm11->trst_active = false;
992 if (arm11->halt_requested)
993 return arm11_halt(target);
999 int arm11_soft_reset_halt(struct target_s *target)
1001 FNC_INFO_NOTIMPLEMENTED;
1006 int arm11_prepare_reset_halt(struct target_s *target)
1008 FNC_INFO_NOTIMPLEMENTED;
1014 /* target register access for gdb */
1015 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1019 arm11_common_t * arm11 = target->arch_info;
1021 if (target->state != TARGET_HALTED)
1023 return ERROR_TARGET_NOT_HALTED;
1026 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1027 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1030 for (i = 16; i < 24; i++)
1032 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1035 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1039 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1041 if (arm11_reg_defs[i].gdb_num == -1)
1044 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1051 /* target memory access
1052 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1053 * count: number of items of <size>
1055 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1057 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1061 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1063 arm11_common_t * arm11 = target->arch_info;
1065 arm11_run_instr_data_prepare(arm11);
1067 /* MRC p14,0,r0,c0,c5,0 */
1068 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1073 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1074 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1078 /* ldrb r1, [r0], #1 */
1079 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1082 /* MCR p14,0,R1,c0,c5,0 */
1083 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1091 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1093 u16 * buf16 = (u16*)buffer;
1097 /* ldrh r1, [r0], #2 */
1098 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1102 /* MCR p14,0,R1,c0,c5,0 */
1103 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1112 /* LDC p14,c5,[R0],#4 */
1113 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1117 arm11_run_instr_data_finish(arm11);
1122 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1126 DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1128 arm11_common_t * arm11 = target->arch_info;
1130 arm11_run_instr_data_prepare(arm11);
1132 /* MRC p14,0,r0,c0,c5,0 */
1133 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1138 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1142 /* MRC p14,0,r1,c0,c5,0 */
1143 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1145 /* strb r1, [r0], #1 */
1146 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1152 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1154 u16 * buf16 = (u16*)buffer;
1158 /* MRC p14,0,r1,c0,c5,0 */
1159 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1161 /* strh r1, [r0], #2 */
1162 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1168 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1170 if (!arm11_config_memwrite_burst)
1172 /* STC p14,c5,[R0],#4 */
1173 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1177 /* STC p14,c5,[R0],#4 */
1178 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1185 /* r0 verification */
1189 /* MCR p14,0,R0,c0,c5,0 */
1190 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1192 if (address + size * count != r0)
1194 ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1196 if (arm11_config_memwrite_burst)
1197 ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1199 if (arm11_config_memwrite_error_fatal)
1206 arm11_run_instr_data_finish(arm11);
1215 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1216 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1220 return arm11_write_memory(target, address, 4, count, buffer);
1224 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1226 FNC_INFO_NOTIMPLEMENTED;
1232 /* target break-/watchpoint control
1233 * rw: 0 = write, 1 = read, 2 = access
1235 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1239 arm11_common_t * arm11 = target->arch_info;
1242 if (breakpoint->type == BKPT_SOFT)
1244 INFO("sw breakpoint requested, but software breakpoints not enabled");
1245 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1249 if (!arm11->free_brps)
1251 INFO("no breakpoint unit available for hardware breakpoint");
1252 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1255 if (breakpoint->length != 4)
1257 INFO("only breakpoints of four bytes length supported");
1258 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1266 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1270 arm11_common_t * arm11 = target->arch_info;
1277 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1279 FNC_INFO_NOTIMPLEMENTED;
1284 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1286 FNC_INFO_NOTIMPLEMENTED;
1292 /* target algorithm support */
1293 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1295 FNC_INFO_NOTIMPLEMENTED;
1300 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1306 ERROR("'target arm11' 4th argument <jtag chain pos>");
1310 int chain_pos = strtoul(args[3], NULL, 0);
1312 NEW(arm11_common_t, arm11, 1);
1314 arm11->target = target;
1316 /* prepare JTAG information for the new target */
1317 arm11->jtag_info.chain_pos = chain_pos;
1318 arm11->jtag_info.scann_size = 5;
1320 arm_jtag_setup_connection(&arm11->jtag_info);
1322 jtag_device_t *device = jtag_get_device(chain_pos);
1324 if (device->ir_length != 5)
1326 ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1330 target->arch_info = arm11;
1335 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1339 arm11_common_t * arm11 = target->arch_info;
1343 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1345 scan_field_t idcode_field;
1347 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1349 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1353 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1355 arm11_add_IR(arm11, ARM11_INTEST, -1);
1357 scan_field_t chain0_fields[2];
1359 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1360 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1362 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1364 jtag_execute_queue();
1367 switch (arm11->device_id & 0x0FFFF000)
1369 case 0x07B36000: INFO("found ARM1136"); break;
1370 case 0x07B56000: INFO("found ARM1156"); break;
1371 case 0x07B76000: INFO("found ARM1176"); break;
1374 ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1379 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1381 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1382 arm11->debug_version != ARM11_DEBUG_V61)
1384 ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1389 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1390 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1392 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1393 arm11->free_brps = arm11->brp;
1394 arm11->free_wrps = arm11->wrp;
1396 DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1401 arm11_build_reg_cache(target);
1404 /* as a side-effect this reads DSCR and thus
1405 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1406 * as suggested by the spec.
1409 arm11_check_init(arm11, NULL);
1414 int arm11_quit(void)
1416 FNC_INFO_NOTIMPLEMENTED;
1421 /** Load a register that is marked !valid in the register cache */
1422 int arm11_get_reg(reg_t *reg)
1426 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1428 if (target->state != TARGET_HALTED)
1430 return ERROR_TARGET_NOT_HALTED;
1433 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1436 arm11_common_t *arm11 = target->arch_info;
1437 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1443 /** Change a value in the register cache */
1444 int arm11_set_reg(reg_t *reg, u8 *buf)
1448 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1449 arm11_common_t *arm11 = target->arch_info;
1450 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1452 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1460 void arm11_build_reg_cache(target_t *target)
1462 arm11_common_t *arm11 = target->arch_info;
1464 NEW(reg_cache_t, cache, 1);
1465 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1466 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1468 if (arm11_regs_arch_type == -1)
1469 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1471 arm11->reg_list = reg_list;
1473 /* Build the process context cache */
1474 cache->name = "arm11 registers";
1476 cache->reg_list = reg_list;
1477 cache->num_regs = ARM11_REGCACHE_COUNT;
1479 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1482 // armv7m->core_cache = cache;
1483 // armv7m->process_context = cache;
1487 /* Not very elegant assertion */
1488 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1489 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1490 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1492 ERROR("arm11->reg_values inconsistent (%d %d %d %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1496 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1498 reg_t * r = reg_list + i;
1499 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1500 arm11_reg_state_t * rs = arm11_reg_states + i;
1504 r->value = (u8 *)(arm11->reg_values + i);
1507 r->bitfield_desc = NULL;
1508 r->num_bitfields = 0;
1509 r->arch_type = arm11_regs_arch_type;
1513 rs->target = target;
1519 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, int * var, char * name)
1523 INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1528 return ERROR_COMMAND_SYNTAX_ERROR;
1533 case 'f': /* false */
1535 case 'd': /* disable */
1541 case 't': /* true */
1543 case 'e': /* enable */
1549 INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1555 #define BOOL_WRAPPER(name, print_name) \
1556 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1558 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1561 #define RC_TOP(name, descr, more) \
1563 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1564 command_t * top_cmd = new_cmd; \
1568 #define RC_FINAL(name, descr, handler) \
1569 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1571 #define RC_FINAL_BOOL(name, descr, var) \
1572 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1575 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1576 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1579 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1583 arm11_vcr = strtoul(args[0], NULL, 0);
1587 return ERROR_COMMAND_SYNTAX_ERROR;
1590 INFO("VCR 0x%08X", arm11_vcr);
1595 int arm11_register_commands(struct command_context_s *cmd_ctx)
1599 command_t * top_cmd = NULL;
1601 RC_TOP( "arm11", "arm11 specific commands",
1603 RC_TOP( "memwrite", "Control memory write transfer mode",
1605 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1608 RC_FINAL_BOOL( "error_fatal",
1609 "Terminate program if transfer error was found (default: enabled)",
1610 memwrite_error_fatal)
1613 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",