1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
7 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
30 #include "target_type.h"
34 #define _DEBUG_INSTRUCTION_EXECUTION_
38 #define FNC_INFO LOG_DEBUG("-")
44 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
46 #define FNC_INFO_NOTIMPLEMENTED
49 static int arm11_on_enter_debug_state(arm11_common_t * arm11);
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
53 uint32_t arm11_vcr = 0;
54 bool arm11_config_memrw_no_increment = false;
55 bool arm11_config_step_irq_enable = false;
57 #define ARM11_HANDLER(x) \
60 target_type_t arm11_target =
65 ARM11_HANDLER(arch_state),
67 ARM11_HANDLER(target_request_data),
70 ARM11_HANDLER(resume),
73 ARM11_HANDLER(assert_reset),
74 ARM11_HANDLER(deassert_reset),
75 ARM11_HANDLER(soft_reset_halt),
77 ARM11_HANDLER(get_gdb_reg_list),
79 ARM11_HANDLER(read_memory),
80 ARM11_HANDLER(write_memory),
82 ARM11_HANDLER(bulk_write_memory),
84 ARM11_HANDLER(checksum_memory),
86 ARM11_HANDLER(add_breakpoint),
87 ARM11_HANDLER(remove_breakpoint),
88 ARM11_HANDLER(add_watchpoint),
89 ARM11_HANDLER(remove_watchpoint),
91 ARM11_HANDLER(run_algorithm),
93 ARM11_HANDLER(register_commands),
94 ARM11_HANDLER(target_create),
95 ARM11_HANDLER(init_target),
96 ARM11_HANDLER(examine),
100 int arm11_regs_arch_type = -1;
118 ARM11_REGISTER_SPSR_FIQ,
119 ARM11_REGISTER_SPSR_SVC,
120 ARM11_REGISTER_SPSR_ABT,
121 ARM11_REGISTER_SPSR_IRQ,
122 ARM11_REGISTER_SPSR_UND,
123 ARM11_REGISTER_SPSR_MON,
132 typedef struct arm11_reg_defs_s
137 enum arm11_regtype type;
140 /* update arm11_regcache_ids when changing this */
141 static const arm11_reg_defs_t arm11_reg_defs[] =
143 {"r0", 0, 0, ARM11_REGISTER_CORE},
144 {"r1", 1, 1, ARM11_REGISTER_CORE},
145 {"r2", 2, 2, ARM11_REGISTER_CORE},
146 {"r3", 3, 3, ARM11_REGISTER_CORE},
147 {"r4", 4, 4, ARM11_REGISTER_CORE},
148 {"r5", 5, 5, ARM11_REGISTER_CORE},
149 {"r6", 6, 6, ARM11_REGISTER_CORE},
150 {"r7", 7, 7, ARM11_REGISTER_CORE},
151 {"r8", 8, 8, ARM11_REGISTER_CORE},
152 {"r9", 9, 9, ARM11_REGISTER_CORE},
153 {"r10", 10, 10, ARM11_REGISTER_CORE},
154 {"r11", 11, 11, ARM11_REGISTER_CORE},
155 {"r12", 12, 12, ARM11_REGISTER_CORE},
156 {"sp", 13, 13, ARM11_REGISTER_CORE},
157 {"lr", 14, 14, ARM11_REGISTER_CORE},
158 {"pc", 15, 15, ARM11_REGISTER_CORE},
160 #if ARM11_REGCACHE_FREGS
161 {"f0", 0, 16, ARM11_REGISTER_FX},
162 {"f1", 1, 17, ARM11_REGISTER_FX},
163 {"f2", 2, 18, ARM11_REGISTER_FX},
164 {"f3", 3, 19, ARM11_REGISTER_FX},
165 {"f4", 4, 20, ARM11_REGISTER_FX},
166 {"f5", 5, 21, ARM11_REGISTER_FX},
167 {"f6", 6, 22, ARM11_REGISTER_FX},
168 {"f7", 7, 23, ARM11_REGISTER_FX},
169 {"fps", 0, 24, ARM11_REGISTER_FPS},
172 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
174 #if ARM11_REGCACHE_MODEREGS
175 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
176 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
177 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
178 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
179 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
180 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
181 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
182 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
184 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
185 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
186 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
188 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
189 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
190 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
192 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
193 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
194 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
196 {"r13_und", 13, -1, ARM11_REGISTER_UND},
197 {"r14_und", 14, -1, ARM11_REGISTER_UND},
198 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
201 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
202 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
203 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
206 /* Debug Registers */
207 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
208 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
209 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
212 enum arm11_regcache_ids
215 ARM11_RC_RX = ARM11_RC_R0,
230 ARM11_RC_SP = ARM11_RC_R13,
232 ARM11_RC_LR = ARM11_RC_R14,
234 ARM11_RC_PC = ARM11_RC_R15,
236 #if ARM11_REGCACHE_FREGS
238 ARM11_RC_FX = ARM11_RC_F0,
251 #if ARM11_REGCACHE_MODEREGS
289 #define ARM11_GDB_REGISTER_COUNT 26
291 uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
293 reg_t arm11_gdb_dummy_fp_reg =
295 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
298 uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
300 reg_t arm11_gdb_dummy_fps_reg =
302 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
307 /** Check and if necessary take control of the system
309 * \param arm11 Target state variable.
310 * \param dscr If the current DSCR content is
311 * available a pointer to a word holding the
312 * DSCR can be passed. Otherwise use NULL.
314 int arm11_check_init(arm11_common_t * arm11, uint32_t * dscr)
318 uint32_t dscr_local_tmp_copy;
322 dscr = &dscr_local_tmp_copy;
324 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
327 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
329 LOG_DEBUG("Bringing target into debug mode");
331 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
332 arm11_write_DSCR(arm11, *dscr);
334 /* add further reset initialization here */
336 arm11->simulate_reset_on_next_halt = true;
338 if (*dscr & ARM11_DSCR_CORE_HALTED)
340 /** \todo TODO: this needs further scrutiny because
341 * arm11_on_enter_debug_state() never gets properly called.
342 * As a result we don't read the actual register states from
346 arm11->target->state = TARGET_HALTED;
347 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
351 arm11->target->state = TARGET_RUNNING;
352 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
355 arm11_sc7_clear_vbw(arm11);
364 (arm11->reg_values[ARM11_RC_##x])
366 /** Save processor state.
368 * This is called when the HALT instruction has succeeded
369 * or on other occasions that stop the processor.
372 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
376 for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
378 arm11->reg_list[i].valid = 1;
379 arm11->reg_list[i].dirty = 0;
383 CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
387 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
389 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
391 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
393 scan_field_t chain5_fields[3];
395 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
396 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
397 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
399 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
403 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
407 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
408 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
409 ARM1136 seems to require this to issue ITR's as well */
411 uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
413 /* this executes JTAG queue: */
415 arm11_write_DSCR(arm11, new_dscr);
419 Before executing any instruction in debug state you have to drain the write buffer.
420 This ensures that no imprecise Data Aborts can return at a later point:*/
422 /** \todo TODO: Test drain write buffer. */
427 /* MRC p14,0,R0,c5,c10,0 */
428 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
430 /* mcr 15, 0, r0, cr7, cr10, {4} */
431 arm11_run_instr_no_data1(arm11, 0xee070f9a);
433 uint32_t dscr = arm11_read_DSCR(arm11);
435 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
437 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
439 arm11_run_instr_no_data1(arm11, 0xe320f000);
441 dscr = arm11_read_DSCR(arm11);
443 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
450 arm11_run_instr_data_prepare(arm11);
454 /** \todo TODO: handle other mode registers */
456 for (size_t i = 0; i < 15; i++)
458 /* MCR p14,0,R?,c0,c5,0 */
459 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
464 /* check rDTRfull in DSCR */
466 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
468 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
469 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
473 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
478 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
483 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
486 /* adjust PC depending on ARM state */
488 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
490 arm11->reg_values[ARM11_RC_PC] -= 0;
492 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
494 arm11->reg_values[ARM11_RC_PC] -= 4;
498 arm11->reg_values[ARM11_RC_PC] -= 8;
501 if (arm11->simulate_reset_on_next_halt)
503 arm11->simulate_reset_on_next_halt = false;
505 LOG_DEBUG("Reset c1 Control Register");
507 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
509 /* MCR p15,0,R0,c1,c0,0 */
510 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
514 arm11_run_instr_data_finish(arm11);
516 arm11_dump_reg_changes(arm11);
521 void arm11_dump_reg_changes(arm11_common_t * arm11)
524 if (!(debug_level >= LOG_LVL_DEBUG))
529 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
531 if (!arm11->reg_list[i].valid)
533 if (arm11->reg_history[i].valid)
534 LOG_DEBUG("%8s INVALID (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
538 if (arm11->reg_history[i].valid)
540 if (arm11->reg_history[i].value != arm11->reg_values[i])
541 LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
545 LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
551 /** Restore processor state
553 * This is called in preparation for the RESTART function.
556 int arm11_leave_debug_state(arm11_common_t * arm11)
560 arm11_run_instr_data_prepare(arm11);
562 /** \todo TODO: handle other mode registers */
564 /* restore R1 - R14 */
566 for (size_t i = 1; i < 15; i++)
568 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
571 /* MRC p14,0,r?,c0,c5,0 */
572 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
574 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
577 arm11_run_instr_data_finish(arm11);
579 /* spec says clear wDTR and rDTR; we assume they are clear as
580 otherwise our programming would be sloppy */
584 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
586 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
588 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
592 arm11_run_instr_data_prepare(arm11);
594 /* restore original wDTR */
596 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
598 /* MCR p14,0,R0,c0,c5,0 */
599 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
605 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
610 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
614 /* MRC p14,0,r0,c0,c5,0 */
615 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
617 arm11_run_instr_data_finish(arm11);
621 arm11_write_DSCR(arm11, R(DSCR));
625 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
627 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
629 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
631 scan_field_t chain5_fields[3];
633 uint8_t Ready = 0; /* ignored */
634 uint8_t Valid = 0; /* ignored */
636 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
637 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
638 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
640 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
643 arm11_record_register_history(arm11);
648 void arm11_record_register_history(arm11_common_t * arm11)
650 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
652 arm11->reg_history[i].value = arm11->reg_values[i];
653 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
655 arm11->reg_list[i].valid = 0;
656 arm11->reg_list[i].dirty = 0;
661 /* poll current target status */
662 int arm11_poll(struct target_s *target)
666 arm11_common_t * arm11 = target->arch_info;
668 if (arm11->trst_active)
673 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
675 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
677 CHECK_RETVAL(arm11_check_init(arm11, &dscr));
679 if (dscr & ARM11_DSCR_CORE_HALTED)
681 if (target->state != TARGET_HALTED)
683 enum target_state old_state = target->state;
685 LOG_DEBUG("enter TARGET_HALTED");
686 target->state = TARGET_HALTED;
687 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
688 arm11_on_enter_debug_state(arm11);
690 target_call_event_callbacks(target,
691 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
696 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
698 LOG_DEBUG("enter TARGET_RUNNING");
699 target->state = TARGET_RUNNING;
700 target->debug_reason = DBG_REASON_NOTHALTED;
706 /* architecture specific status reply */
707 int arm11_arch_state(struct target_s *target)
709 arm11_common_t * arm11 = target->arch_info;
711 LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
712 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
719 /* target request support */
720 int arm11_target_request_data(struct target_s *target, uint32_t size, uint8_t *buffer)
722 FNC_INFO_NOTIMPLEMENTED;
727 /* target execution control */
728 int arm11_halt(struct target_s *target)
732 arm11_common_t * arm11 = target->arch_info;
734 LOG_DEBUG("target->state: %s",
735 target_state_name(target));
737 if (target->state == TARGET_UNKNOWN)
739 arm11->simulate_reset_on_next_halt = true;
742 if (target->state == TARGET_HALTED)
744 LOG_DEBUG("target was already halted");
748 if (arm11->trst_active)
750 arm11->halt_requested = true;
754 arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
756 CHECK_RETVAL(jtag_execute_queue());
762 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
764 if (dscr & ARM11_DSCR_CORE_HALTED)
768 arm11_on_enter_debug_state(arm11);
770 enum target_state old_state = target->state;
772 target->state = TARGET_HALTED;
773 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
776 target_call_event_callbacks(target,
777 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
782 int arm11_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
786 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
787 // current, address, handle_breakpoints, debug_execution);
789 arm11_common_t * arm11 = target->arch_info;
791 LOG_DEBUG("target->state: %s",
792 target_state_name(target));
795 if (target->state != TARGET_HALTED)
797 LOG_ERROR("Target not halted");
798 return ERROR_TARGET_NOT_HALTED;
804 LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
806 /* clear breakpoints/watchpoints and VCR*/
807 arm11_sc7_clear_vbw(arm11);
809 /* Set up breakpoints */
810 if (!debug_execution)
812 /* check if one matches PC and step over it if necessary */
816 for (bp = target->breakpoints; bp; bp = bp->next)
818 if (bp->address == R(PC))
820 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
821 arm11_step(target, 1, 0, 0);
826 /* set all breakpoints */
830 for (bp = target->breakpoints; bp; bp = bp->next)
832 arm11_sc7_action_t brp[2];
835 brp[0].address = ARM11_SC7_BVR0 + brp_num;
836 brp[0].value = bp->address;
838 brp[1].address = ARM11_SC7_BCR0 + brp_num;
839 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
841 arm11_sc7_run(arm11, brp, asizeof(brp));
843 LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
848 arm11_sc7_set_vcr(arm11, arm11_vcr);
851 arm11_leave_debug_state(arm11);
853 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
855 CHECK_RETVAL(jtag_execute_queue());
861 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
863 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
865 if (dscr & ARM11_DSCR_CORE_RESTARTED)
869 if (!debug_execution)
871 target->state = TARGET_RUNNING;
872 target->debug_reason = DBG_REASON_NOTHALTED;
874 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
878 target->state = TARGET_DEBUG_RUNNING;
879 target->debug_reason = DBG_REASON_NOTHALTED;
881 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
887 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
891 LOG_DEBUG("target->state: %s",
892 target_state_name(target));
894 if (target->state != TARGET_HALTED)
896 LOG_WARNING("target was not halted");
897 return ERROR_TARGET_NOT_HALTED;
900 arm11_common_t * arm11 = target->arch_info;
905 LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
907 /** \todo TODO: Thumb not supported here */
909 uint32_t next_instruction;
911 CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
914 if ((next_instruction & 0xFFF00070) == 0xe1200070)
917 arm11->reg_list[ARM11_RC_PC].valid = 1;
918 arm11->reg_list[ARM11_RC_PC].dirty = 0;
919 LOG_DEBUG("Skipping BKPT");
921 /* skip over Wait for interrupt / Standby */
922 /* mcr 15, 0, r?, cr7, cr0, {4} */
923 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
926 arm11->reg_list[ARM11_RC_PC].valid = 1;
927 arm11->reg_list[ARM11_RC_PC].dirty = 0;
928 LOG_DEBUG("Skipping WFI");
930 /* ignore B to self */
931 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
933 LOG_DEBUG("Not stepping jump to self");
937 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
940 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
941 * the VCR might be something worth looking into. */
944 /* Set up breakpoint for stepping */
946 arm11_sc7_action_t brp[2];
949 brp[0].address = ARM11_SC7_BVR0;
950 brp[0].value = R(PC);
952 brp[1].address = ARM11_SC7_BCR0;
953 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
955 CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
960 if (arm11_config_step_irq_enable)
961 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
963 R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
966 CHECK_RETVAL(arm11_leave_debug_state(arm11));
968 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
970 CHECK_RETVAL(jtag_execute_queue());
972 /** \todo TODO: add a timeout */
980 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
982 LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
984 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
985 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
989 /* clear breakpoint */
990 arm11_sc7_clear_vbw(arm11);
993 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
995 /* restore default state */
996 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
1000 // target->state = TARGET_HALTED;
1001 target->debug_reason = DBG_REASON_SINGLESTEP;
1003 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
1008 /* target reset control */
1009 int arm11_assert_reset(struct target_s *target)
1014 /* assert reset lines */
1015 /* resets only the DBGTAP, not the ARM */
1017 jtag_add_reset(1, 0);
1018 jtag_add_sleep(5000);
1020 arm11_common_t * arm11 = target->arch_info;
1021 arm11->trst_active = true;
1024 if (target->reset_halt)
1026 CHECK_RETVAL(target_halt(target));
1032 int arm11_deassert_reset(struct target_s *target)
1037 LOG_DEBUG("target->state: %s",
1038 target_state_name(target));
1041 /* deassert reset lines */
1042 jtag_add_reset(0, 0);
1044 arm11_common_t * arm11 = target->arch_info;
1045 arm11->trst_active = false;
1047 if (arm11->halt_requested)
1048 return arm11_halt(target);
1054 int arm11_soft_reset_halt(struct target_s *target)
1056 FNC_INFO_NOTIMPLEMENTED;
1061 /* target register access for gdb */
1062 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1066 arm11_common_t * arm11 = target->arch_info;
1068 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1069 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1071 for (size_t i = 16; i < 24; i++)
1073 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1076 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1078 for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
1080 if (arm11_reg_defs[i].gdb_num == -1)
1083 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1089 /* target memory access
1090 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1091 * count: number of items of <size>
1093 int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1095 /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
1099 if (target->state != TARGET_HALTED)
1101 LOG_WARNING("target was not halted");
1102 return ERROR_TARGET_NOT_HALTED;
1105 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1107 arm11_common_t * arm11 = target->arch_info;
1109 arm11_run_instr_data_prepare(arm11);
1111 /* MRC p14,0,r0,c0,c5,0 */
1112 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1117 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1118 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1120 for (size_t i = 0; i < count; i++)
1122 /* ldrb r1, [r0], #1 */
1124 arm11_run_instr_no_data1(arm11,
1125 !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
1128 /* MCR p14,0,R1,c0,c5,0 */
1129 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1138 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1140 for (size_t i = 0; i < count; i++)
1142 /* ldrh r1, [r0], #2 */
1143 arm11_run_instr_no_data1(arm11,
1144 !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
1148 /* MCR p14,0,R1,c0,c5,0 */
1149 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1151 uint16_t svalue = res;
1152 memcpy(buffer + count * sizeof(uint16_t), &svalue, sizeof(uint16_t));
1160 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
1161 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1162 uint32_t *words = (uint32_t *)buffer;
1164 /* LDC p14,c5,[R0],#4 */
1165 /* LDC p14,c5,[R0] */
1166 arm11_run_instr_data_from_core(arm11, instr, words, count);
1171 arm11_run_instr_data_finish(arm11);
1176 int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
1180 if (target->state != TARGET_HALTED)
1182 LOG_WARNING("target was not halted");
1183 return ERROR_TARGET_NOT_HALTED;
1186 LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "", address, size, count);
1188 arm11_common_t * arm11 = target->arch_info;
1190 arm11_run_instr_data_prepare(arm11);
1192 /* MRC p14,0,r0,c0,c5,0 */
1193 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1199 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1201 for (size_t i = 0; i < count; i++)
1203 /* MRC p14,0,r1,c0,c5,0 */
1204 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1206 /* strb r1, [r0], #1 */
1208 arm11_run_instr_no_data1(arm11,
1209 !arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
1217 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1219 for (size_t i = 0; i < count; i++)
1222 memcpy(&value, buffer + count * sizeof(uint16_t), sizeof(uint16_t));
1224 /* MRC p14,0,r1,c0,c5,0 */
1225 arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1227 /* strh r1, [r0], #2 */
1229 arm11_run_instr_no_data1(arm11,
1230 !arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
1237 uint32_t instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
1239 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1240 uint32_t *words = (uint32_t*)buffer;
1242 if (!arm11_config_memwrite_burst)
1244 /* STC p14,c5,[R0],#4 */
1245 /* STC p14,c5,[R0]*/
1246 arm11_run_instr_data_to_core(arm11, instr, words, count);
1250 /* STC p14,c5,[R0],#4 */
1251 /* STC p14,c5,[R0]*/
1252 arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1260 /* r0 verification */
1261 if (!arm11_config_memrw_no_increment)
1265 /* MCR p14,0,R0,c0,c5,0 */
1266 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1268 if (address + size * count != r0)
1270 LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
1272 if (arm11_config_memwrite_burst)
1273 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1275 if (arm11_config_memwrite_error_fatal)
1281 arm11_run_instr_data_finish(arm11);
1287 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1288 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
1292 if (target->state != TARGET_HALTED)
1294 LOG_WARNING("target was not halted");
1295 return ERROR_TARGET_NOT_HALTED;
1298 return arm11_write_memory(target, address, 4, count, buffer);
1301 /* here we have nothing target specific to contribute, so we fail and then the
1302 * fallback code will read data from the target and calculate the CRC on the
1305 int arm11_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
1310 /* target break-/watchpoint control
1311 * rw: 0 = write, 1 = read, 2 = access
1313 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1317 arm11_common_t * arm11 = target->arch_info;
1320 if (breakpoint->type == BKPT_SOFT)
1322 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1323 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1327 if (!arm11->free_brps)
1329 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1330 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1333 if (breakpoint->length != 4)
1335 LOG_DEBUG("only breakpoints of four bytes length supported");
1336 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1344 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1348 arm11_common_t * arm11 = target->arch_info;
1355 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1357 FNC_INFO_NOTIMPLEMENTED;
1362 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1364 FNC_INFO_NOTIMPLEMENTED;
1369 // HACKHACKHACK - FIXME mode/state
1370 /* target algorithm support */
1371 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1372 int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point,
1373 int timeout_ms, void *arch_info)
1375 arm11_common_t *arm11 = target->arch_info;
1376 // enum armv4_5_state core_state = arm11->core_state;
1377 // enum armv4_5_mode core_mode = arm11->core_mode;
1378 uint32_t context[16];
1380 int exit_breakpoint_size = 0;
1381 int retval = ERROR_OK;
1382 LOG_DEBUG("Running algorithm");
1385 if (target->state != TARGET_HALTED)
1387 LOG_WARNING("target not halted");
1388 return ERROR_TARGET_NOT_HALTED;
1392 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1393 // return ERROR_FAIL;
1396 for (size_t i = 0; i < 16; i++)
1398 context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
1399 LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
1402 cpsr = buf_get_u32((uint8_t*)(arm11->reg_values + ARM11_RC_CPSR),0,32);
1403 LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
1405 for (int i = 0; i < num_mem_params; i++)
1407 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1410 // Set register parameters
1411 for (int i = 0; i < num_reg_params; i++)
1413 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1416 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1420 if (reg->size != reg_params[i].size)
1422 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1425 arm11_set_reg(reg,reg_params[i].value);
1426 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1429 exit_breakpoint_size = 4;
1431 /* arm11->core_state = arm11_algorithm_info->core_state;
1432 if (arm11->core_state == ARMV4_5_STATE_ARM)
1433 exit_breakpoint_size = 4;
1434 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1435 exit_breakpoint_size = 2;
1438 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1444 /* arm11 at this point only supports ARM not THUMB mode
1445 however if this test needs to be reactivated the current state can be read back
1448 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1450 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1451 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1452 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1453 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1457 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1459 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1460 retval = ERROR_TARGET_FAILURE;
1464 // no debug, otherwise breakpoint is not set
1465 CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
1467 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
1469 if (target->state != TARGET_HALTED)
1471 CHECK_RETVAL(target_halt(target));
1473 CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
1475 retval = ERROR_TARGET_TIMEOUT;
1477 goto del_breakpoint;
1480 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1482 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1483 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1484 retval = ERROR_TARGET_TIMEOUT;
1485 goto del_breakpoint;
1488 for (int i = 0; i < num_mem_params; i++)
1490 if (mem_params[i].direction != PARAM_OUT)
1491 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1494 for (int i = 0; i < num_reg_params; i++)
1496 if (reg_params[i].direction != PARAM_OUT)
1498 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1501 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1505 if (reg->size != reg_params[i].size)
1507 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1511 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1516 breakpoint_remove(target, exit_point);
1520 for (size_t i = 0; i < 16; i++)
1522 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1523 arm11->reg_list[i].name, context[i]);
1524 arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
1526 LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
1527 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
1529 // arm11->core_state = core_state;
1530 // arm11->core_mode = core_mode;
1535 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1539 NEW(arm11_common_t, arm11, 1);
1541 arm11->target = target;
1543 if (target->tap == NULL)
1546 if (target->tap->ir_length != 5)
1548 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1549 return ERROR_COMMAND_SYNTAX_ERROR;
1552 target->arch_info = arm11;
1557 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1559 /* Initialize anything we can set up without talking to the target */
1560 return arm11_build_reg_cache(target);
1563 /* talk to the target and set things up */
1564 int arm11_examine(struct target_s *target)
1568 arm11_common_t * arm11 = target->arch_info;
1572 arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1574 scan_field_t idcode_field;
1576 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1578 arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1582 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1584 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1586 scan_field_t chain0_fields[2];
1588 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1589 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1591 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
1593 CHECK_RETVAL(jtag_execute_queue());
1595 switch (arm11->device_id & 0x0FFFF000)
1597 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1598 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1599 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1602 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1607 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1609 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1610 arm11->debug_version != ARM11_DEBUG_V61)
1612 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1616 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1617 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1619 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1620 arm11->free_brps = arm11->brp;
1621 arm11->free_wrps = arm11->wrp;
1623 LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
1625 (int)(arm11->implementor),
1628 /* as a side-effect this reads DSCR and thus
1629 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1630 * as suggested by the spec.
1633 arm11_check_init(arm11, NULL);
1635 target_set_examined(target);
1640 int arm11_quit(void)
1642 FNC_INFO_NOTIMPLEMENTED;
1647 /** Load a register that is marked !valid in the register cache */
1648 int arm11_get_reg(reg_t *reg)
1652 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1654 if (target->state != TARGET_HALTED)
1656 LOG_WARNING("target was not halted");
1657 return ERROR_TARGET_NOT_HALTED;
1660 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1663 arm11_common_t *arm11 = target->arch_info;
1664 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1670 /** Change a value in the register cache */
1671 int arm11_set_reg(reg_t *reg, uint8_t *buf)
1675 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1676 arm11_common_t *arm11 = target->arch_info;
1677 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1679 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1686 int arm11_build_reg_cache(target_t *target)
1688 arm11_common_t *arm11 = target->arch_info;
1690 NEW(reg_cache_t, cache, 1);
1691 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1692 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1694 if (arm11_regs_arch_type == -1)
1695 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1697 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1698 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1700 arm11->reg_list = reg_list;
1702 /* Build the process context cache */
1703 cache->name = "arm11 registers";
1705 cache->reg_list = reg_list;
1706 cache->num_regs = ARM11_REGCACHE_COUNT;
1708 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1711 arm11->core_cache = cache;
1712 // armv7m->process_context = cache;
1716 /* Not very elegant assertion */
1717 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1718 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1719 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1721 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1725 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1727 reg_t * r = reg_list + i;
1728 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1729 arm11_reg_state_t * rs = arm11_reg_states + i;
1733 r->value = (uint8_t *)(arm11->reg_values + i);
1736 r->bitfield_desc = NULL;
1737 r->num_bitfields = 0;
1738 r->arch_type = arm11_regs_arch_type;
1742 rs->target = target;
1748 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1752 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1757 return ERROR_COMMAND_SYNTAX_ERROR;
1762 case 'f': /* false */
1764 case 'd': /* disable */
1770 case 't': /* true */
1772 case 'e': /* enable */
1778 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1783 #define BOOL_WRAPPER(name, print_name) \
1784 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1786 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1789 #define RC_TOP(name, descr, more) \
1791 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1792 command_t * top_cmd = new_cmd; \
1796 #define RC_FINAL(name, descr, handler) \
1797 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1799 #define RC_FINAL_BOOL(name, descr, var) \
1800 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1802 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1803 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1804 BOOL_WRAPPER(memrw_no_increment, "\"no increment\" mode for memory transfers")
1805 BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1807 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1811 arm11_vcr = strtoul(args[0], NULL, 0);
1815 return ERROR_COMMAND_SYNTAX_ERROR;
1818 LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1822 const uint32_t arm11_coproc_instruction_limits[] =
1824 15, /* coprocessor */
1829 0xFFFFFFFF, /* value */
1832 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1833 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1835 arm11_common_t * arm11_find_target(const char * arg)
1840 tap = jtag_tap_by_string(arg);
1845 for (t = all_targets; t; t = t->next)
1850 /* if (t->type == arm11_target) */
1851 if (0 == strcmp(target_get_name(t), "arm11"))
1852 return t->arch_info;
1858 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1860 if (argc != (read ? 6 : 7))
1862 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1866 arm11_common_t * arm11 = arm11_find_target(args[0]);
1870 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1871 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1876 if (arm11->target->state != TARGET_HALTED)
1878 LOG_WARNING("target was not halted");
1879 return ERROR_TARGET_NOT_HALTED;
1884 for (size_t i = 0; i < (read ? 5 : 6); i++)
1886 values[i] = strtoul(args[i + 1], NULL, 0);
1888 if (values[i] > arm11_coproc_instruction_limits[i])
1890 LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
1892 arm11_coproc_instruction_limits[i],
1893 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1898 uint32_t instr = 0xEE000010 |
1906 instr |= 0x00100000;
1908 arm11_run_instr_data_prepare(arm11);
1913 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1915 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
1920 (int)(values[4]), result, result);
1924 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1926 LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
1927 (int)(values[0]), (int)(values[1]),
1929 (int)(values[2]), (int)(values[3]), (int)(values[4]));
1932 arm11_run_instr_data_finish(arm11);
1938 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1940 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1943 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1945 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1948 int arm11_register_commands(struct command_context_s *cmd_ctx)
1952 command_t * top_cmd = NULL;
1954 RC_TOP("arm11", "arm11 specific commands",
1956 RC_TOP("memwrite", "Control memory write transfer mode",
1958 RC_FINAL_BOOL("burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1961 RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
1962 memwrite_error_fatal)
1965 RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
1968 RC_FINAL_BOOL("step_irq_enable", "Enable interrupts while stepping (default: disabled)",
1971 RC_FINAL("vcr", "Control (Interrupt) Vector Catch Register",
1974 RC_FINAL("mrc", "Read Coprocessor register",
1977 RC_FINAL("mcr", "Write Coprocessor register",