1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #define FNC_INFO LOG_DEBUG("-")
43 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
45 #define FNC_INFO_NOTIMPLEMENTED
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
56 #define ARM11_HANDLER(x) \
59 target_type_t arm11_target =
64 ARM11_HANDLER(arch_state),
66 ARM11_HANDLER(target_request_data),
69 ARM11_HANDLER(resume),
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
76 ARM11_HANDLER(get_gdb_reg_list),
78 ARM11_HANDLER(read_memory),
79 ARM11_HANDLER(write_memory),
81 ARM11_HANDLER(bulk_write_memory),
83 ARM11_HANDLER(checksum_memory),
85 ARM11_HANDLER(add_breakpoint),
86 ARM11_HANDLER(remove_breakpoint),
87 ARM11_HANDLER(add_watchpoint),
88 ARM11_HANDLER(remove_watchpoint),
90 ARM11_HANDLER(run_algorithm),
92 ARM11_HANDLER(register_commands),
93 ARM11_HANDLER(target_command),
94 ARM11_HANDLER(init_target),
95 ARM11_HANDLER(examine),
99 int arm11_regs_arch_type = -1;
117 ARM11_REGISTER_SPSR_FIQ,
118 ARM11_REGISTER_SPSR_SVC,
119 ARM11_REGISTER_SPSR_ABT,
120 ARM11_REGISTER_SPSR_IRQ,
121 ARM11_REGISTER_SPSR_UND,
122 ARM11_REGISTER_SPSR_MON,
131 typedef struct arm11_reg_defs_s
136 enum arm11_regtype type;
139 /* update arm11_regcache_ids when changing this */
140 static const arm11_reg_defs_t arm11_reg_defs[] =
142 {"r0", 0, 0, ARM11_REGISTER_CORE},
143 {"r1", 1, 1, ARM11_REGISTER_CORE},
144 {"r2", 2, 2, ARM11_REGISTER_CORE},
145 {"r3", 3, 3, ARM11_REGISTER_CORE},
146 {"r4", 4, 4, ARM11_REGISTER_CORE},
147 {"r5", 5, 5, ARM11_REGISTER_CORE},
148 {"r6", 6, 6, ARM11_REGISTER_CORE},
149 {"r7", 7, 7, ARM11_REGISTER_CORE},
150 {"r8", 8, 8, ARM11_REGISTER_CORE},
151 {"r9", 9, 9, ARM11_REGISTER_CORE},
152 {"r10", 10, 10, ARM11_REGISTER_CORE},
153 {"r11", 11, 11, ARM11_REGISTER_CORE},
154 {"r12", 12, 12, ARM11_REGISTER_CORE},
155 {"sp", 13, 13, ARM11_REGISTER_CORE},
156 {"lr", 14, 14, ARM11_REGISTER_CORE},
157 {"pc", 15, 15, ARM11_REGISTER_CORE},
159 #if ARM11_REGCACHE_FREGS
160 {"f0", 0, 16, ARM11_REGISTER_FX},
161 {"f1", 1, 17, ARM11_REGISTER_FX},
162 {"f2", 2, 18, ARM11_REGISTER_FX},
163 {"f3", 3, 19, ARM11_REGISTER_FX},
164 {"f4", 4, 20, ARM11_REGISTER_FX},
165 {"f5", 5, 21, ARM11_REGISTER_FX},
166 {"f6", 6, 22, ARM11_REGISTER_FX},
167 {"f7", 7, 23, ARM11_REGISTER_FX},
168 {"fps", 0, 24, ARM11_REGISTER_FPS},
171 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
173 #if ARM11_REGCACHE_MODEREGS
174 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
175 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
176 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
177 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
178 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
179 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
180 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
181 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
183 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
184 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
185 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
187 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
188 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
189 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
191 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
192 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
193 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
195 {"r13_und", 13, -1, ARM11_REGISTER_UND},
196 {"r14_und", 14, -1, ARM11_REGISTER_UND},
197 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
200 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
201 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
202 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
205 /* Debug Registers */
206 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
207 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
208 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
211 enum arm11_regcache_ids
214 ARM11_RC_RX = ARM11_RC_R0,
229 ARM11_RC_SP = ARM11_RC_R13,
231 ARM11_RC_LR = ARM11_RC_R14,
233 ARM11_RC_PC = ARM11_RC_R15,
235 #if ARM11_REGCACHE_FREGS
237 ARM11_RC_FX = ARM11_RC_F0,
250 #if ARM11_REGCACHE_MODEREGS
288 #define ARM11_GDB_REGISTER_COUNT 26
290 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
292 reg_t arm11_gdb_dummy_fp_reg =
294 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
297 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
299 reg_t arm11_gdb_dummy_fps_reg =
301 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
306 /** Check and if necessary take control of the system
308 * \param arm11 Target state variable.
309 * \param dscr If the current DSCR content is
310 * available a pointer to a word holding the
311 * DSCR can be passed. Otherwise use NULL.
313 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
317 u32 dscr_local_tmp_copy;
321 dscr = &dscr_local_tmp_copy;
322 *dscr = arm11_read_DSCR(arm11);
325 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
327 LOG_DEBUG("Bringing target into debug mode");
329 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
330 arm11_write_DSCR(arm11, *dscr);
332 /* add further reset initialization here */
334 arm11->simulate_reset_on_next_halt = true;
336 if (*dscr & ARM11_DSCR_CORE_HALTED)
338 /** \todo TODO: this needs further scrutiny because
339 * arm11_on_enter_debug_state() never gets properly called
342 arm11->target->state = TARGET_HALTED;
343 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
347 arm11->target->state = TARGET_RUNNING;
348 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
351 arm11_sc7_clear_vbw(arm11);
358 (arm11->reg_values[ARM11_RC_##x])
360 /** Save processor state.
362 * This is called when the HALT instruction has succeeded
363 * or on other occasions that stop the processor.
366 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
371 for(i = 0; i < asizeof(arm11->reg_values); i++)
373 arm11->reg_list[i].valid = 1;
374 arm11->reg_list[i].dirty = 0;
379 R(DSCR) = arm11_read_DSCR(arm11);
383 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
385 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
387 arm11_add_IR(arm11, ARM11_INTEST, -1);
389 scan_field_t chain5_fields[3];
391 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
392 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
393 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
395 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
399 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
403 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
404 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
405 ARM1136 seems to require this to issue ITR's as well */
407 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
409 /* this executes JTAG queue: */
411 arm11_write_DSCR(arm11, new_dscr);
415 Before executing any instruction in debug state you have to drain the write buffer.
416 This ensures that no imprecise Data Aborts can return at a later point:*/
418 /** \todo TODO: Test drain write buffer. */
423 /* MRC p14,0,R0,c5,c10,0 */
424 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
426 /* mcr 15, 0, r0, cr7, cr10, {4} */
427 arm11_run_instr_no_data1(arm11, 0xee070f9a);
429 u32 dscr = arm11_read_DSCR(arm11);
431 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
433 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
435 arm11_run_instr_no_data1(arm11, 0xe320f000);
437 dscr = arm11_read_DSCR(arm11);
439 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
447 arm11_run_instr_data_prepare(arm11);
452 /** \todo TODO: handle other mode registers */
455 for (i = 0; i < 15; i++)
457 /* MCR p14,0,R?,c0,c5,0 */
458 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
464 /* check rDTRfull in DSCR */
466 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
468 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
469 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
473 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
478 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
479 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
483 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
484 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
486 /* adjust PC depending on ARM state */
488 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
490 arm11->reg_values[ARM11_RC_PC] -= 0;
492 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
494 arm11->reg_values[ARM11_RC_PC] -= 4;
498 arm11->reg_values[ARM11_RC_PC] -= 8;
501 if (arm11->simulate_reset_on_next_halt)
503 arm11->simulate_reset_on_next_halt = false;
505 LOG_DEBUG("Reset c1 Control Register");
507 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
509 /* MCR p15,0,R0,c1,c0,0 */
510 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
514 arm11_run_instr_data_finish(arm11);
516 arm11_dump_reg_changes(arm11);
519 void arm11_dump_reg_changes(arm11_common_t * arm11)
522 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
524 if (!arm11->reg_list[i].valid)
526 if (arm11->reg_history[i].valid)
527 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
531 if (arm11->reg_history[i].valid)
533 if (arm11->reg_history[i].value != arm11->reg_values[i])
534 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
538 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
545 /** Restore processor state
547 * This is called in preparation for the RESTART function.
550 void arm11_leave_debug_state(arm11_common_t * arm11)
554 arm11_run_instr_data_prepare(arm11);
556 /** \todo TODO: handle other mode registers */
558 /* restore R1 - R14 */
560 for (i = 1; i < 15; i++)
562 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
565 /* MRC p14,0,r?,c0,c5,0 */
566 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
568 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
571 arm11_run_instr_data_finish(arm11);
574 /* spec says clear wDTR and rDTR; we assume they are clear as
575 otherwise our programming would be sloppy */
578 u32 DSCR = arm11_read_DSCR(arm11);
580 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
582 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
586 arm11_run_instr_data_prepare(arm11);
588 /* restore original wDTR */
590 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
592 /* MCR p14,0,R0,c0,c5,0 */
593 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
599 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
605 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
610 /* MRC p14,0,r0,c0,c5,0 */
611 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
613 arm11_run_instr_data_finish(arm11);
618 arm11_write_DSCR(arm11, R(DSCR));
623 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
625 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
627 arm11_add_IR(arm11, ARM11_EXTEST, -1);
629 scan_field_t chain5_fields[3];
631 u8 Ready = 0; /* ignored */
632 u8 Valid = 0; /* ignored */
634 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
635 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
636 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
638 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
641 arm11_record_register_history(arm11);
644 void arm11_record_register_history(arm11_common_t * arm11)
647 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
649 arm11->reg_history[i].value = arm11->reg_values[i];
650 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
652 arm11->reg_list[i].valid = 0;
653 arm11->reg_list[i].dirty = 0;
658 /* poll current target status */
659 int arm11_poll(struct target_s *target)
663 arm11_common_t * arm11 = target->arch_info;
665 if (arm11->trst_active)
668 u32 dscr = arm11_read_DSCR(arm11);
670 LOG_DEBUG("DSCR %08x", dscr);
672 arm11_check_init(arm11, &dscr);
674 if (dscr & ARM11_DSCR_CORE_HALTED)
676 if (target->state != TARGET_HALTED)
678 enum target_state old_state = target->state;
680 LOG_DEBUG("enter TARGET_HALTED");
681 target->state = TARGET_HALTED;
682 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
683 arm11_on_enter_debug_state(arm11);
685 target_call_event_callbacks(target,
686 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
691 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
693 LOG_DEBUG("enter TARGET_RUNNING");
694 target->state = TARGET_RUNNING;
695 target->debug_reason = DBG_REASON_NOTHALTED;
701 /* architecture specific status reply */
702 int arm11_arch_state(struct target_s *target)
704 FNC_INFO_NOTIMPLEMENTED;
710 /* target request support */
711 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
713 FNC_INFO_NOTIMPLEMENTED;
720 /* target execution control */
721 int arm11_halt(struct target_s *target)
725 arm11_common_t * arm11 = target->arch_info;
727 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
729 if (target->state == TARGET_UNKNOWN)
731 arm11->simulate_reset_on_next_halt = true;
734 if (target->state == TARGET_HALTED)
736 LOG_DEBUG("target was already halted");
740 if (arm11->trst_active)
742 arm11->halt_requested = true;
746 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
748 jtag_execute_queue();
754 dscr = arm11_read_DSCR(arm11);
756 if (dscr & ARM11_DSCR_CORE_HALTED)
760 arm11_on_enter_debug_state(arm11);
762 enum target_state old_state = target->state;
764 target->state = TARGET_HALTED;
765 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
767 target_call_event_callbacks(target,
768 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
774 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
778 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
779 // current, address, handle_breakpoints, debug_execution);
781 arm11_common_t * arm11 = target->arch_info;
783 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
785 if (target->state != TARGET_HALTED)
787 LOG_WARNING("target was not halted");
788 return ERROR_TARGET_NOT_HALTED;
794 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
796 /* clear breakpoints/watchpoints and VCR*/
797 arm11_sc7_clear_vbw(arm11);
799 /* Set up breakpoints */
800 if (!debug_execution)
802 /* check if one matches PC and step over it if necessary */
806 for (bp = target->breakpoints; bp; bp = bp->next)
808 if (bp->address == R(PC))
810 LOG_DEBUG("must step over %08x", bp->address);
811 arm11_step(target, 1, 0, 0);
816 /* set all breakpoints */
820 for (bp = target->breakpoints; bp; bp = bp->next)
822 arm11_sc7_action_t brp[2];
825 brp[0].address = ARM11_SC7_BVR0 + brp_num;
826 brp[0].value = bp->address;
828 brp[1].address = ARM11_SC7_BCR0 + brp_num;
829 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
831 arm11_sc7_run(arm11, brp, asizeof(brp));
833 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
838 arm11_sc7_set_vcr(arm11, arm11_vcr);
842 arm11_leave_debug_state(arm11);
844 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
846 jtag_execute_queue();
850 u32 dscr = arm11_read_DSCR(arm11);
852 LOG_DEBUG("DSCR %08x", dscr);
854 if (dscr & ARM11_DSCR_CORE_RESTARTED)
858 if (!debug_execution)
860 target->state = TARGET_RUNNING;
861 target->debug_reason = DBG_REASON_NOTHALTED;
862 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
866 target->state = TARGET_DEBUG_RUNNING;
867 target->debug_reason = DBG_REASON_NOTHALTED;
868 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
874 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
878 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
880 if (target->state != TARGET_HALTED)
882 LOG_WARNING("target was not halted");
883 return ERROR_TARGET_NOT_HALTED;
886 arm11_common_t * arm11 = target->arch_info;
891 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
893 /** \todo TODO: Thumb not supported here */
895 u32 next_instruction;
897 arm11_read_memory_word(arm11, R(PC), &next_instruction);
900 if ((next_instruction & 0xFFF00070) == 0xe1200070)
903 arm11->reg_list[ARM11_RC_PC].valid = 1;
904 arm11->reg_list[ARM11_RC_PC].dirty = 0;
905 LOG_INFO("Skipping BKPT");
907 /* skip over Wait for interrupt / Standby */
908 /* mcr 15, 0, r?, cr7, cr0, {4} */
909 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
912 arm11->reg_list[ARM11_RC_PC].valid = 1;
913 arm11->reg_list[ARM11_RC_PC].dirty = 0;
914 LOG_INFO("Skipping WFI");
916 /* ignore B to self */
917 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
919 LOG_INFO("Not stepping jump to self");
923 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
926 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
927 * the VCR might be something worth looking into. */
930 /* Set up breakpoint for stepping */
932 arm11_sc7_action_t brp[2];
935 brp[0].address = ARM11_SC7_BVR0;
936 brp[0].value = R(PC);
938 brp[1].address = ARM11_SC7_BCR0;
939 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
941 arm11_sc7_run(arm11, brp, asizeof(brp));
945 arm11_leave_debug_state(arm11);
947 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
949 jtag_execute_queue();
951 /** \todo TODO: add a timeout */
957 u32 dscr = arm11_read_DSCR(arm11);
959 LOG_DEBUG("DSCR %08x", dscr);
961 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
962 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
966 /* clear breakpoint */
967 arm11_sc7_clear_vbw(arm11);
970 arm11_on_enter_debug_state(arm11);
973 // target->state = TARGET_HALTED;
974 target->debug_reason = DBG_REASON_SINGLESTEP;
976 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
982 /* target reset control */
983 int arm11_assert_reset(struct target_s *target)
988 /* assert reset lines */
989 /* resets only the DBGTAP, not the ARM */
991 jtag_add_reset(1, 0);
992 jtag_add_sleep(5000);
994 arm11_common_t * arm11 = target->arch_info;
995 arm11->trst_active = true;
1001 int arm11_deassert_reset(struct target_s *target)
1006 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1008 /* deassert reset lines */
1009 jtag_add_reset(0, 0);
1011 arm11_common_t * arm11 = target->arch_info;
1012 arm11->trst_active = false;
1014 if (arm11->halt_requested)
1015 return arm11_halt(target);
1021 int arm11_soft_reset_halt(struct target_s *target)
1023 FNC_INFO_NOTIMPLEMENTED;
1030 /* target register access for gdb */
1031 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1035 arm11_common_t * arm11 = target->arch_info;
1037 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1038 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1041 for (i = 16; i < 24; i++)
1043 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1046 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1050 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1052 if (arm11_reg_defs[i].gdb_num == -1)
1055 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1062 /* target memory access
1063 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1064 * count: number of items of <size>
1066 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1068 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1072 if (target->state != TARGET_HALTED)
1074 LOG_WARNING("target was not halted");
1075 return ERROR_TARGET_NOT_HALTED;
1078 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1080 arm11_common_t * arm11 = target->arch_info;
1082 arm11_run_instr_data_prepare(arm11);
1084 /* MRC p14,0,r0,c0,c5,0 */
1085 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1090 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1091 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1094 for (i = 0; i < count; i++)
1096 /* ldrb r1, [r0], #1 */
1097 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1100 /* MCR p14,0,R1,c0,c5,0 */
1101 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1110 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1112 u16 * buf16 = (u16*)buffer;
1115 for (i = 0; i < count; i++)
1117 /* ldrh r1, [r0], #2 */
1118 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1122 /* MCR p14,0,R1,c0,c5,0 */
1123 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1133 /* LDC p14,c5,[R0],#4 */
1134 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1138 arm11_run_instr_data_finish(arm11);
1143 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1147 if (target->state != TARGET_HALTED)
1149 LOG_WARNING("target was not halted");
1150 return ERROR_TARGET_NOT_HALTED;
1153 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1155 arm11_common_t * arm11 = target->arch_info;
1157 arm11_run_instr_data_prepare(arm11);
1159 /* MRC p14,0,r0,c0,c5,0 */
1160 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1166 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1169 for (i = 0; i < count; i++)
1171 /* MRC p14,0,r1,c0,c5,0 */
1172 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1174 /* strb r1, [r0], #1 */
1175 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1183 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1185 u16 * buf16 = (u16*)buffer;
1188 for (i = 0; i < count; i++)
1190 /* MRC p14,0,r1,c0,c5,0 */
1191 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1193 /* strh r1, [r0], #2 */
1194 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1201 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1203 if (!arm11_config_memwrite_burst)
1205 /* STC p14,c5,[R0],#4 */
1206 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1210 /* STC p14,c5,[R0],#4 */
1211 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1218 /* r0 verification */
1222 /* MCR p14,0,R0,c0,c5,0 */
1223 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1225 if (address + size * count != r0)
1227 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1229 if (arm11_config_memwrite_burst)
1230 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1232 if (arm11_config_memwrite_error_fatal)
1239 arm11_run_instr_data_finish(arm11);
1248 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1249 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1253 if (target->state != TARGET_HALTED)
1255 LOG_WARNING("target was not halted");
1256 return ERROR_TARGET_NOT_HALTED;
1259 return arm11_write_memory(target, address, 4, count, buffer);
1263 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1265 FNC_INFO_NOTIMPLEMENTED;
1271 /* target break-/watchpoint control
1272 * rw: 0 = write, 1 = read, 2 = access
1274 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1278 arm11_common_t * arm11 = target->arch_info;
1281 if (breakpoint->type == BKPT_SOFT)
1283 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1284 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1288 if (!arm11->free_brps)
1290 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1291 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1294 if (breakpoint->length != 4)
1296 LOG_INFO("only breakpoints of four bytes length supported");
1297 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1305 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1309 arm11_common_t * arm11 = target->arch_info;
1316 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1318 FNC_INFO_NOTIMPLEMENTED;
1323 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1325 FNC_INFO_NOTIMPLEMENTED;
1331 /* target algorithm support */
1332 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1334 FNC_INFO_NOTIMPLEMENTED;
1339 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1345 LOG_ERROR("'target arm11' 4th argument <jtag chain pos>");
1349 int chain_pos = strtoul(args[3], NULL, 0);
1351 NEW(arm11_common_t, arm11, 1);
1353 arm11->target = target;
1355 /* prepare JTAG information for the new target */
1356 arm11->jtag_info.chain_pos = chain_pos;
1357 arm11->jtag_info.scann_size = 5;
1359 arm_jtag_setup_connection(&arm11->jtag_info);
1361 jtag_device_t *device = jtag_get_device(chain_pos);
1363 if (device->ir_length != 5)
1365 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1369 target->arch_info = arm11;
1374 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1376 /* Initialize anything we can set up without talking to the target */
1380 /* talk to the target and set things up */
1381 int arm11_examine(struct command_context_s *cmd_ctx, struct target_s *target)
1385 arm11_common_t * arm11 = target->arch_info;
1389 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1391 scan_field_t idcode_field;
1393 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1395 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1399 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1401 arm11_add_IR(arm11, ARM11_INTEST, -1);
1403 scan_field_t chain0_fields[2];
1405 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1406 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1408 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1410 jtag_execute_queue();
1413 switch (arm11->device_id & 0x0FFFF000)
1415 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1416 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1417 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1420 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1425 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1427 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1428 arm11->debug_version != ARM11_DEBUG_V61)
1430 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1435 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1436 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1438 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1439 arm11->free_brps = arm11->brp;
1440 arm11->free_wrps = arm11->wrp;
1442 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1447 arm11_build_reg_cache(target);
1450 /* as a side-effect this reads DSCR and thus
1451 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1452 * as suggested by the spec.
1455 arm11_check_init(arm11, NULL);
1460 int arm11_quit(void)
1462 FNC_INFO_NOTIMPLEMENTED;
1467 /** Load a register that is marked !valid in the register cache */
1468 int arm11_get_reg(reg_t *reg)
1472 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1474 if (target->state != TARGET_HALTED)
1476 LOG_WARNING("target was not halted");
1477 return ERROR_TARGET_NOT_HALTED;
1480 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1483 arm11_common_t *arm11 = target->arch_info;
1484 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1490 /** Change a value in the register cache */
1491 int arm11_set_reg(reg_t *reg, u8 *buf)
1495 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1496 arm11_common_t *arm11 = target->arch_info;
1497 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1499 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1507 void arm11_build_reg_cache(target_t *target)
1509 arm11_common_t *arm11 = target->arch_info;
1511 NEW(reg_cache_t, cache, 1);
1512 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1513 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1515 if (arm11_regs_arch_type == -1)
1516 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1518 arm11->reg_list = reg_list;
1520 /* Build the process context cache */
1521 cache->name = "arm11 registers";
1523 cache->reg_list = reg_list;
1524 cache->num_regs = ARM11_REGCACHE_COUNT;
1526 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1529 // armv7m->core_cache = cache;
1530 // armv7m->process_context = cache;
1534 /* Not very elegant assertion */
1535 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1536 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1537 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1539 LOG_ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1543 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1545 reg_t * r = reg_list + i;
1546 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1547 arm11_reg_state_t * rs = arm11_reg_states + i;
1551 r->value = (u8 *)(arm11->reg_values + i);
1554 r->bitfield_desc = NULL;
1555 r->num_bitfields = 0;
1556 r->arch_type = arm11_regs_arch_type;
1560 rs->target = target;
1566 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1570 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1575 return ERROR_COMMAND_SYNTAX_ERROR;
1580 case 'f': /* false */
1582 case 'd': /* disable */
1588 case 't': /* true */
1590 case 'e': /* enable */
1596 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1602 #define BOOL_WRAPPER(name, print_name) \
1603 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1605 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1608 #define RC_TOP(name, descr, more) \
1610 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1611 command_t * top_cmd = new_cmd; \
1615 #define RC_FINAL(name, descr, handler) \
1616 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1618 #define RC_FINAL_BOOL(name, descr, var) \
1619 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1622 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1623 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1626 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1630 arm11_vcr = strtoul(args[0], NULL, 0);
1634 return ERROR_COMMAND_SYNTAX_ERROR;
1637 LOG_INFO("VCR 0x%08X", arm11_vcr);
1641 const u32 arm11_coproc_instruction_limits[] =
1643 15, /* coprocessor */
1648 0xFFFFFFFF, /* value */
1651 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1652 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1655 arm11_common_t * arm11_find_target(const char * arg)
1657 size_t jtag_target = strtoul(arg, NULL, 0);
1660 for (t = targets; t; t = t->next)
1662 if (t->type != &arm11_target)
1665 arm11_common_t * arm11 = t->arch_info;
1667 if (arm11->jtag_info.chain_pos != jtag_target)
1676 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1678 if (argc != (read ? 6 : 7))
1680 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1684 arm11_common_t * arm11 = arm11_find_target(args[0]);
1688 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1689 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1695 if (arm11->target->state != TARGET_HALTED)
1697 LOG_WARNING("target was not halted");
1698 return ERROR_TARGET_NOT_HALTED;
1705 for (i = 0; i < (read ? 5 : 6); i++)
1707 values[i] = strtoul(args[i + 1], NULL, 0);
1709 if (values[i] > arm11_coproc_instruction_limits[i])
1711 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1712 i + 2, arm11_coproc_instruction_limits[i],
1713 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1718 u32 instr = 0xEE000010 |
1726 instr |= 0x00100000;
1729 arm11_run_instr_data_prepare(arm11);
1734 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1736 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1737 values[0], values[1], values[2], values[3], values[4], result, result);
1741 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1743 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1744 values[0], values[1],
1746 values[2], values[3], values[4]);
1749 arm11_run_instr_data_finish(arm11);
1755 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1757 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1760 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1762 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1765 int arm11_register_commands(struct command_context_s *cmd_ctx)
1769 command_t * top_cmd = NULL;
1771 RC_TOP( "arm11", "arm11 specific commands",
1773 RC_TOP( "memwrite", "Control memory write transfer mode",
1775 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1778 RC_FINAL_BOOL( "error_fatal",
1779 "Terminate program if transfer error was found (default: enabled)",
1780 memwrite_error_fatal)
1783 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1786 RC_FINAL( "mrc", "Read Coprocessor register",
1789 RC_FINAL( "mcr", "Write Coprocessor register",