1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
37 #define FNC_INFO LOG_DEBUG("-")
43 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
45 #define FNC_INFO_NOTIMPLEMENTED
48 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
51 bool arm11_config_memwrite_burst = true;
52 bool arm11_config_memwrite_error_fatal = true;
56 #define ARM11_HANDLER(x) \
59 target_type_t arm11_target =
64 ARM11_HANDLER(arch_state),
66 ARM11_HANDLER(target_request_data),
69 ARM11_HANDLER(resume),
72 ARM11_HANDLER(assert_reset),
73 ARM11_HANDLER(deassert_reset),
74 ARM11_HANDLER(soft_reset_halt),
76 ARM11_HANDLER(get_gdb_reg_list),
78 ARM11_HANDLER(read_memory),
79 ARM11_HANDLER(write_memory),
81 ARM11_HANDLER(bulk_write_memory),
83 ARM11_HANDLER(checksum_memory),
85 ARM11_HANDLER(add_breakpoint),
86 ARM11_HANDLER(remove_breakpoint),
87 ARM11_HANDLER(add_watchpoint),
88 ARM11_HANDLER(remove_watchpoint),
90 ARM11_HANDLER(run_algorithm),
92 ARM11_HANDLER(register_commands),
93 ARM11_HANDLER(target_command),
94 ARM11_HANDLER(init_target),
98 int arm11_regs_arch_type = -1;
116 ARM11_REGISTER_SPSR_FIQ,
117 ARM11_REGISTER_SPSR_SVC,
118 ARM11_REGISTER_SPSR_ABT,
119 ARM11_REGISTER_SPSR_IRQ,
120 ARM11_REGISTER_SPSR_UND,
121 ARM11_REGISTER_SPSR_MON,
130 typedef struct arm11_reg_defs_s
135 enum arm11_regtype type;
138 /* update arm11_regcache_ids when changing this */
139 static const arm11_reg_defs_t arm11_reg_defs[] =
141 {"r0", 0, 0, ARM11_REGISTER_CORE},
142 {"r1", 1, 1, ARM11_REGISTER_CORE},
143 {"r2", 2, 2, ARM11_REGISTER_CORE},
144 {"r3", 3, 3, ARM11_REGISTER_CORE},
145 {"r4", 4, 4, ARM11_REGISTER_CORE},
146 {"r5", 5, 5, ARM11_REGISTER_CORE},
147 {"r6", 6, 6, ARM11_REGISTER_CORE},
148 {"r7", 7, 7, ARM11_REGISTER_CORE},
149 {"r8", 8, 8, ARM11_REGISTER_CORE},
150 {"r9", 9, 9, ARM11_REGISTER_CORE},
151 {"r10", 10, 10, ARM11_REGISTER_CORE},
152 {"r11", 11, 11, ARM11_REGISTER_CORE},
153 {"r12", 12, 12, ARM11_REGISTER_CORE},
154 {"sp", 13, 13, ARM11_REGISTER_CORE},
155 {"lr", 14, 14, ARM11_REGISTER_CORE},
156 {"pc", 15, 15, ARM11_REGISTER_CORE},
158 #if ARM11_REGCACHE_FREGS
159 {"f0", 0, 16, ARM11_REGISTER_FX},
160 {"f1", 1, 17, ARM11_REGISTER_FX},
161 {"f2", 2, 18, ARM11_REGISTER_FX},
162 {"f3", 3, 19, ARM11_REGISTER_FX},
163 {"f4", 4, 20, ARM11_REGISTER_FX},
164 {"f5", 5, 21, ARM11_REGISTER_FX},
165 {"f6", 6, 22, ARM11_REGISTER_FX},
166 {"f7", 7, 23, ARM11_REGISTER_FX},
167 {"fps", 0, 24, ARM11_REGISTER_FPS},
170 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
172 #if ARM11_REGCACHE_MODEREGS
173 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
174 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
175 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
176 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
177 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
178 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
179 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
180 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
182 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
183 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
184 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
186 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
187 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
188 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
190 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
191 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
192 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
194 {"r13_und", 13, -1, ARM11_REGISTER_UND},
195 {"r14_und", 14, -1, ARM11_REGISTER_UND},
196 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
199 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
200 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
201 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
204 /* Debug Registers */
205 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
206 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
207 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
210 enum arm11_regcache_ids
213 ARM11_RC_RX = ARM11_RC_R0,
228 ARM11_RC_SP = ARM11_RC_R13,
230 ARM11_RC_LR = ARM11_RC_R14,
232 ARM11_RC_PC = ARM11_RC_R15,
234 #if ARM11_REGCACHE_FREGS
236 ARM11_RC_FX = ARM11_RC_F0,
249 #if ARM11_REGCACHE_MODEREGS
287 #define ARM11_GDB_REGISTER_COUNT 26
289 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
291 reg_t arm11_gdb_dummy_fp_reg =
293 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
296 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
298 reg_t arm11_gdb_dummy_fps_reg =
300 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
305 /** Check and if necessary take control of the system
307 * \param arm11 Target state variable.
308 * \param dscr If the current DSCR content is
309 * available a pointer to a word holding the
310 * DSCR can be passed. Otherwise use NULL.
312 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
316 u32 dscr_local_tmp_copy;
320 dscr = &dscr_local_tmp_copy;
321 *dscr = arm11_read_DSCR(arm11);
324 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
326 LOG_DEBUG("Bringing target into debug mode");
328 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
329 arm11_write_DSCR(arm11, *dscr);
331 /* add further reset initialization here */
333 arm11->simulate_reset_on_next_halt = true;
335 if (*dscr & ARM11_DSCR_CORE_HALTED)
337 /** \todo TODO: this needs further scrutiny because
338 * arm11_on_enter_debug_state() never gets properly called
341 arm11->target->state = TARGET_HALTED;
342 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
346 arm11->target->state = TARGET_RUNNING;
347 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
350 arm11_sc7_clear_vbw(arm11);
357 (arm11->reg_values[ARM11_RC_##x])
359 /** Save processor state.
361 * This is called when the HALT instruction has succeeded
362 * or on other occasions that stop the processor.
365 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
370 for(i = 0; i < asizeof(arm11->reg_values); i++)
372 arm11->reg_list[i].valid = 1;
373 arm11->reg_list[i].dirty = 0;
378 R(DSCR) = arm11_read_DSCR(arm11);
382 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
384 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
386 arm11_add_IR(arm11, ARM11_INTEST, -1);
388 scan_field_t chain5_fields[3];
390 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
391 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
392 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
394 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
398 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
402 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
403 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
404 ARM1136 seems to require this to issue ITR's as well */
406 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
408 /* this executes JTAG queue: */
410 arm11_write_DSCR(arm11, new_dscr);
414 Before executing any instruction in debug state you have to drain the write buffer.
415 This ensures that no imprecise Data Aborts can return at a later point:*/
417 /** \todo TODO: Test drain write buffer. */
422 /* MRC p14,0,R0,c5,c10,0 */
423 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
425 /* mcr 15, 0, r0, cr7, cr10, {4} */
426 arm11_run_instr_no_data1(arm11, 0xee070f9a);
428 u32 dscr = arm11_read_DSCR(arm11);
430 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
432 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
434 arm11_run_instr_no_data1(arm11, 0xe320f000);
436 dscr = arm11_read_DSCR(arm11);
438 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
446 arm11_run_instr_data_prepare(arm11);
451 /** \todo TODO: handle other mode registers */
454 for (i = 0; i < 15; i++)
456 /* MCR p14,0,R?,c0,c5,0 */
457 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
463 /* check rDTRfull in DSCR */
465 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
467 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
468 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
472 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
477 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
478 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
482 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
483 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
485 /* adjust PC depending on ARM state */
487 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
489 arm11->reg_values[ARM11_RC_PC] -= 0;
491 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
493 arm11->reg_values[ARM11_RC_PC] -= 4;
497 arm11->reg_values[ARM11_RC_PC] -= 8;
500 if (arm11->simulate_reset_on_next_halt)
502 arm11->simulate_reset_on_next_halt = false;
504 LOG_DEBUG("Reset c1 Control Register");
506 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
508 /* MCR p15,0,R0,c1,c0,0 */
509 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
513 arm11_run_instr_data_finish(arm11);
515 arm11_dump_reg_changes(arm11);
518 void arm11_dump_reg_changes(arm11_common_t * arm11)
521 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
523 if (!arm11->reg_list[i].valid)
525 if (arm11->reg_history[i].valid)
526 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
530 if (arm11->reg_history[i].valid)
532 if (arm11->reg_history[i].value != arm11->reg_values[i])
533 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
537 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
544 /** Restore processor state
546 * This is called in preparation for the RESTART function.
549 void arm11_leave_debug_state(arm11_common_t * arm11)
553 arm11_run_instr_data_prepare(arm11);
555 /** \todo TODO: handle other mode registers */
557 /* restore R1 - R14 */
559 for (i = 1; i < 15; i++)
561 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
564 /* MRC p14,0,r?,c0,c5,0 */
565 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
567 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
570 arm11_run_instr_data_finish(arm11);
573 /* spec says clear wDTR and rDTR; we assume they are clear as
574 otherwise our programming would be sloppy */
577 u32 DSCR = arm11_read_DSCR(arm11);
579 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
581 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
585 arm11_run_instr_data_prepare(arm11);
587 /* restore original wDTR */
589 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
591 /* MCR p14,0,R0,c0,c5,0 */
592 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
598 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
604 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
609 /* MRC p14,0,r0,c0,c5,0 */
610 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
612 arm11_run_instr_data_finish(arm11);
617 arm11_write_DSCR(arm11, R(DSCR));
622 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
624 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
626 arm11_add_IR(arm11, ARM11_EXTEST, -1);
628 scan_field_t chain5_fields[3];
630 u8 Ready = 0; /* ignored */
631 u8 Valid = 0; /* ignored */
633 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
634 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
635 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
637 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
640 arm11_record_register_history(arm11);
643 void arm11_record_register_history(arm11_common_t * arm11)
646 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
648 arm11->reg_history[i].value = arm11->reg_values[i];
649 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
651 arm11->reg_list[i].valid = 0;
652 arm11->reg_list[i].dirty = 0;
657 /* poll current target status */
658 int arm11_poll(struct target_s *target)
662 arm11_common_t * arm11 = target->arch_info;
664 if (arm11->trst_active)
667 u32 dscr = arm11_read_DSCR(arm11);
669 LOG_DEBUG("DSCR %08x", dscr);
671 arm11_check_init(arm11, &dscr);
673 if (dscr & ARM11_DSCR_CORE_HALTED)
675 if (target->state != TARGET_HALTED)
677 enum target_state old_state = target->state;
679 LOG_DEBUG("enter TARGET_HALTED");
680 target->state = TARGET_HALTED;
681 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
682 arm11_on_enter_debug_state(arm11);
684 target_call_event_callbacks(target,
685 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
690 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
692 LOG_DEBUG("enter TARGET_RUNNING");
693 target->state = TARGET_RUNNING;
694 target->debug_reason = DBG_REASON_NOTHALTED;
700 /* architecture specific status reply */
701 int arm11_arch_state(struct target_s *target)
703 FNC_INFO_NOTIMPLEMENTED;
709 /* target request support */
710 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
712 FNC_INFO_NOTIMPLEMENTED;
719 /* target execution control */
720 int arm11_halt(struct target_s *target)
724 arm11_common_t * arm11 = target->arch_info;
726 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
728 if (target->state == TARGET_UNKNOWN)
730 arm11->simulate_reset_on_next_halt = true;
733 if (target->state == TARGET_HALTED)
735 LOG_DEBUG("target was already halted");
739 if (arm11->trst_active)
741 arm11->halt_requested = true;
745 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
747 jtag_execute_queue();
753 dscr = arm11_read_DSCR(arm11);
755 if (dscr & ARM11_DSCR_CORE_HALTED)
759 arm11_on_enter_debug_state(arm11);
761 enum target_state old_state = target->state;
763 target->state = TARGET_HALTED;
764 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
766 target_call_event_callbacks(target,
767 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
773 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
777 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
778 // current, address, handle_breakpoints, debug_execution);
780 arm11_common_t * arm11 = target->arch_info;
782 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
784 if (target->state != TARGET_HALTED)
786 LOG_WARNING("target was not halted");
787 return ERROR_TARGET_NOT_HALTED;
793 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
795 /* clear breakpoints/watchpoints and VCR*/
796 arm11_sc7_clear_vbw(arm11);
798 /* Set up breakpoints */
799 if (!debug_execution)
801 /* check if one matches PC and step over it if necessary */
805 for (bp = target->breakpoints; bp; bp = bp->next)
807 if (bp->address == R(PC))
809 LOG_DEBUG("must step over %08x", bp->address);
810 arm11_step(target, 1, 0, 0);
815 /* set all breakpoints */
819 for (bp = target->breakpoints; bp; bp = bp->next)
821 arm11_sc7_action_t brp[2];
824 brp[0].address = ARM11_SC7_BVR0 + brp_num;
825 brp[0].value = bp->address;
827 brp[1].address = ARM11_SC7_BCR0 + brp_num;
828 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
830 arm11_sc7_run(arm11, brp, asizeof(brp));
832 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
837 arm11_sc7_set_vcr(arm11, arm11_vcr);
841 arm11_leave_debug_state(arm11);
843 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
845 jtag_execute_queue();
849 u32 dscr = arm11_read_DSCR(arm11);
851 LOG_DEBUG("DSCR %08x", dscr);
853 if (dscr & ARM11_DSCR_CORE_RESTARTED)
857 if (!debug_execution)
859 target->state = TARGET_RUNNING;
860 target->debug_reason = DBG_REASON_NOTHALTED;
861 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
865 target->state = TARGET_DEBUG_RUNNING;
866 target->debug_reason = DBG_REASON_NOTHALTED;
867 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
873 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
877 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
879 if (target->state != TARGET_HALTED)
881 LOG_WARNING("target was not halted");
882 return ERROR_TARGET_NOT_HALTED;
885 arm11_common_t * arm11 = target->arch_info;
890 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
892 /** \todo TODO: Thumb not supported here */
894 u32 next_instruction;
896 arm11_read_memory_word(arm11, R(PC), &next_instruction);
899 if ((next_instruction & 0xFFF00070) == 0xe1200070)
902 arm11->reg_list[ARM11_RC_PC].valid = 1;
903 arm11->reg_list[ARM11_RC_PC].dirty = 0;
904 LOG_INFO("Skipping BKPT");
906 /* skip over Wait for interrupt / Standby */
907 /* mcr 15, 0, r?, cr7, cr0, {4} */
908 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
911 arm11->reg_list[ARM11_RC_PC].valid = 1;
912 arm11->reg_list[ARM11_RC_PC].dirty = 0;
913 LOG_INFO("Skipping WFI");
915 /* ignore B to self */
916 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
918 LOG_INFO("Not stepping jump to self");
922 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
925 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
926 * the VCR might be something worth looking into. */
929 /* Set up breakpoint for stepping */
931 arm11_sc7_action_t brp[2];
934 brp[0].address = ARM11_SC7_BVR0;
935 brp[0].value = R(PC);
937 brp[1].address = ARM11_SC7_BCR0;
938 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
940 arm11_sc7_run(arm11, brp, asizeof(brp));
944 arm11_leave_debug_state(arm11);
946 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
948 jtag_execute_queue();
950 /** \todo TODO: add a timeout */
956 u32 dscr = arm11_read_DSCR(arm11);
958 LOG_DEBUG("DSCR %08x", dscr);
960 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
961 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
965 /* clear breakpoint */
966 arm11_sc7_clear_vbw(arm11);
969 arm11_on_enter_debug_state(arm11);
972 // target->state = TARGET_HALTED;
973 target->debug_reason = DBG_REASON_SINGLESTEP;
975 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
981 /* target reset control */
982 int arm11_assert_reset(struct target_s *target)
987 /* assert reset lines */
988 /* resets only the DBGTAP, not the ARM */
990 jtag_add_reset(1, 0);
991 jtag_add_sleep(5000);
993 arm11_common_t * arm11 = target->arch_info;
994 arm11->trst_active = true;
1000 int arm11_deassert_reset(struct target_s *target)
1005 LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
1007 /* deassert reset lines */
1008 jtag_add_reset(0, 0);
1010 arm11_common_t * arm11 = target->arch_info;
1011 arm11->trst_active = false;
1013 if (arm11->halt_requested)
1014 return arm11_halt(target);
1020 int arm11_soft_reset_halt(struct target_s *target)
1022 FNC_INFO_NOTIMPLEMENTED;
1029 /* target register access for gdb */
1030 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1034 arm11_common_t * arm11 = target->arch_info;
1036 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1037 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1040 for (i = 16; i < 24; i++)
1042 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1045 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1049 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1051 if (arm11_reg_defs[i].gdb_num == -1)
1054 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1061 /* target memory access
1062 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1063 * count: number of items of <size>
1065 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1067 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1071 if (target->state != TARGET_HALTED)
1073 LOG_WARNING("target was not halted");
1074 return ERROR_TARGET_NOT_HALTED;
1077 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1079 arm11_common_t * arm11 = target->arch_info;
1081 arm11_run_instr_data_prepare(arm11);
1083 /* MRC p14,0,r0,c0,c5,0 */
1084 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1089 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1090 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1093 for (i = 0; i < count; i++)
1095 /* ldrb r1, [r0], #1 */
1096 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1099 /* MCR p14,0,R1,c0,c5,0 */
1100 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1109 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1111 u16 * buf16 = (u16*)buffer;
1114 for (i = 0; i < count; i++)
1116 /* ldrh r1, [r0], #2 */
1117 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1121 /* MCR p14,0,R1,c0,c5,0 */
1122 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1132 /* LDC p14,c5,[R0],#4 */
1133 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1137 arm11_run_instr_data_finish(arm11);
1142 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1146 if (target->state != TARGET_HALTED)
1148 LOG_WARNING("target was not halted");
1149 return ERROR_TARGET_NOT_HALTED;
1152 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1154 arm11_common_t * arm11 = target->arch_info;
1156 arm11_run_instr_data_prepare(arm11);
1158 /* MRC p14,0,r0,c0,c5,0 */
1159 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1165 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1168 for (i = 0; i < count; i++)
1170 /* MRC p14,0,r1,c0,c5,0 */
1171 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1173 /* strb r1, [r0], #1 */
1174 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1182 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1184 u16 * buf16 = (u16*)buffer;
1187 for (i = 0; i < count; i++)
1189 /* MRC p14,0,r1,c0,c5,0 */
1190 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1192 /* strh r1, [r0], #2 */
1193 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1200 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1202 if (!arm11_config_memwrite_burst)
1204 /* STC p14,c5,[R0],#4 */
1205 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1209 /* STC p14,c5,[R0],#4 */
1210 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1217 /* r0 verification */
1221 /* MCR p14,0,R0,c0,c5,0 */
1222 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1224 if (address + size * count != r0)
1226 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1228 if (arm11_config_memwrite_burst)
1229 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1231 if (arm11_config_memwrite_error_fatal)
1238 arm11_run_instr_data_finish(arm11);
1247 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1248 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1252 if (target->state != TARGET_HALTED)
1254 LOG_WARNING("target was not halted");
1255 return ERROR_TARGET_NOT_HALTED;
1258 return arm11_write_memory(target, address, 4, count, buffer);
1262 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1264 FNC_INFO_NOTIMPLEMENTED;
1270 /* target break-/watchpoint control
1271 * rw: 0 = write, 1 = read, 2 = access
1273 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1277 arm11_common_t * arm11 = target->arch_info;
1280 if (breakpoint->type == BKPT_SOFT)
1282 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1287 if (!arm11->free_brps)
1289 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1290 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1293 if (breakpoint->length != 4)
1295 LOG_INFO("only breakpoints of four bytes length supported");
1296 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1304 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1308 arm11_common_t * arm11 = target->arch_info;
1315 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1317 FNC_INFO_NOTIMPLEMENTED;
1322 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1324 FNC_INFO_NOTIMPLEMENTED;
1330 /* target algorithm support */
1331 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
1333 FNC_INFO_NOTIMPLEMENTED;
1338 int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
1344 LOG_ERROR("'target arm11' 4th argument <jtag chain pos>");
1348 int chain_pos = strtoul(args[3], NULL, 0);
1350 NEW(arm11_common_t, arm11, 1);
1352 arm11->target = target;
1354 /* prepare JTAG information for the new target */
1355 arm11->jtag_info.chain_pos = chain_pos;
1356 arm11->jtag_info.scann_size = 5;
1358 arm_jtag_setup_connection(&arm11->jtag_info);
1360 jtag_device_t *device = jtag_get_device(chain_pos);
1362 if (device->ir_length != 5)
1364 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1368 target->arch_info = arm11;
1373 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1377 arm11_common_t * arm11 = target->arch_info;
1381 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1383 scan_field_t idcode_field;
1385 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1387 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1391 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1393 arm11_add_IR(arm11, ARM11_INTEST, -1);
1395 scan_field_t chain0_fields[2];
1397 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1398 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1400 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1402 jtag_execute_queue();
1405 switch (arm11->device_id & 0x0FFFF000)
1407 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1408 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1409 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1412 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1417 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1419 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1420 arm11->debug_version != ARM11_DEBUG_V61)
1422 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1427 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1428 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1430 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1431 arm11->free_brps = arm11->brp;
1432 arm11->free_wrps = arm11->wrp;
1434 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1439 arm11_build_reg_cache(target);
1442 /* as a side-effect this reads DSCR and thus
1443 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1444 * as suggested by the spec.
1447 arm11_check_init(arm11, NULL);
1452 int arm11_quit(void)
1454 FNC_INFO_NOTIMPLEMENTED;
1459 /** Load a register that is marked !valid in the register cache */
1460 int arm11_get_reg(reg_t *reg)
1464 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1466 if (target->state != TARGET_HALTED)
1468 LOG_WARNING("target was not halted");
1469 return ERROR_TARGET_NOT_HALTED;
1472 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1475 arm11_common_t *arm11 = target->arch_info;
1476 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1482 /** Change a value in the register cache */
1483 int arm11_set_reg(reg_t *reg, u8 *buf)
1487 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1488 arm11_common_t *arm11 = target->arch_info;
1489 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1491 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1499 void arm11_build_reg_cache(target_t *target)
1501 arm11_common_t *arm11 = target->arch_info;
1503 NEW(reg_cache_t, cache, 1);
1504 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1505 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1507 if (arm11_regs_arch_type == -1)
1508 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1510 arm11->reg_list = reg_list;
1512 /* Build the process context cache */
1513 cache->name = "arm11 registers";
1515 cache->reg_list = reg_list;
1516 cache->num_regs = ARM11_REGCACHE_COUNT;
1518 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1521 // armv7m->core_cache = cache;
1522 // armv7m->process_context = cache;
1526 /* Not very elegant assertion */
1527 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1528 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1529 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1531 LOG_ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1535 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1537 reg_t * r = reg_list + i;
1538 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1539 arm11_reg_state_t * rs = arm11_reg_states + i;
1543 r->value = (u8 *)(arm11->reg_values + i);
1546 r->bitfield_desc = NULL;
1547 r->num_bitfields = 0;
1548 r->arch_type = arm11_regs_arch_type;
1552 rs->target = target;
1558 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1562 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1567 return ERROR_COMMAND_SYNTAX_ERROR;
1572 case 'f': /* false */
1574 case 'd': /* disable */
1580 case 't': /* true */
1582 case 'e': /* enable */
1588 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1594 #define BOOL_WRAPPER(name, print_name) \
1595 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1597 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1600 #define RC_TOP(name, descr, more) \
1602 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1603 command_t * top_cmd = new_cmd; \
1607 #define RC_FINAL(name, descr, handler) \
1608 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1610 #define RC_FINAL_BOOL(name, descr, var) \
1611 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1614 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1615 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1618 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1622 arm11_vcr = strtoul(args[0], NULL, 0);
1626 return ERROR_COMMAND_SYNTAX_ERROR;
1629 LOG_INFO("VCR 0x%08X", arm11_vcr);
1633 const u32 arm11_coproc_instruction_limits[] =
1635 15, /* coprocessor */
1640 0xFFFFFFFF, /* value */
1643 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1644 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1647 arm11_common_t * arm11_find_target(const char * arg)
1649 size_t jtag_target = strtoul(arg, NULL, 0);
1652 for (t = targets; t; t = t->next)
1654 if (t->type != &arm11_target)
1657 arm11_common_t * arm11 = t->arch_info;
1659 if (arm11->jtag_info.chain_pos != jtag_target)
1668 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1670 if (argc != (read ? 6 : 7))
1672 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1676 arm11_common_t * arm11 = arm11_find_target(args[0]);
1680 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1681 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1687 if (arm11->target->state != TARGET_HALTED)
1689 LOG_WARNING("target was not halted");
1690 return ERROR_TARGET_NOT_HALTED;
1697 for (i = 0; i < (read ? 5 : 6); i++)
1699 values[i] = strtoul(args[i + 1], NULL, 0);
1701 if (values[i] > arm11_coproc_instruction_limits[i])
1703 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1704 i + 2, arm11_coproc_instruction_limits[i],
1705 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1710 u32 instr = 0xEE000010 |
1718 instr |= 0x00100000;
1721 arm11_run_instr_data_prepare(arm11);
1726 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1728 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1729 values[0], values[1], values[2], values[3], values[4], result, result);
1733 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1735 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1736 values[0], values[1],
1738 values[2], values[3], values[4]);
1741 arm11_run_instr_data_finish(arm11);
1747 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1749 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1752 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1754 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1757 int arm11_register_commands(struct command_context_s *cmd_ctx)
1761 command_t * top_cmd = NULL;
1763 RC_TOP( "arm11", "arm11 specific commands",
1765 RC_TOP( "memwrite", "Control memory write transfer mode",
1767 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1770 RC_FINAL_BOOL( "error_fatal",
1771 "Terminate program if transfer error was found (default: enabled)",
1772 memwrite_error_fatal)
1775 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1778 RC_FINAL( "mrc", "Read Coprocessor register",
1781 RC_FINAL( "mcr", "Write Coprocessor register",