git.sur5r.net Git - openocd/blob - src/target/arm11.c

   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
   6  *                                                                         *
   7  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "etm.h"
  30 #include "breakpoints.h"
  31 #include "arm11_dbgtap.h"
  32 #include "arm_simulator.h"
  33 #include "time_support.h"
  34 #include "target_type.h"
  35 #include "algorithm.h"
  36 #include "register.h"
  37
  38
  39 #if 0
  40 #define _DEBUG_INSTRUCTION_EXECUTION_
  41 #endif
  42
  43 static bool arm11_config_memwrite_burst = true;
  44 static bool arm11_config_memwrite_error_fatal = true;
  45 static uint32_t arm11_vcr = 0;
  46 static bool arm11_config_step_irq_enable = false;
  47 static bool arm11_config_hardware_step = false;
  48
  49 enum arm11_regtype
  50 {
  51         /* debug regs */
  52         ARM11_REGISTER_DSCR,
  53         ARM11_REGISTER_WDTR,
  54         ARM11_REGISTER_RDTR,
  55 };
  56
  57
  58 struct arm11_reg_defs
  59 {
  60         char *                                  name;
  61         uint32_t                                                num;
  62         int                                             gdb_num;
  63         enum arm11_regtype              type;
  64 };
  65
  66 /* update arm11_regcache_ids when changing this */
  67 static const struct arm11_reg_defs arm11_reg_defs[] =
  68 {
  69         /* Debug Registers */
  70         {"dscr",        0,      -1,     ARM11_REGISTER_DSCR},
  71         {"wdtr",        0,      -1,     ARM11_REGISTER_WDTR},
  72         {"rdtr",        0,      -1,     ARM11_REGISTER_RDTR},
  73 };
  74
  75 enum arm11_regcache_ids
  76 {
  77         ARM11_RC_DSCR,
  78         ARM11_RC_WDTR,
  79         ARM11_RC_RDTR,
  80
  81         ARM11_RC_MAX,
  82 };
  83
  84 static int arm11_on_enter_debug_state(struct arm11_common *arm11);
  85 static int arm11_step(struct target *target, int current,
  86                 uint32_t address, int handle_breakpoints);
  87 /* helpers */
  88 static int arm11_build_reg_cache(struct target *target);
  89 static int arm11_set_reg(struct reg *reg, uint8_t *buf);
  90 static int arm11_get_reg(struct reg *reg);
  91
  92
  93 /** Check and if necessary take control of the system
  94  *
  95  * \param arm11         Target state variable.
  96  * \param dscr          If the current DSCR content is
  97  *                                      available a pointer to a word holding the
  98  *                                      DSCR can be passed. Otherwise use NULL.
  99  */
 100 static int arm11_check_init(struct arm11_common *arm11, uint32_t *dscr)
 101 {
 102         uint32_t                        dscr_local_tmp_copy;
 103
 104         if (!dscr)
 105         {
 106                 dscr = &dscr_local_tmp_copy;
 107
 108                 CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
 109         }
 110
 111         if (!(*dscr & ARM11_DSCR_MODE_SELECT))
 112         {
 113                 LOG_DEBUG("Bringing target into debug mode");
 114
 115                 *dscr |= ARM11_DSCR_MODE_SELECT;                /* Halt debug-mode */
 116                 arm11_write_DSCR(arm11, *dscr);
 117
 118                 /* add further reset initialization here */
 119
 120                 arm11->simulate_reset_on_next_halt = true;
 121
 122                 if (*dscr & ARM11_DSCR_CORE_HALTED)
 123                 {
 124                         /** \todo TODO: this needs further scrutiny because
 125                           * arm11_on_enter_debug_state() never gets properly called.
 126                           * As a result we don't read the actual register states from
 127                           * the target.
 128                           */
 129
 130                         arm11->arm.target->state = TARGET_HALTED;
 131                         arm11->arm.target->debug_reason =
 132                                         arm11_get_DSCR_debug_reason(*dscr);
 133                 }
 134                 else
 135                 {
 136                         arm11->arm.target->state = TARGET_RUNNING;
 137                         arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
 138                 }
 139
 140                 arm11_sc7_clear_vbw(arm11);
 141         }
 142
 143         return ERROR_OK;
 144 }
 145
 146
 147
 148 #define R(x) \
 149         (arm11->reg_values[ARM11_RC_##x])
 150
 151 /** Save processor state.
 152   *
 153   * This is called when the HALT instruction has succeeded
 154   * or on other occasions that stop the processor.
 155   *
 156   */
 157 static int arm11_on_enter_debug_state(struct arm11_common *arm11)
 158 {
 159         int retval;
 160
 161         /* REVISIT entire cache should already be invalid !!! */
 162         register_cache_invalidate(arm11->arm.core_cache);
 163
 164         for (size_t i = 0; i < ARRAY_SIZE(arm11->reg_values); i++)
 165         {
 166                 arm11->reg_list[i].valid        = 1;
 167                 arm11->reg_list[i].dirty        = 0;
 168         }
 169
 170         /* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
 171
 172         /* Save DSCR */
 173         CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
 174
 175         /* Save wDTR */
 176
 177         if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
 178         {
 179                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 180
 181                 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 182
 183                 struct scan_field       chain5_fields[3];
 184
 185                 arm11_setup_field(arm11, 32, NULL, &R(WDTR),    chain5_fields + 0);
 186                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
 187                 arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
 188
 189                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 190         }
 191         else
 192         {
 193                 arm11->reg_list[ARM11_RC_WDTR].valid    = 0;
 194         }
 195
 196
 197         /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
 198          *
 199          * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
 200          * but not to issue ITRs. ARM1136 seems to require this to issue
 201          * ITR's as well...
 202          */
 203         uint32_t new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
 204
 205         /* this executes JTAG queue: */
 206
 207         arm11_write_DSCR(arm11, new_dscr);
 208
 209
 210         /* From the spec:
 211            Before executing any instruction in debug state you have to drain the write buffer.
 212            This ensures that no imprecise Data Aborts can return at a later point:*/
 213
 214         /** \todo TODO: Test drain write buffer. */
 215
 216 #if 0
 217         while (1)
 218         {
 219                 /* MRC p14,0,R0,c5,c10,0 */
 220                 //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
 221
 222                 /* mcr     15, 0, r0, cr7, cr10, {4} */
 223                 arm11_run_instr_no_data1(arm11, 0xee070f9a);
 224
 225                 uint32_t dscr = arm11_read_DSCR(arm11);
 226
 227                 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 228
 229                 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
 230                 {
 231                         arm11_run_instr_no_data1(arm11, 0xe320f000);
 232
 233                         dscr = arm11_read_DSCR(arm11);
 234
 235                         LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
 236
 237                         break;
 238                 }
 239         }
 240 #endif
 241
 242         /* Save registers.
 243          *
 244          * NOTE:  ARM1136 TRM suggests saving just R0 here now, then
 245          * CPSR and PC after the rDTR stuff.  We do it all at once.
 246          */
 247         retval = arm_dpm_read_current_registers(&arm11->dpm);
 248         if (retval != ERROR_OK)
 249                 LOG_ERROR("DPM REG READ -- fail %d", retval);
 250
 251         retval = arm11_run_instr_data_prepare(arm11);
 252         if (retval != ERROR_OK)
 253                 return retval;
 254
 255         /* maybe save rDTR */
 256
 257         /* check rDTRfull in DSCR */
 258
 259         if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
 260         {
 261                 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
 262                 retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
 263                 if (retval != ERROR_OK)
 264                         return retval;
 265         }
 266         else
 267         {
 268                 arm11->reg_list[ARM11_RC_RDTR].valid    = 0;
 269         }
 270
 271         /* REVISIT Now that we've saved core state, there's may also
 272          * be MMU and cache state to care about ...
 273          */
 274
 275         if (arm11->simulate_reset_on_next_halt)
 276         {
 277                 arm11->simulate_reset_on_next_halt = false;
 278
 279                 LOG_DEBUG("Reset c1 Control Register");
 280
 281                 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
 282
 283                 /* MCR p15,0,R0,c1,c0,0 */
 284                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
 285                 if (retval != ERROR_OK)
 286                         return retval;
 287
 288         }
 289
 290         retval = arm11_run_instr_data_finish(arm11);
 291         if (retval != ERROR_OK)
 292                 return retval;
 293
 294         return ERROR_OK;
 295 }
 296
 297 /**
 298  * Restore processor state.  This is called in preparation for
 299  * the RESTART function.
 300  */
 301 static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 302 {
 303         int retval;
 304
 305         /* See e.g. ARM1136 TRM, "14.8.5 Leaving Debug state" */
 306
 307         /* NOTE:  the ARM1136 TRM suggests restoring all registers
 308          * except R0/PC/CPSR right now.  Instead, we do them all
 309          * at once, just a bit later on.
 310          */
 311
 312         /* REVISIT once we start caring about MMU and cache state,
 313          * address it here ...
 314          */
 315
 316         /* spec says clear wDTR and rDTR; we assume they are clear as
 317            otherwise our programming would be sloppy */
 318         {
 319                 uint32_t DSCR;
 320
 321                 CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
 322
 323                 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 324                 {
 325                         /*
 326                         The wDTR/rDTR two registers that are used to send/receive data to/from
 327                         the core in tandem with corresponding instruction codes that are
 328                         written into the core. The RDTR FULL/WDTR FULL flag indicates that the
 329                         registers hold data that was written by one side (CPU or JTAG) and not
 330                         read out by the other side.
 331                         */
 332                         LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 333                         return ERROR_FAIL;
 334                 }
 335         }
 336
 337         /* maybe restore original wDTR */
 338         if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
 339         {
 340                 retval = arm11_run_instr_data_prepare(arm11);
 341                 if (retval != ERROR_OK)
 342                         return retval;
 343
 344                 /* MCR p14,0,R0,c0,c5,0 */
 345                 retval = arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
 346                 if (retval != ERROR_OK)
 347                         return retval;
 348
 349                 retval = arm11_run_instr_data_finish(arm11);
 350                 if (retval != ERROR_OK)
 351                         return retval;
 352         }
 353
 354         /* restore CPSR, PC, and R0 ... after flushing any modified
 355          * registers.
 356          */
 357         retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 358
 359         register_cache_invalidate(arm11->arm.core_cache);
 360
 361         /* restore DSCR */
 362
 363         arm11_write_DSCR(arm11, R(DSCR));
 364
 365         /* maybe restore rDTR */
 366
 367         if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
 368         {
 369                 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 370
 371                 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 372
 373                 struct scan_field       chain5_fields[3];
 374
 375                 uint8_t                 Ready           = 0;    /* ignored */
 376                 uint8_t                 Valid           = 0;    /* ignored */
 377
 378                 arm11_setup_field(arm11, 32, &R(RDTR),  NULL, chain5_fields + 0);
 379                 arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
 380                 arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 381
 382                 arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
 383         }
 384
 385         /* now processor is ready to RESTART */
 386
 387         return ERROR_OK;
 388 }
 389
 390 /* poll current target status */
 391 static int arm11_poll(struct target *target)
 392 {
 393         int retval;
 394         struct arm11_common *arm11 = target_to_arm11(target);
 395         uint32_t        dscr;
 396
 397         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 398
 399         LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 400
 401         CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 402
 403         if (dscr & ARM11_DSCR_CORE_HALTED)
 404         {
 405                 if (target->state != TARGET_HALTED)
 406                 {
 407                         enum target_state old_state = target->state;
 408
 409                         LOG_DEBUG("enter TARGET_HALTED");
 410                         target->state                   = TARGET_HALTED;
 411                         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 412                         retval = arm11_on_enter_debug_state(arm11);
 413                         if (retval != ERROR_OK)
 414                                 return retval;
 415
 416                         target_call_event_callbacks(target,
 417                                 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
 418                 }
 419         }
 420         else
 421         {
 422                 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
 423                 {
 424                         LOG_DEBUG("enter TARGET_RUNNING");
 425                         target->state                   = TARGET_RUNNING;
 426                         target->debug_reason    = DBG_REASON_NOTHALTED;
 427                 }
 428         }
 429
 430         return ERROR_OK;
 431 }
 432 /* architecture specific status reply */
 433 static int arm11_arch_state(struct target *target)
 434 {
 435         int retval;
 436
 437         retval = armv4_5_arch_state(target);
 438
 439         /* REVISIT also display ARM11-specific MMU and cache status ... */
 440
 441         return retval;
 442 }
 443
 444 /* target request support */
 445 static int arm11_target_request_data(struct target *target,
 446                 uint32_t size, uint8_t *buffer)
 447 {
 448         LOG_WARNING("Not implemented: %s", __func__);
 449
 450         return ERROR_FAIL;
 451 }
 452
 453 /* target execution control */
 454 static int arm11_halt(struct target *target)
 455 {
 456         struct arm11_common *arm11 = target_to_arm11(target);
 457
 458         LOG_DEBUG("target->state: %s",
 459                 target_state_name(target));
 460
 461         if (target->state == TARGET_UNKNOWN)
 462         {
 463                 arm11->simulate_reset_on_next_halt = true;
 464         }
 465
 466         if (target->state == TARGET_HALTED)
 467         {
 468                 LOG_DEBUG("target was already halted");
 469                 return ERROR_OK;
 470         }
 471
 472         arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 473
 474         CHECK_RETVAL(jtag_execute_queue());
 475
 476         uint32_t dscr;
 477
 478         int i = 0;
 479         while (1)
 480         {
 481                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 482
 483                 if (dscr & ARM11_DSCR_CORE_HALTED)
 484                         break;
 485
 486
 487                 long long then = 0;
 488                 if (i == 1000)
 489                 {
 490                         then = timeval_ms();
 491                 }
 492                 if (i >= 1000)
 493                 {
 494                         if ((timeval_ms()-then) > 1000)
 495                         {
 496                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 497                                 return ERROR_FAIL;
 498                         }
 499                 }
 500                 i++;
 501         }
 502
 503         arm11_on_enter_debug_state(arm11);
 504
 505         enum target_state old_state     = target->state;
 506
 507         target->state           = TARGET_HALTED;
 508         target->debug_reason    = arm11_get_DSCR_debug_reason(dscr);
 509
 510         CHECK_RETVAL(
 511                 target_call_event_callbacks(target,
 512                         old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 513
 514         return ERROR_OK;
 515 }
 516
 517 static uint32_t
 518 arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 519 {
 520         void *value = arm11->arm.core_cache->reg_list[15].value;
 521
 522         if (!current)
 523                 buf_set_u32(value, 0, 32, address);
 524         else
 525                 address = buf_get_u32(value, 0, 32);
 526
 527         return address;
 528 }
 529
 530 static int arm11_resume(struct target *target, int current,
 531                 uint32_t address, int handle_breakpoints, int debug_execution)
 532 {
 533         //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
 534         //      current, address, handle_breakpoints, debug_execution);
 535
 536         struct arm11_common *arm11 = target_to_arm11(target);
 537
 538         LOG_DEBUG("target->state: %s",
 539                 target_state_name(target));
 540
 541
 542         if (target->state != TARGET_HALTED)
 543         {
 544                 LOG_ERROR("Target not halted");
 545                 return ERROR_TARGET_NOT_HALTED;
 546         }
 547
 548         address = arm11_nextpc(arm11, current, address);
 549
 550         LOG_DEBUG("RESUME PC %08" PRIx32 "%s", address, !current ? "!" : "");
 551
 552         /* clear breakpoints/watchpoints and VCR*/
 553         arm11_sc7_clear_vbw(arm11);
 554
 555         if (!debug_execution)
 556                 target_free_all_working_areas(target);
 557
 558         /* Set up breakpoints */
 559         if (handle_breakpoints)
 560         {
 561                 /* check if one matches PC and step over it if necessary */
 562
 563                 struct breakpoint *     bp;
 564
 565                 for (bp = target->breakpoints; bp; bp = bp->next)
 566                 {
 567                         if (bp->address == address)
 568                         {
 569                                 LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 570                                 arm11_step(target, 1, 0, 0);
 571                                 break;
 572                         }
 573                 }
 574
 575                 /* set all breakpoints */
 576
 577                 unsigned brp_num = 0;
 578
 579                 for (bp = target->breakpoints; bp; bp = bp->next)
 580                 {
 581                         struct arm11_sc7_action brp[2];
 582
 583                         brp[0].write    = 1;
 584                         brp[0].address  = ARM11_SC7_BVR0 + brp_num;
 585                         brp[0].value    = bp->address;
 586                         brp[1].write    = 1;
 587                         brp[1].address  = ARM11_SC7_BCR0 + brp_num;
 588                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 589
 590                         arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp));
 591
 592                         LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
 593                                         bp->address);
 594
 595                         brp_num++;
 596                 }
 597
 598                 arm11_sc7_set_vcr(arm11, arm11_vcr);
 599         }
 600
 601         arm11_leave_debug_state(arm11, handle_breakpoints);
 602
 603         arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 604
 605         CHECK_RETVAL(jtag_execute_queue());
 606
 607         int i = 0;
 608         while (1)
 609         {
 610                 uint32_t dscr;
 611
 612                 CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 613
 614                 LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 615
 616                 if (dscr & ARM11_DSCR_CORE_RESTARTED)
 617                         break;
 618
 619
 620                 long long then = 0;
 621                 if (i == 1000)
 622                 {
 623                         then = timeval_ms();
 624                 }
 625                 if (i >= 1000)
 626                 {
 627                         if ((timeval_ms()-then) > 1000)
 628                         {
 629                                 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 630                                 return ERROR_FAIL;
 631                         }
 632                 }
 633                 i++;
 634         }
 635
 636         if (!debug_execution)
 637         {
 638                 target->state                   = TARGET_RUNNING;
 639                 target->debug_reason    = DBG_REASON_NOTHALTED;
 640
 641                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 642         }
 643         else
 644         {
 645                 target->state                   = TARGET_DEBUG_RUNNING;
 646                 target->debug_reason    = DBG_REASON_NOTHALTED;
 647
 648                 CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 649         }
 650
 651         return ERROR_OK;
 652 }
 653
 654 static int arm11_step(struct target *target, int current,
 655                 uint32_t address, int handle_breakpoints)
 656 {
 657         LOG_DEBUG("target->state: %s",
 658                 target_state_name(target));
 659
 660         if (target->state != TARGET_HALTED)
 661         {
 662                 LOG_WARNING("target was not halted");
 663                 return ERROR_TARGET_NOT_HALTED;
 664         }
 665
 666         struct arm11_common *arm11 = target_to_arm11(target);
 667
 668         address = arm11_nextpc(arm11, current, address);
 669
 670         LOG_DEBUG("STEP PC %08" PRIx32 "%s", address, !current ? "!" : "");
 671
 672
 673         /** \todo TODO: Thumb not supported here */
 674
 675         uint32_t        next_instruction;
 676
 677         CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
 678
 679         /* skip over BKPT */
 680         if ((next_instruction & 0xFFF00070) == 0xe1200070)
 681         {
 682                 address = arm11_nextpc(arm11, 0, address + 4);
 683                 LOG_DEBUG("Skipping BKPT");
 684         }
 685         /* skip over Wait for interrupt / Standby */
 686         /* mcr  15, 0, r?, cr7, cr0, {4} */
 687         else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
 688         {
 689                 address = arm11_nextpc(arm11, 0, address + 4);
 690                 LOG_DEBUG("Skipping WFI");
 691         }
 692         /* ignore B to self */
 693         else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
 694         {
 695                 LOG_DEBUG("Not stepping jump to self");
 696         }
 697         else
 698         {
 699                 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
 700                 * with this. */
 701
 702                 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
 703                 * the VCR might be something worth looking into. */
 704
 705
 706                 /* Set up breakpoint for stepping */
 707
 708                 struct arm11_sc7_action brp[2];
 709
 710                 brp[0].write    = 1;
 711                 brp[0].address  = ARM11_SC7_BVR0;
 712                 brp[1].write    = 1;
 713                 brp[1].address  = ARM11_SC7_BCR0;
 714
 715                 if (arm11_config_hardware_step)
 716                 {
 717                         /* Hardware single stepping ("instruction address
 718                          * mismatch") is used if enabled.  It's not quite
 719                          * exactly "run one instruction"; "branch to here"
 720                          * loops won't break, neither will some other cases,
 721                          * but it's probably the best default.
 722                          *
 723                          * Hardware single stepping isn't supported on v6
 724                          * debug modules.  ARM1176 and v7 can support it...
 725                          *
 726                          * FIXME Thumb stepping likely needs to use 0x03
 727                          * or 0xc0 byte masks, not 0x0f.
 728                          */
 729                          brp[0].value   = address;
 730                          brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
 731                                         | (0 << 14) | (0 << 16) | (0 << 20)
 732                                         | (2 << 21);
 733                 } else
 734                 {
 735                         /* Sets a breakpoint on the next PC, as calculated
 736                          * by instruction set simulation.
 737                          *
 738                          * REVISIT stepping Thumb on ARM1156 requires Thumb2
 739                          * support from the simulator.
 740                          */
 741                         uint32_t next_pc;
 742                         int retval;
 743
 744                         retval = arm_simulate_step(target, &next_pc);
 745                         if (retval != ERROR_OK)
 746                                 return retval;
 747
 748                         brp[0].value    = next_pc;
 749                         brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
 750                                         | (0 << 14) | (0 << 16) | (0 << 20)
 751                                         | (0 << 21);
 752                 }
 753
 754                 CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 755
 756                 /* resume */
 757
 758
 759                 if (arm11_config_step_irq_enable)
 760                         R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;              /* should be redundant */
 761                 else
 762                         R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
 763
 764
 765                 CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
 766
 767                 arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
 768
 769                 CHECK_RETVAL(jtag_execute_queue());
 770
 771                 /* wait for halt */
 772                 int i = 0;
 773                 while (1)
 774                 {
 775                         uint32_t dscr;
 776
 777                         CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 778
 779                         LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
 780
 781                         if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
 782                                 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
 783                                 break;
 784
 785                         long long then = 0;
 786                         if (i == 1000)
 787                         {
 788                                 then = timeval_ms();
 789                         }
 790                         if (i >= 1000)
 791                         {
 792                                 if ((timeval_ms()-then) > 1000)
 793                                 {
 794                                         LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
 795                                         return ERROR_FAIL;
 796                                 }
 797                         }
 798                         i++;
 799                 }
 800
 801                 /* clear breakpoint */
 802                 arm11_sc7_clear_vbw(arm11);
 803
 804                 /* save state */
 805                 CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
 806
 807             /* restore default state */
 808                 R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
 809
 810         }
 811
 812         //        target->state         = TARGET_HALTED;
 813         target->debug_reason    = DBG_REASON_SINGLESTEP;
 814
 815         CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 816
 817         return ERROR_OK;
 818 }
 819
 820 static int arm11_assert_reset(struct target *target)
 821 {
 822         int retval;
 823         struct arm11_common *arm11 = target_to_arm11(target);
 824
 825         retval = arm11_check_init(arm11, NULL);
 826         if (retval != ERROR_OK)
 827                 return retval;
 828
 829         target->state = TARGET_UNKNOWN;
 830
 831         /* we would very much like to reset into the halted, state,
 832          * but resetting and halting is second best... */
 833         if (target->reset_halt)
 834         {
 835                 CHECK_RETVAL(target_halt(target));
 836         }
 837
 838
 839         /* srst is funny. We can not do *anything* else while it's asserted
 840          * and it has unkonwn side effects. Make sure no other code runs
 841          * meanwhile.
 842          *
 843          * Code below assumes srst:
 844          *
 845          * - Causes power-on-reset (but of what parts of the system?). Bug
 846          * in arm11?
 847          *
 848          * - Messes us TAP state without asserting trst.
 849          *
 850          * - There is another bug in the arm11 core. When you generate an access to
 851          * external logic (for example ddr controller via AHB bus) and that block
 852          * is not configured (perhaps it is still held in reset), that transaction
 853          * will never complete. This will hang arm11 core but it will also hang
 854          * JTAG controller. Nothing, short of srst assertion will bring it out of
 855          * this.
 856          *
 857          * Mysteries:
 858          *
 859          * - What should the PC be after an srst reset when starting in the halted
 860          * state?
 861          */
 862
 863         jtag_add_reset(0, 1);
 864         jtag_add_reset(0, 0);
 865
 866         /* How long do we have to wait? */
 867         jtag_add_sleep(5000);
 868
 869         /* un-mess up TAP state */
 870         jtag_add_tlr();
 871
 872         retval = jtag_execute_queue();
 873         if (retval != ERROR_OK)
 874         {
 875                 return retval;
 876         }
 877
 878         return ERROR_OK;
 879 }
 880
 881 static int arm11_deassert_reset(struct target *target)
 882 {
 883         return ERROR_OK;
 884 }
 885
 886 static int arm11_soft_reset_halt(struct target *target)
 887 {
 888         LOG_WARNING("Not implemented: %s", __func__);
 889
 890         return ERROR_FAIL;
 891 }
 892
 893 /* target memory access
 894  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
 895  * count: number of items of <size>
 896  *
 897  * arm11_config_memrw_no_increment - in the future we may want to be able
 898  * to read/write a range of data to a "port". a "port" is an action on
 899  * read memory address for some peripheral.
 900  */
 901 static int arm11_read_memory_inner(struct target *target,
 902                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
 903                 bool arm11_config_memrw_no_increment)
 904 {
 905         /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
 906         int retval;
 907
 908         if (target->state != TARGET_HALTED)
 909         {
 910                 LOG_WARNING("target was not halted");
 911                 return ERROR_TARGET_NOT_HALTED;
 912         }
 913
 914         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 915
 916         struct arm11_common *arm11 = target_to_arm11(target);
 917
 918         retval = arm11_run_instr_data_prepare(arm11);
 919         if (retval != ERROR_OK)
 920                 return retval;
 921
 922         /* MRC p14,0,r0,c0,c5,0 */
 923         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
 924         if (retval != ERROR_OK)
 925                 return retval;
 926
 927         switch (size)
 928         {
 929         case 1:
 930                 arm11->arm.core_cache->reg_list[1].dirty = true;
 931
 932                 for (size_t i = 0; i < count; i++)
 933                 {
 934                         /* ldrb    r1, [r0], #1 */
 935                         /* ldrb    r1, [r0] */
 936                         arm11_run_instr_no_data1(arm11,
 937                                         !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000);
 938
 939                         uint32_t res;
 940                         /* MCR p14,0,R1,c0,c5,0 */
 941                         arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 942
 943                         *buffer++ = res;
 944                 }
 945
 946                 break;
 947
 948         case 2:
 949                 {
 950                         arm11->arm.core_cache->reg_list[1].dirty = true;
 951
 952                         for (size_t i = 0; i < count; i++)
 953                         {
 954                                 /* ldrh    r1, [r0], #2 */
 955                                 arm11_run_instr_no_data1(arm11,
 956                                         !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0);
 957
 958                                 uint32_t res;
 959
 960                                 /* MCR p14,0,R1,c0,c5,0 */
 961                                 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
 962
 963                                 uint16_t svalue = res;
 964                                 memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
 965                         }
 966
 967                         break;
 968                 }
 969
 970         case 4:
 971                 {
 972                 uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
 973                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 974                 uint32_t *words = (uint32_t *)buffer;
 975
 976                 /* LDC p14,c5,[R0],#4 */
 977                 /* LDC p14,c5,[R0] */
 978                 arm11_run_instr_data_from_core(arm11, instr, words, count);
 979                 break;
 980                 }
 981         }
 982
 983         return arm11_run_instr_data_finish(arm11);
 984 }
 985
 986 static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 987 {
 988         return arm11_read_memory_inner(target, address, size, count, buffer, false);
 989 }
 990
 991 /*
 992 * no_increment - in the future we may want to be able
 993 * to read/write a range of data to a "port". a "port" is an action on
 994 * read memory address for some peripheral.
 995 */
 996 static int arm11_write_memory_inner(struct target *target,
 997                 uint32_t address, uint32_t size,
 998                 uint32_t count, uint8_t *buffer,
 999                 bool no_increment)
1000 {
1001         int retval;
1002
1003         if (target->state != TARGET_HALTED)
1004         {
1005                 LOG_WARNING("target was not halted");
1006                 return ERROR_TARGET_NOT_HALTED;
1007         }
1008
1009         LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
1010
1011         struct arm11_common *arm11 = target_to_arm11(target);
1012
1013         retval = arm11_run_instr_data_prepare(arm11);
1014         if (retval != ERROR_OK)
1015                 return retval;
1016
1017         /* MRC p14,0,r0,c0,c5,0 */
1018         retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1019         if (retval != ERROR_OK)
1020                 return retval;
1021
1022         /* burst writes are not used for single words as those may well be
1023          * reset init script writes.
1024          *
1025          * The other advantage is that as burst writes are default, we'll
1026          * now exercise both burst and non-burst code paths with the
1027          * default settings, increasing code coverage.
1028          */
1029         bool burst = arm11_config_memwrite_burst && (count > 1);
1030
1031         switch (size)
1032         {
1033         case 1:
1034                 {
1035                         arm11->arm.core_cache->reg_list[1].dirty = true;
1036
1037                         for (size_t i = 0; i < count; i++)
1038                         {
1039                                 /* MRC p14,0,r1,c0,c5,0 */
1040                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1041                                 if (retval != ERROR_OK)
1042                                         return retval;
1043
1044                                 /* strb    r1, [r0], #1 */
1045                                 /* strb    r1, [r0] */
1046                                 retval = arm11_run_instr_no_data1(arm11,
1047                                         !no_increment
1048                                                 ? 0xe4c01001
1049                                                 : 0xe5c01000);
1050                                 if (retval != ERROR_OK)
1051                                         return retval;
1052                         }
1053
1054                         break;
1055                 }
1056
1057         case 2:
1058                 {
1059                         arm11->arm.core_cache->reg_list[1].dirty = true;
1060
1061                         for (size_t i = 0; i < count; i++)
1062                         {
1063                                 uint16_t value;
1064                                 memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
1065
1066                                 /* MRC p14,0,r1,c0,c5,0 */
1067                                 retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
1068                                 if (retval != ERROR_OK)
1069                                         return retval;
1070
1071                                 /* strh    r1, [r0], #2 */
1072                                 /* strh    r1, [r0] */
1073                                 retval = arm11_run_instr_no_data1(arm11,
1074                                         !no_increment
1075                                                 ? 0xe0c010b2
1076                                                 : 0xe1c010b0);
1077                                 if (retval != ERROR_OK)
1078                                         return retval;
1079                         }
1080
1081                         break;
1082                 }
1083
1084         case 4: {
1085                 uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
1086
1087                 /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
1088                 uint32_t *words = (uint32_t*)buffer;
1089
1090                 if (!burst)
1091                 {
1092                         /* STC p14,c5,[R0],#4 */
1093                         /* STC p14,c5,[R0]*/
1094                         retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
1095                         if (retval != ERROR_OK)
1096                                 return retval;
1097                 }
1098                 else
1099                 {
1100                         /* STC p14,c5,[R0],#4 */
1101                         /* STC p14,c5,[R0]*/
1102                         retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
1103                         if (retval != ERROR_OK)
1104                                 return retval;
1105                 }
1106
1107                 break;
1108         }
1109         }
1110
1111         /* r0 verification */
1112         if (!no_increment)
1113         {
1114                 uint32_t r0;
1115
1116                 /* MCR p14,0,R0,c0,c5,0 */
1117                 retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1118                 if (retval != ERROR_OK)
1119                         return retval;
1120
1121                 if (address + size * count != r0)
1122                 {
1123                         LOG_ERROR("Data transfer failed. Expected end "
1124                                         "address 0x%08x, got 0x%08x",
1125                                         (unsigned) (address + size * count),
1126                                         (unsigned) r0);
1127
1128                         if (burst)
1129                                 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1130
1131                         if (arm11_config_memwrite_error_fatal)
1132                                 return ERROR_FAIL;
1133                 }
1134         }
1135
1136         return arm11_run_instr_data_finish(arm11);
1137 }
1138
1139 static int arm11_write_memory(struct target *target,
1140                 uint32_t address, uint32_t size,
1141                 uint32_t count, uint8_t *buffer)
1142 {
1143         /* pointer increment matters only for multi-unit writes ...
1144          * not e.g. to a "reset the chip" controller.
1145          */
1146         return arm11_write_memory_inner(target, address, size,
1147                         count, buffer, count == 1);
1148 }
1149
1150 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1151 static int arm11_bulk_write_memory(struct target *target,
1152                 uint32_t address, uint32_t count, uint8_t *buffer)
1153 {
1154         if (target->state != TARGET_HALTED)
1155         {
1156                 LOG_WARNING("target was not halted");
1157                 return ERROR_TARGET_NOT_HALTED;
1158         }
1159
1160         return arm11_write_memory(target, address, 4, count, buffer);
1161 }
1162
1163 /* target break-/watchpoint control
1164 * rw: 0 = write, 1 = read, 2 = access
1165 */
1166 static int arm11_add_breakpoint(struct target *target,
1167                 struct breakpoint *breakpoint)
1168 {
1169         struct arm11_common *arm11 = target_to_arm11(target);
1170
1171 #if 0
1172         if (breakpoint->type == BKPT_SOFT)
1173         {
1174                 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1175                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1176         }
1177 #endif
1178
1179         if (!arm11->free_brps)
1180         {
1181                 LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
1182                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1183         }
1184
1185         if (breakpoint->length != 4)
1186         {
1187                 LOG_DEBUG("only breakpoints of four bytes length supported");
1188                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1189         }
1190
1191         arm11->free_brps--;
1192
1193         return ERROR_OK;
1194 }
1195
1196 static int arm11_remove_breakpoint(struct target *target,
1197                 struct breakpoint *breakpoint)
1198 {
1199         struct arm11_common *arm11 = target_to_arm11(target);
1200
1201         arm11->free_brps++;
1202
1203         return ERROR_OK;
1204 }
1205
1206 static int arm11_target_create(struct target *target, Jim_Interp *interp)
1207 {
1208         struct arm11_common *arm11;
1209
1210         if (target->tap == NULL)
1211                 return ERROR_FAIL;
1212
1213         if (target->tap->ir_length != 5)
1214         {
1215                 LOG_ERROR("'target arm11' expects IR LENGTH = 5");
1216                 return ERROR_COMMAND_SYNTAX_ERROR;
1217         }
1218
1219         arm11 = calloc(1, sizeof *arm11);
1220         if (!arm11)
1221                 return ERROR_FAIL;
1222
1223         armv4_5_init_arch_info(target, &arm11->arm);
1224
1225         arm11->jtag_info.tap = target->tap;
1226         arm11->jtag_info.scann_size = 5;
1227         arm11->jtag_info.scann_instr = ARM11_SCAN_N;
1228         /* cur_scan_chain == 0 */
1229         arm11->jtag_info.intest_instr = ARM11_INTEST;
1230
1231         return ERROR_OK;
1232 }
1233
1234 static int arm11_init_target(struct command_context *cmd_ctx,
1235                 struct target *target)
1236 {
1237         /* Initialize anything we can set up without talking to the target */
1238
1239         /* REVISIT do we really want such a debug-registers-only cache?
1240          * If we do, it should probably be handled purely by the DPM code,
1241          * so it works identically on the v7a/v7r cores.
1242          */
1243         return arm11_build_reg_cache(target);
1244 }
1245
1246 /* talk to the target and set things up */
1247 static int arm11_examine(struct target *target)
1248 {
1249         int retval;
1250         char *type;
1251         struct arm11_common *arm11 = target_to_arm11(target);
1252         uint32_t didr, device_id;
1253         uint8_t implementor;
1254
1255         /* FIXME split into do-first-time and do-every-time logic ... */
1256
1257         /* check IDCODE */
1258
1259         arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
1260
1261         struct scan_field               idcode_field;
1262
1263         arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
1264
1265         arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
1266
1267         /* check DIDR */
1268
1269         arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
1270
1271         arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
1272
1273         struct scan_field               chain0_fields[2];
1274
1275         arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
1276         arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
1277
1278         arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
1279
1280         CHECK_RETVAL(jtag_execute_queue());
1281
1282         switch (device_id & 0x0FFFF000)
1283         {
1284         case 0x07B36000:
1285                 type = "ARM1136";
1286                 break;
1287         case 0x07B56000:
1288                 type = "ARM1156";
1289                 break;
1290         case 0x07B76000:
1291                 arm11->arm.core_type = ARM_MODE_MON;
1292                 type = "ARM1176";
1293                 break;
1294         default:
1295                 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1296                 return ERROR_FAIL;
1297         }
1298         LOG_INFO("found %s", type);
1299
1300         /* unlikely this could ever fail, but ... */
1301         switch ((didr >> 16) & 0x0F) {
1302         case ARM11_DEBUG_V6:
1303         case ARM11_DEBUG_V61:           /* supports security extensions */
1304                 break;
1305         default:
1306                 LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
1307                 return ERROR_FAIL;
1308         }
1309
1310         arm11->brp = ((didr >> 24) & 0x0F) + 1;
1311         arm11->wrp = ((didr >> 28) & 0x0F) + 1;
1312
1313         /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1314         arm11->free_brps = arm11->brp;
1315
1316         LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
1317                         device_id, implementor, didr);
1318
1319         /* as a side-effect this reads DSCR and thus
1320          * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1321          * as suggested by the spec.
1322          */
1323
1324         retval = arm11_check_init(arm11, NULL);
1325         if (retval != ERROR_OK)
1326                 return retval;
1327
1328         /* Build register cache "late", after target_init(), since we
1329          * want to know if this core supports Secure Monitor mode.
1330          */
1331         if (!target_was_examined(target))
1332                 retval = arm11_dpm_init(arm11, didr);
1333
1334         /* ETM on ARM11 still uses original scanchain 6 access mode */
1335         if (arm11->arm.etm && !target_was_examined(target)) {
1336                 *register_get_last_cache_p(&target->reg_cache) =
1337                         etm_build_reg_cache(target, &arm11->jtag_info,
1338                                         arm11->arm.etm);
1339                 retval = etm_setup(target);
1340         }
1341
1342         target_set_examined(target);
1343
1344         return ERROR_OK;
1345 }
1346
1347
1348 /** Load a register that is marked !valid in the register cache */
1349 static int arm11_get_reg(struct reg *reg)
1350 {
1351         struct arm11_reg_state *r = reg->arch_info;
1352         struct target *target = r->target;
1353
1354         if (target->state != TARGET_HALTED)
1355         {
1356                 LOG_WARNING("target was not halted");
1357                 return ERROR_TARGET_NOT_HALTED;
1358         }
1359
1360         /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1361
1362 #if 0
1363         struct arm11_common *arm11 = target_to_arm11(target);
1364         const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1365 #endif
1366
1367         return ERROR_OK;
1368 }
1369
1370 /** Change a value in the register cache */
1371 static int arm11_set_reg(struct reg *reg, uint8_t *buf)
1372 {
1373         struct arm11_reg_state *r = reg->arch_info;
1374         struct target *target = r->target;
1375         struct arm11_common *arm11 = target_to_arm11(target);
1376 //      const struct arm11_reg_defs *arm11_reg_info = arm11_reg_defs + ((struct arm11_reg_state *)reg->arch_info)->def_index;
1377
1378         arm11->reg_values[((struct arm11_reg_state *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1379         reg->valid      = 1;
1380         reg->dirty      = 1;
1381
1382         return ERROR_OK;
1383 }
1384
1385 static const struct reg_arch_type arm11_reg_type = {
1386         .get = arm11_get_reg,
1387         .set = arm11_set_reg,
1388 };
1389
1390 static int arm11_build_reg_cache(struct target *target)
1391 {
1392         struct arm11_common *arm11 = target_to_arm11(target);
1393         struct reg_cache *cache;
1394         struct reg *reg_list;
1395         struct arm11_reg_state *arm11_reg_states;
1396
1397         cache = calloc(1, sizeof *cache);
1398         reg_list = calloc(ARM11_REGCACHE_COUNT, sizeof *reg_list);
1399         arm11_reg_states = calloc(ARM11_REGCACHE_COUNT,
1400                         sizeof *arm11_reg_states);
1401         if (!cache || !reg_list || !arm11_reg_states) {
1402                 free(cache);
1403                 free(reg_list);
1404                 free(arm11_reg_states);
1405                 return ERROR_FAIL;
1406         }
1407
1408         arm11->reg_list = reg_list;
1409
1410         /* build cache for some of the debug registers */
1411         cache->name = "arm11 debug registers";
1412         cache->reg_list = reg_list;
1413         cache->num_regs = ARM11_REGCACHE_COUNT;
1414
1415         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
1416         (*cache_p) = cache;
1417
1418         arm11->core_cache = cache;
1419
1420         size_t i;
1421
1422         /* Not very elegant assertion */
1423         if (ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11->reg_values) ||
1424                 ARM11_REGCACHE_COUNT != ARRAY_SIZE(arm11_reg_defs) ||
1425                 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1426         {
1427                 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d %u %u %d)",
1428                                 ARM11_REGCACHE_COUNT,
1429                                 (unsigned) ARRAY_SIZE(arm11->reg_values),
1430                                 (unsigned) ARRAY_SIZE(arm11_reg_defs),
1431                                 ARM11_RC_MAX);
1432                 /* FIXME minimally, use a build_bug_on(X) mechanism;
1433                  * runtime exit() here is bad!
1434                  */
1435                 exit(-1);
1436         }
1437
1438         for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1439         {
1440                 struct reg *                                            r       = reg_list                      + i;
1441                 const struct arm11_reg_defs *   rd      = arm11_reg_defs        + i;
1442                 struct arm11_reg_state *                        rs      = arm11_reg_states      + i;
1443
1444                 r->name                         = rd->name;
1445                 r->size                         = 32;
1446                 r->value                        = (uint8_t *)(arm11->reg_values + i);
1447                 r->dirty                        = 0;
1448                 r->valid                        = 0;
1449                 r->type = &arm11_reg_type;
1450                 r->arch_info            = rs;
1451
1452                 rs->def_index           = i;
1453                 rs->target                      = target;
1454         }
1455
1456         return ERROR_OK;
1457 }
1458
1459 /* FIXME all these BOOL_WRAPPER things should be modifying
1460  * per-instance state, not shared state; ditto the vector
1461  * catch register support.  Scan chains with multiple cores
1462  * should be able to say "work with this core like this,
1463  * that core like that".  Example, ARM11 MPCore ...
1464  */
1465
1466 #define ARM11_BOOL_WRAPPER(name, print_name)    \
1467                 COMMAND_HANDLER(arm11_handle_bool_##name) \
1468                 { \
1469                         return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
1470                                         &arm11_config_##name, print_name); \
1471                 }
1472
1473 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1474 ARM11_BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1475 ARM11_BOOL_WRAPPER(step_irq_enable, "IRQs while stepping")
1476 ARM11_BOOL_WRAPPER(hardware_step, "hardware single step")
1477
1478 COMMAND_HANDLER(arm11_handle_vcr)
1479 {
1480         switch (CMD_ARGC) {
1481         case 0:
1482                 break;
1483         case 1:
1484                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11_vcr);
1485                 break;
1486         default:
1487                 return ERROR_COMMAND_SYNTAX_ERROR;
1488         }
1489
1490         LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
1491         return ERROR_OK;
1492 }
1493
1494 static const struct command_registration arm11_mw_command_handlers[] = {
1495         {
1496                 .name = "burst",
1497                 .handler = &arm11_handle_bool_memwrite_burst,
1498                 .mode = COMMAND_ANY,
1499                 .help = "Enable/Disable non-standard but fast burst mode"
1500                         " (default: enabled)",
1501         },
1502         {
1503                 .name = "error_fatal",
1504                 .handler = &arm11_handle_bool_memwrite_error_fatal,
1505                 .mode = COMMAND_ANY,
1506                 .help = "Terminate program if transfer error was found"
1507                         " (default: enabled)",
1508         },
1509         COMMAND_REGISTRATION_DONE
1510 };
1511 static const struct command_registration arm11_any_command_handlers[] = {
1512         {
1513                 /* "hardware_step" is only here to check if the default
1514                  * simulate + breakpoint implementation is broken.
1515                  * TEMPORARY! NOT DOCUMENTED! */
1516                 .name = "hardware_step",
1517                 .handler = &arm11_handle_bool_hardware_step,
1518                 .mode = COMMAND_ANY,
1519                 .help = "DEBUG ONLY - Hardware single stepping"
1520                         " (default: disabled)",
1521                 .usage = "(enable|disable)",
1522         },
1523         {
1524                 .name = "memwrite",
1525                 .mode = COMMAND_ANY,
1526                 .help = "memwrite command group",
1527                 .chain = arm11_mw_command_handlers,
1528         },
1529         {
1530                 .name = "step_irq_enable",
1531                 .handler = &arm11_handle_bool_step_irq_enable,
1532                 .mode = COMMAND_ANY,
1533                 .help = "Enable interrupts while stepping"
1534                         " (default: disabled)",
1535         },
1536         {
1537                 .name = "vcr",
1538                 .handler = &arm11_handle_vcr,
1539                 .mode = COMMAND_ANY,
1540                 .help = "Control (Interrupt) Vector Catch Register",
1541         },
1542         COMMAND_REGISTRATION_DONE
1543 };
1544 static const struct command_registration arm11_command_handlers[] = {
1545         {
1546                 .chain = arm_command_handlers,
1547         },
1548         {
1549                 .chain = etm_command_handlers,
1550         },
1551         {
1552                 .name = "arm11",
1553                 .mode = COMMAND_ANY,
1554                 .help = "ARM11 command group",
1555                 .chain = arm11_any_command_handlers,
1556         },
1557         COMMAND_REGISTRATION_DONE
1558 };
1559
1560 /** Holds methods for ARM11xx targets. */
1561 struct target_type arm11_target = {
1562         .name =                 "arm11",
1563
1564         .poll =                 arm11_poll,
1565         .arch_state =           arm11_arch_state,
1566
1567         .target_request_data =  arm11_target_request_data,
1568
1569         .halt =                 arm11_halt,
1570         .resume =               arm11_resume,
1571         .step =                 arm11_step,
1572
1573         .assert_reset =         arm11_assert_reset,
1574         .deassert_reset =       arm11_deassert_reset,
1575         .soft_reset_halt =      arm11_soft_reset_halt,
1576
1577         .get_gdb_reg_list =     armv4_5_get_gdb_reg_list,
1578
1579         .read_memory =          arm11_read_memory,
1580         .write_memory =         arm11_write_memory,
1581
1582         .bulk_write_memory =    arm11_bulk_write_memory,
1583
1584         .checksum_memory =      arm_checksum_memory,
1585         .blank_check_memory =   arm_blank_check_memory,
1586
1587         .add_breakpoint =       arm11_add_breakpoint,
1588         .remove_breakpoint =    arm11_remove_breakpoint,
1589
1590         .run_algorithm =        armv4_5_run_algorithm,
1591
1592         .commands =             arm11_command_handlers,
1593         .target_create =        arm11_target_create,
1594         .init_target =          arm11_init_target,
1595         .examine =              arm11_examine,
1596 };