1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
36 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #define FNC_INFO LOG_DEBUG("-")
47 #define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
49 #define FNC_INFO_NOTIMPLEMENTED
52 static void arm11_on_enter_debug_state(arm11_common_t * arm11);
55 bool arm11_config_memwrite_burst = true;
56 bool arm11_config_memwrite_error_fatal = true;
60 #define ARM11_HANDLER(x) \
63 target_type_t arm11_target =
68 ARM11_HANDLER(arch_state),
70 ARM11_HANDLER(target_request_data),
73 ARM11_HANDLER(resume),
76 ARM11_HANDLER(assert_reset),
77 ARM11_HANDLER(deassert_reset),
78 ARM11_HANDLER(soft_reset_halt),
80 ARM11_HANDLER(get_gdb_reg_list),
82 ARM11_HANDLER(read_memory),
83 ARM11_HANDLER(write_memory),
85 ARM11_HANDLER(bulk_write_memory),
87 ARM11_HANDLER(checksum_memory),
89 ARM11_HANDLER(add_breakpoint),
90 ARM11_HANDLER(remove_breakpoint),
91 ARM11_HANDLER(add_watchpoint),
92 ARM11_HANDLER(remove_watchpoint),
94 ARM11_HANDLER(run_algorithm),
96 ARM11_HANDLER(register_commands),
97 ARM11_HANDLER(target_create),
98 ARM11_HANDLER(init_target),
99 ARM11_HANDLER(examine),
103 int arm11_regs_arch_type = -1;
121 ARM11_REGISTER_SPSR_FIQ,
122 ARM11_REGISTER_SPSR_SVC,
123 ARM11_REGISTER_SPSR_ABT,
124 ARM11_REGISTER_SPSR_IRQ,
125 ARM11_REGISTER_SPSR_UND,
126 ARM11_REGISTER_SPSR_MON,
135 typedef struct arm11_reg_defs_s
140 enum arm11_regtype type;
143 /* update arm11_regcache_ids when changing this */
144 static const arm11_reg_defs_t arm11_reg_defs[] =
146 {"r0", 0, 0, ARM11_REGISTER_CORE},
147 {"r1", 1, 1, ARM11_REGISTER_CORE},
148 {"r2", 2, 2, ARM11_REGISTER_CORE},
149 {"r3", 3, 3, ARM11_REGISTER_CORE},
150 {"r4", 4, 4, ARM11_REGISTER_CORE},
151 {"r5", 5, 5, ARM11_REGISTER_CORE},
152 {"r6", 6, 6, ARM11_REGISTER_CORE},
153 {"r7", 7, 7, ARM11_REGISTER_CORE},
154 {"r8", 8, 8, ARM11_REGISTER_CORE},
155 {"r9", 9, 9, ARM11_REGISTER_CORE},
156 {"r10", 10, 10, ARM11_REGISTER_CORE},
157 {"r11", 11, 11, ARM11_REGISTER_CORE},
158 {"r12", 12, 12, ARM11_REGISTER_CORE},
159 {"sp", 13, 13, ARM11_REGISTER_CORE},
160 {"lr", 14, 14, ARM11_REGISTER_CORE},
161 {"pc", 15, 15, ARM11_REGISTER_CORE},
163 #if ARM11_REGCACHE_FREGS
164 {"f0", 0, 16, ARM11_REGISTER_FX},
165 {"f1", 1, 17, ARM11_REGISTER_FX},
166 {"f2", 2, 18, ARM11_REGISTER_FX},
167 {"f3", 3, 19, ARM11_REGISTER_FX},
168 {"f4", 4, 20, ARM11_REGISTER_FX},
169 {"f5", 5, 21, ARM11_REGISTER_FX},
170 {"f6", 6, 22, ARM11_REGISTER_FX},
171 {"f7", 7, 23, ARM11_REGISTER_FX},
172 {"fps", 0, 24, ARM11_REGISTER_FPS},
175 {"cpsr", 0, 25, ARM11_REGISTER_CPSR},
177 #if ARM11_REGCACHE_MODEREGS
178 {"r8_fiq", 8, -1, ARM11_REGISTER_FIQ},
179 {"r9_fiq", 9, -1, ARM11_REGISTER_FIQ},
180 {"r10_fiq", 10, -1, ARM11_REGISTER_FIQ},
181 {"r11_fiq", 11, -1, ARM11_REGISTER_FIQ},
182 {"r12_fiq", 12, -1, ARM11_REGISTER_FIQ},
183 {"r13_fiq", 13, -1, ARM11_REGISTER_FIQ},
184 {"r14_fiq", 14, -1, ARM11_REGISTER_FIQ},
185 {"spsr_fiq", 0, -1, ARM11_REGISTER_SPSR_FIQ},
187 {"r13_svc", 13, -1, ARM11_REGISTER_SVC},
188 {"r14_svc", 14, -1, ARM11_REGISTER_SVC},
189 {"spsr_svc", 0, -1, ARM11_REGISTER_SPSR_SVC},
191 {"r13_abt", 13, -1, ARM11_REGISTER_ABT},
192 {"r14_abt", 14, -1, ARM11_REGISTER_ABT},
193 {"spsr_abt", 0, -1, ARM11_REGISTER_SPSR_ABT},
195 {"r13_irq", 13, -1, ARM11_REGISTER_IRQ},
196 {"r14_irq", 14, -1, ARM11_REGISTER_IRQ},
197 {"spsr_irq", 0, -1, ARM11_REGISTER_SPSR_IRQ},
199 {"r13_und", 13, -1, ARM11_REGISTER_UND},
200 {"r14_und", 14, -1, ARM11_REGISTER_UND},
201 {"spsr_und", 0, -1, ARM11_REGISTER_SPSR_UND},
204 {"r13_mon", 13, -1, ARM11_REGISTER_MON},
205 {"r14_mon", 14, -1, ARM11_REGISTER_MON},
206 {"spsr_mon", 0, -1, ARM11_REGISTER_SPSR_MON},
209 /* Debug Registers */
210 {"dscr", 0, -1, ARM11_REGISTER_DSCR},
211 {"wdtr", 0, -1, ARM11_REGISTER_WDTR},
212 {"rdtr", 0, -1, ARM11_REGISTER_RDTR},
215 enum arm11_regcache_ids
218 ARM11_RC_RX = ARM11_RC_R0,
233 ARM11_RC_SP = ARM11_RC_R13,
235 ARM11_RC_LR = ARM11_RC_R14,
237 ARM11_RC_PC = ARM11_RC_R15,
239 #if ARM11_REGCACHE_FREGS
241 ARM11_RC_FX = ARM11_RC_F0,
254 #if ARM11_REGCACHE_MODEREGS
292 #define ARM11_GDB_REGISTER_COUNT 26
294 u8 arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
296 reg_t arm11_gdb_dummy_fp_reg =
298 "GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
301 u8 arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
303 reg_t arm11_gdb_dummy_fps_reg =
305 "GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
310 /** Check and if necessary take control of the system
312 * \param arm11 Target state variable.
313 * \param dscr If the current DSCR content is
314 * available a pointer to a word holding the
315 * DSCR can be passed. Otherwise use NULL.
317 void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
321 u32 dscr_local_tmp_copy;
325 dscr = &dscr_local_tmp_copy;
326 *dscr = arm11_read_DSCR(arm11);
329 if (!(*dscr & ARM11_DSCR_MODE_SELECT))
331 LOG_DEBUG("Bringing target into debug mode");
333 *dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
334 arm11_write_DSCR(arm11, *dscr);
336 /* add further reset initialization here */
338 arm11->simulate_reset_on_next_halt = true;
340 if (*dscr & ARM11_DSCR_CORE_HALTED)
342 /** \todo TODO: this needs further scrutiny because
343 * arm11_on_enter_debug_state() never gets properly called
346 arm11->target->state = TARGET_HALTED;
347 arm11->target->debug_reason = arm11_get_DSCR_debug_reason(*dscr);
351 arm11->target->state = TARGET_RUNNING;
352 arm11->target->debug_reason = DBG_REASON_NOTHALTED;
355 arm11_sc7_clear_vbw(arm11);
362 (arm11->reg_values[ARM11_RC_##x])
364 /** Save processor state.
366 * This is called when the HALT instruction has succeeded
367 * or on other occasions that stop the processor.
370 static void arm11_on_enter_debug_state(arm11_common_t * arm11)
375 for(i = 0; i < asizeof(arm11->reg_values); i++)
377 arm11->reg_list[i].valid = 1;
378 arm11->reg_list[i].dirty = 0;
383 R(DSCR) = arm11_read_DSCR(arm11);
387 if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
389 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
391 arm11_add_IR(arm11, ARM11_INTEST, -1);
393 scan_field_t chain5_fields[3];
395 arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
396 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
397 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
399 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
403 arm11->reg_list[ARM11_RC_WDTR].valid = 0;
407 /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE */
408 /* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode", but not to issue ITRs
409 ARM1136 seems to require this to issue ITR's as well */
411 u32 new_dscr = R(DSCR) | ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE;
413 /* this executes JTAG queue: */
415 arm11_write_DSCR(arm11, new_dscr);
419 Before executing any instruction in debug state you have to drain the write buffer.
420 This ensures that no imprecise Data Aborts can return at a later point:*/
422 /** \todo TODO: Test drain write buffer. */
427 /* MRC p14,0,R0,c5,c10,0 */
428 // arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
430 /* mcr 15, 0, r0, cr7, cr10, {4} */
431 arm11_run_instr_no_data1(arm11, 0xee070f9a);
433 u32 dscr = arm11_read_DSCR(arm11);
435 LOG_DEBUG("DRAIN, DSCR %08x", dscr);
437 if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
439 arm11_run_instr_no_data1(arm11, 0xe320f000);
441 dscr = arm11_read_DSCR(arm11);
443 LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
451 arm11_run_instr_data_prepare(arm11);
456 /** \todo TODO: handle other mode registers */
459 for (i = 0; i < 15; i++)
461 /* MCR p14,0,R?,c0,c5,0 */
462 arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
468 /* check rDTRfull in DSCR */
470 if (R(DSCR) & ARM11_DSCR_RDTR_FULL)
472 /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
473 arm11_run_instr_data_from_core_via_r0(arm11, 0xEE100E15, &R(RDTR));
477 arm11->reg_list[ARM11_RC_RDTR].valid = 0;
482 /* MRS r0,CPSR (move CPSR -> r0 (-> wDTR -> local var)) */
483 arm11_run_instr_data_from_core_via_r0(arm11, 0xE10F0000, &R(CPSR));
487 /* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
488 arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
490 /* adjust PC depending on ARM state */
492 if (R(CPSR) & ARM11_CPSR_J) /* Java state */
494 arm11->reg_values[ARM11_RC_PC] -= 0;
496 else if (R(CPSR) & ARM11_CPSR_T) /* Thumb state */
498 arm11->reg_values[ARM11_RC_PC] -= 4;
502 arm11->reg_values[ARM11_RC_PC] -= 8;
505 if (arm11->simulate_reset_on_next_halt)
507 arm11->simulate_reset_on_next_halt = false;
509 LOG_DEBUG("Reset c1 Control Register");
511 /* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
513 /* MCR p15,0,R0,c1,c0,0 */
514 arm11_run_instr_data_to_core_via_r0(arm11, 0xee010f10, 0);
518 arm11_run_instr_data_finish(arm11);
520 arm11_dump_reg_changes(arm11);
523 void arm11_dump_reg_changes(arm11_common_t * arm11)
526 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
528 if (!arm11->reg_list[i].valid)
530 if (arm11->reg_history[i].valid)
531 LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
535 if (arm11->reg_history[i].valid)
537 if (arm11->reg_history[i].value != arm11->reg_values[i])
538 LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
542 LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
549 /** Restore processor state
551 * This is called in preparation for the RESTART function.
554 void arm11_leave_debug_state(arm11_common_t * arm11)
558 arm11_run_instr_data_prepare(arm11);
560 /** \todo TODO: handle other mode registers */
562 /* restore R1 - R14 */
564 for (i = 1; i < 15; i++)
566 if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
569 /* MRC p14,0,r?,c0,c5,0 */
570 arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
572 // LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
575 arm11_run_instr_data_finish(arm11);
578 /* spec says clear wDTR and rDTR; we assume they are clear as
579 otherwise our programming would be sloppy */
582 u32 DSCR = arm11_read_DSCR(arm11);
584 if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
586 LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
590 arm11_run_instr_data_prepare(arm11);
592 /* restore original wDTR */
594 if ((R(DSCR) & ARM11_DSCR_WDTR_FULL) || arm11->reg_list[ARM11_RC_WDTR].dirty)
596 /* MCR p14,0,R0,c0,c5,0 */
597 arm11_run_instr_data_to_core_via_r0(arm11, 0xee000e15, R(WDTR));
603 arm11_run_instr_data_to_core_via_r0(arm11, 0xe129f000, R(CPSR));
609 arm11_run_instr_data_to_core_via_r0(arm11, 0xe1a0f000, R(PC));
614 /* MRC p14,0,r0,c0,c5,0 */
615 arm11_run_instr_data_to_core1(arm11, 0xee100e15, R(R0));
617 arm11_run_instr_data_finish(arm11);
622 arm11_write_DSCR(arm11, R(DSCR));
627 if (R(DSCR) & ARM11_DSCR_RDTR_FULL || arm11->reg_list[ARM11_RC_RDTR].dirty)
629 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
631 arm11_add_IR(arm11, ARM11_EXTEST, -1);
633 scan_field_t chain5_fields[3];
635 u8 Ready = 0; /* ignored */
636 u8 Valid = 0; /* ignored */
638 arm11_setup_field(arm11, 32, &R(RDTR), NULL, chain5_fields + 0);
639 arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
640 arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
642 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
645 arm11_record_register_history(arm11);
648 void arm11_record_register_history(arm11_common_t * arm11)
651 for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
653 arm11->reg_history[i].value = arm11->reg_values[i];
654 arm11->reg_history[i].valid = arm11->reg_list[i].valid;
656 arm11->reg_list[i].valid = 0;
657 arm11->reg_list[i].dirty = 0;
662 /* poll current target status */
663 int arm11_poll(struct target_s *target)
667 arm11_common_t * arm11 = target->arch_info;
669 if (arm11->trst_active)
672 u32 dscr = arm11_read_DSCR(arm11);
674 LOG_DEBUG("DSCR %08x", dscr);
676 arm11_check_init(arm11, &dscr);
678 if (dscr & ARM11_DSCR_CORE_HALTED)
680 if (target->state != TARGET_HALTED)
682 enum target_state old_state = target->state;
684 LOG_DEBUG("enter TARGET_HALTED");
685 target->state = TARGET_HALTED;
686 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
687 arm11_on_enter_debug_state(arm11);
689 target_call_event_callbacks(target,
690 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
695 if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
697 LOG_DEBUG("enter TARGET_RUNNING");
698 target->state = TARGET_RUNNING;
699 target->debug_reason = DBG_REASON_NOTHALTED;
705 /* architecture specific status reply */
706 int arm11_arch_state(struct target_s *target)
708 FNC_INFO_NOTIMPLEMENTED;
714 /* target request support */
715 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer)
717 FNC_INFO_NOTIMPLEMENTED;
724 /* target execution control */
725 int arm11_halt(struct target_s *target)
729 arm11_common_t * arm11 = target->arch_info;
731 LOG_DEBUG("target->state: %s",
732 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
734 if (target->state == TARGET_UNKNOWN)
736 arm11->simulate_reset_on_next_halt = true;
739 if (target->state == TARGET_HALTED)
741 LOG_DEBUG("target was already halted");
745 if (arm11->trst_active)
747 arm11->halt_requested = true;
751 arm11_add_IR(arm11, ARM11_HALT, TAP_RTI);
753 jtag_execute_queue();
759 dscr = arm11_read_DSCR(arm11);
761 if (dscr & ARM11_DSCR_CORE_HALTED)
765 arm11_on_enter_debug_state(arm11);
767 enum target_state old_state = target->state;
769 target->state = TARGET_HALTED;
770 target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
772 target_call_event_callbacks(target,
773 old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);
779 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
783 // LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
784 // current, address, handle_breakpoints, debug_execution);
786 arm11_common_t * arm11 = target->arch_info;
788 LOG_DEBUG("target->state: %s",
789 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
792 if (target->state != TARGET_HALTED)
794 LOG_ERROR("Target not halted");
795 return ERROR_TARGET_NOT_HALTED;
801 LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
803 /* clear breakpoints/watchpoints and VCR*/
804 arm11_sc7_clear_vbw(arm11);
806 /* Set up breakpoints */
807 if (!debug_execution)
809 /* check if one matches PC and step over it if necessary */
813 for (bp = target->breakpoints; bp; bp = bp->next)
815 if (bp->address == R(PC))
817 LOG_DEBUG("must step over %08x", bp->address);
818 arm11_step(target, 1, 0, 0);
823 /* set all breakpoints */
827 for (bp = target->breakpoints; bp; bp = bp->next)
829 arm11_sc7_action_t brp[2];
832 brp[0].address = ARM11_SC7_BVR0 + brp_num;
833 brp[0].value = bp->address;
835 brp[1].address = ARM11_SC7_BCR0 + brp_num;
836 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
838 arm11_sc7_run(arm11, brp, asizeof(brp));
840 LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
845 arm11_sc7_set_vcr(arm11, arm11_vcr);
849 arm11_leave_debug_state(arm11);
851 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
853 jtag_execute_queue();
857 u32 dscr = arm11_read_DSCR(arm11);
859 LOG_DEBUG("DSCR %08x", dscr);
861 if (dscr & ARM11_DSCR_CORE_RESTARTED)
865 if (!debug_execution)
867 target->state = TARGET_RUNNING;
868 target->debug_reason = DBG_REASON_NOTHALTED;
869 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
873 target->state = TARGET_DEBUG_RUNNING;
874 target->debug_reason = DBG_REASON_NOTHALTED;
875 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
881 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
885 LOG_DEBUG("target->state: %s",
886 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
888 if (target->state != TARGET_HALTED)
890 LOG_WARNING("target was not halted");
891 return ERROR_TARGET_NOT_HALTED;
894 arm11_common_t * arm11 = target->arch_info;
899 LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
901 /** \todo TODO: Thumb not supported here */
903 u32 next_instruction;
905 arm11_read_memory_word(arm11, R(PC), &next_instruction);
908 if ((next_instruction & 0xFFF00070) == 0xe1200070)
911 arm11->reg_list[ARM11_RC_PC].valid = 1;
912 arm11->reg_list[ARM11_RC_PC].dirty = 0;
913 LOG_INFO("Skipping BKPT");
915 /* skip over Wait for interrupt / Standby */
916 /* mcr 15, 0, r?, cr7, cr0, {4} */
917 else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
920 arm11->reg_list[ARM11_RC_PC].valid = 1;
921 arm11->reg_list[ARM11_RC_PC].dirty = 0;
922 LOG_INFO("Skipping WFI");
924 /* ignore B to self */
925 else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
927 LOG_INFO("Not stepping jump to self");
931 /** \todo TODO: check if break-/watchpoints make any sense at all in combination
934 /** \todo TODO: check if disabling IRQs might be a good idea here. Alternatively
935 * the VCR might be something worth looking into. */
938 /* Set up breakpoint for stepping */
940 arm11_sc7_action_t brp[2];
943 brp[0].address = ARM11_SC7_BVR0;
944 brp[0].value = R(PC);
946 brp[1].address = ARM11_SC7_BCR0;
947 brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
949 arm11_sc7_run(arm11, brp, asizeof(brp));
953 arm11_leave_debug_state(arm11);
955 arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI);
957 jtag_execute_queue();
959 /** \todo TODO: add a timeout */
965 u32 dscr = arm11_read_DSCR(arm11);
967 LOG_DEBUG("DSCR %08x", dscr);
969 if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
970 (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
974 /* clear breakpoint */
975 arm11_sc7_clear_vbw(arm11);
978 arm11_on_enter_debug_state(arm11);
981 // target->state = TARGET_HALTED;
982 target->debug_reason = DBG_REASON_SINGLESTEP;
984 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
990 /* target reset control */
991 int arm11_assert_reset(struct target_s *target)
996 /* assert reset lines */
997 /* resets only the DBGTAP, not the ARM */
999 jtag_add_reset(1, 0);
1000 jtag_add_sleep(5000);
1002 arm11_common_t * arm11 = target->arch_info;
1003 arm11->trst_active = true;
1006 if (target->reset_halt)
1009 if ((retval = target_halt(target))!=ERROR_OK)
1016 int arm11_deassert_reset(struct target_s *target)
1021 LOG_DEBUG("target->state: %s",
1022 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
1025 /* deassert reset lines */
1026 jtag_add_reset(0, 0);
1028 arm11_common_t * arm11 = target->arch_info;
1029 arm11->trst_active = false;
1031 if (arm11->halt_requested)
1032 return arm11_halt(target);
1038 int arm11_soft_reset_halt(struct target_s *target)
1040 FNC_INFO_NOTIMPLEMENTED;
1047 /* target register access for gdb */
1048 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size)
1052 arm11_common_t * arm11 = target->arch_info;
1054 *reg_list_size = ARM11_GDB_REGISTER_COUNT;
1055 *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
1058 for (i = 16; i < 24; i++)
1060 (*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
1063 (*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
1067 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1069 if (arm11_reg_defs[i].gdb_num == -1)
1072 (*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
1079 /* target memory access
1080 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
1081 * count: number of items of <size>
1083 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1085 /** \todo TODO: check if buffer cast to u32* and u16* might cause alignment problems */
1089 if (target->state != TARGET_HALTED)
1091 LOG_WARNING("target was not halted");
1092 return ERROR_TARGET_NOT_HALTED;
1095 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1097 arm11_common_t * arm11 = target->arch_info;
1099 arm11_run_instr_data_prepare(arm11);
1101 /* MRC p14,0,r0,c0,c5,0 */
1102 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1107 /** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
1108 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1111 for (i = 0; i < count; i++)
1113 /* ldrb r1, [r0], #1 */
1114 arm11_run_instr_no_data1(arm11, 0xe4d01001);
1117 /* MCR p14,0,R1,c0,c5,0 */
1118 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1127 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1129 u16 * buf16 = (u16*)buffer;
1132 for (i = 0; i < count; i++)
1134 /* ldrh r1, [r0], #2 */
1135 arm11_run_instr_no_data1(arm11, 0xe0d010b2);
1139 /* MCR p14,0,R1,c0,c5,0 */
1140 arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
1150 /* LDC p14,c5,[R0],#4 */
1151 arm11_run_instr_data_from_core(arm11, 0xecb05e01, (u32 *)buffer, count);
1155 arm11_run_instr_data_finish(arm11);
1160 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1164 if (target->state != TARGET_HALTED)
1166 LOG_WARNING("target was not halted");
1167 return ERROR_TARGET_NOT_HALTED;
1170 LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
1172 arm11_common_t * arm11 = target->arch_info;
1174 arm11_run_instr_data_prepare(arm11);
1176 /* MRC p14,0,r0,c0,c5,0 */
1177 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
1183 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1186 for (i = 0; i < count; i++)
1188 /* MRC p14,0,r1,c0,c5,0 */
1189 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
1191 /* strb r1, [r0], #1 */
1192 arm11_run_instr_no_data1(arm11, 0xe4c01001);
1200 arm11->reg_list[ARM11_RC_R1].dirty = 1;
1202 u16 * buf16 = (u16*)buffer;
1205 for (i = 0; i < count; i++)
1207 /* MRC p14,0,r1,c0,c5,0 */
1208 arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
1210 /* strh r1, [r0], #2 */
1211 arm11_run_instr_no_data1(arm11, 0xe0c010b2);
1218 /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
1220 if (!arm11_config_memwrite_burst)
1222 /* STC p14,c5,[R0],#4 */
1223 arm11_run_instr_data_to_core(arm11, 0xeca05e01, (u32 *)buffer, count);
1227 /* STC p14,c5,[R0],#4 */
1228 arm11_run_instr_data_to_core_noack(arm11, 0xeca05e01, (u32 *)buffer, count);
1235 /* r0 verification */
1239 /* MCR p14,0,R0,c0,c5,0 */
1240 arm11_run_instr_data_from_core(arm11, 0xEE000E15, &r0, 1);
1242 if (address + size * count != r0)
1244 LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
1246 if (arm11_config_memwrite_burst)
1247 LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
1249 if (arm11_config_memwrite_error_fatal)
1256 arm11_run_instr_data_finish(arm11);
1265 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
1266 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer)
1270 if (target->state != TARGET_HALTED)
1272 LOG_WARNING("target was not halted");
1273 return ERROR_TARGET_NOT_HALTED;
1276 return arm11_write_memory(target, address, 4, count, buffer);
1280 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
1282 FNC_INFO_NOTIMPLEMENTED;
1288 /* target break-/watchpoint control
1289 * rw: 0 = write, 1 = read, 2 = access
1291 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1295 arm11_common_t * arm11 = target->arch_info;
1298 if (breakpoint->type == BKPT_SOFT)
1300 LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
1301 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1305 if (!arm11->free_brps)
1307 LOG_INFO("no breakpoint unit available for hardware breakpoint");
1308 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1311 if (breakpoint->length != 4)
1313 LOG_INFO("only breakpoints of four bytes length supported");
1314 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1322 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
1326 arm11_common_t * arm11 = target->arch_info;
1333 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1335 FNC_INFO_NOTIMPLEMENTED;
1340 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
1342 FNC_INFO_NOTIMPLEMENTED;
1347 // HACKHACKHACK - FIXME mode/state
1348 /* target algorithm support */
1349 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
1350 int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point,
1351 int timeout_ms, void *arch_info)
1353 arm11_common_t *arm11 = target->arch_info;
1354 armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
1355 // enum armv4_5_state core_state = arm11->core_state;
1356 // enum armv4_5_mode core_mode = arm11->core_mode;
1359 int exit_breakpoint_size = 0;
1361 int retval = ERROR_OK;
1362 LOG_DEBUG("Running algorithm");
1364 if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
1366 LOG_ERROR("current target isn't an ARMV4/5 target");
1367 return ERROR_TARGET_INVALID;
1370 if (target->state != TARGET_HALTED)
1372 LOG_WARNING("target not halted");
1373 return ERROR_TARGET_NOT_HALTED;
1377 // if (armv4_5_mode_to_number(arm11->core_mode)==-1)
1378 // return ERROR_FAIL;
1381 for (i = 0; i < 16; i++)
1383 context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
1384 LOG_DEBUG("Save %i: 0x%x",i,context[i]);
1387 cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
1388 LOG_DEBUG("Save CPSR: 0x%x",i,cpsr);
1390 for (i = 0; i < num_mem_params; i++)
1392 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1395 // Set register parameters
1396 for (i = 0; i < num_reg_params; i++)
1398 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1402 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1406 if (reg->size != reg_params[i].size)
1408 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1411 arm11_set_reg(reg,reg_params[i].value);
1412 // printf("%i: Set %s =%08x\n", i, reg_params[i].reg_name,val);
1415 exit_breakpoint_size = 4;
1417 /* arm11->core_state = arm11_algorithm_info->core_state;
1418 if (arm11->core_state == ARMV4_5_STATE_ARM)
1419 exit_breakpoint_size = 4;
1420 else if (arm11->core_state == ARMV4_5_STATE_THUMB)
1421 exit_breakpoint_size = 2;
1424 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1428 if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
1430 LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
1431 buf_set_u32(arm11->reg_list[ARM11_RC_CPSR].value, 0, 5, arm11_algorithm_info->core_mode);
1432 arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
1433 arm11->reg_list[ARM11_RC_CPSR].valid = 1;
1436 if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
1438 LOG_ERROR("can't add breakpoint to finish algorithm execution");
1439 retval = ERROR_TARGET_FAILURE;
1443 target_resume(target, 0, entry_point, 1, 0); // no debug, otherwise breakpoint is not set
1445 target_wait_state(target, TARGET_HALTED, timeout_ms);
1446 if (target->state != TARGET_HALTED)
1448 if ((retval=target_halt(target))!=ERROR_OK)
1450 if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
1454 retval = ERROR_TARGET_TIMEOUT;
1455 goto del_breakpoint;
1458 if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
1460 LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
1461 buf_get_u32(arm11->reg_list[15].value, 0, 32));
1462 retval = ERROR_TARGET_TIMEOUT;
1463 goto del_breakpoint;
1466 for (i = 0; i < num_mem_params; i++)
1468 if (mem_params[i].direction != PARAM_OUT)
1469 target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
1472 for (i = 0; i < num_reg_params; i++)
1474 if (reg_params[i].direction != PARAM_OUT)
1476 reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
1479 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1483 if (reg->size != reg_params[i].size)
1485 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
1489 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1494 breakpoint_remove(target, exit_point);
1498 for (i = 0; i < 16; i++)
1500 LOG_DEBUG("restoring register %s with value 0x%8.8x",
1501 arm11->reg_list[i].name, context[i]);
1502 arm11_set_reg(&arm11->reg_list[i], &context[i]);
1504 LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
1505 arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], &cpsr);
1507 // arm11->core_state = core_state;
1508 // arm11->core_mode = core_mode;
1513 int arm11_target_create(struct target_s *target, Jim_Interp *interp)
1517 NEW(arm11_common_t, arm11, 1);
1519 arm11->target = target;
1521 /* prepare JTAG information for the new target */
1522 arm11->jtag_info.chain_pos = target->chain_position;
1523 arm11->jtag_info.scann_size = 5;
1525 arm_jtag_setup_connection(&arm11->jtag_info);
1527 jtag_device_t *device = jtag_get_device(target->chain_position);
1529 if (device->ir_length != 5)
1531 LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
1532 return ERROR_COMMAND_SYNTAX_ERROR;
1535 target->arch_info = arm11;
1540 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
1542 /* Initialize anything we can set up without talking to the target */
1546 /* talk to the target and set things up */
1547 int arm11_examine(struct target_s *target)
1552 arm11_common_t * arm11 = target->arch_info;
1556 arm11_add_IR(arm11, ARM11_IDCODE, -1);
1558 scan_field_t idcode_field;
1560 arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field);
1562 arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD);
1566 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
1568 arm11_add_IR(arm11, ARM11_INTEST, -1);
1570 scan_field_t chain0_fields[2];
1572 arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0);
1573 arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1);
1575 arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI);
1577 if ((retval=jtag_execute_queue())!=ERROR_OK)
1581 switch (arm11->device_id & 0x0FFFF000)
1583 case 0x07B36000: LOG_INFO("found ARM1136"); break;
1584 case 0x07B56000: LOG_INFO("found ARM1156"); break;
1585 case 0x07B76000: LOG_INFO("found ARM1176"); break;
1588 LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
1593 arm11->debug_version = (arm11->didr >> 16) & 0x0F;
1595 if (arm11->debug_version != ARM11_DEBUG_V6 &&
1596 arm11->debug_version != ARM11_DEBUG_V61)
1598 LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
1603 arm11->brp = ((arm11->didr >> 24) & 0x0F) + 1;
1604 arm11->wrp = ((arm11->didr >> 28) & 0x0F) + 1;
1606 /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
1607 arm11->free_brps = arm11->brp;
1608 arm11->free_wrps = arm11->wrp;
1610 LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
1615 arm11_build_reg_cache(target);
1618 /* as a side-effect this reads DSCR and thus
1619 * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
1620 * as suggested by the spec.
1623 arm11_check_init(arm11, NULL);
1625 target->type->examined = 1;
1630 int arm11_quit(void)
1632 FNC_INFO_NOTIMPLEMENTED;
1637 /** Load a register that is marked !valid in the register cache */
1638 int arm11_get_reg(reg_t *reg)
1642 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1644 if (target->state != TARGET_HALTED)
1646 LOG_WARNING("target was not halted");
1647 return ERROR_TARGET_NOT_HALTED;
1650 /** \todo TODO: Check this. We assume that all registers are fetched at debug entry. */
1653 arm11_common_t *arm11 = target->arch_info;
1654 const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1660 /** Change a value in the register cache */
1661 int arm11_set_reg(reg_t *reg, u8 *buf)
1665 target_t * target = ((arm11_reg_state_t *)reg->arch_info)->target;
1666 arm11_common_t *arm11 = target->arch_info;
1667 // const arm11_reg_defs_t * arm11_reg_info = arm11_reg_defs + ((arm11_reg_state_t *)reg->arch_info)->def_index;
1669 arm11->reg_values[((arm11_reg_state_t *)reg->arch_info)->def_index] = buf_get_u32(buf, 0, 32);
1677 void arm11_build_reg_cache(target_t *target)
1679 arm11_common_t *arm11 = target->arch_info;
1681 NEW(reg_cache_t, cache, 1);
1682 NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
1683 NEW(arm11_reg_state_t, arm11_reg_states, ARM11_REGCACHE_COUNT);
1685 if (arm11_regs_arch_type == -1)
1686 arm11_regs_arch_type = register_reg_arch_type(arm11_get_reg, arm11_set_reg);
1688 register_init_dummy(&arm11_gdb_dummy_fp_reg);
1689 register_init_dummy(&arm11_gdb_dummy_fps_reg);
1691 arm11->reg_list = reg_list;
1693 /* Build the process context cache */
1694 cache->name = "arm11 registers";
1696 cache->reg_list = reg_list;
1697 cache->num_regs = ARM11_REGCACHE_COUNT;
1699 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
1702 arm11->core_cache = cache;
1703 // armv7m->process_context = cache;
1707 /* Not very elegant assertion */
1708 if (ARM11_REGCACHE_COUNT != asizeof(arm11->reg_values) ||
1709 ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
1710 ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
1712 LOG_ERROR("BUG: arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
1716 for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
1718 reg_t * r = reg_list + i;
1719 const arm11_reg_defs_t * rd = arm11_reg_defs + i;
1720 arm11_reg_state_t * rs = arm11_reg_states + i;
1724 r->value = (u8 *)(arm11->reg_values + i);
1727 r->bitfield_desc = NULL;
1728 r->num_bitfields = 0;
1729 r->arch_type = arm11_regs_arch_type;
1733 rs->target = target;
1739 int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool * var, char * name)
1743 LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
1748 return ERROR_COMMAND_SYNTAX_ERROR;
1753 case 'f': /* false */
1755 case 'd': /* disable */
1761 case 't': /* true */
1763 case 'e': /* enable */
1769 LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
1775 #define BOOL_WRAPPER(name, print_name) \
1776 int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) \
1778 return arm11_handle_bool(cmd_ctx, cmd, args, argc, &arm11_config_##name, print_name); \
1781 #define RC_TOP(name, descr, more) \
1783 command_t * new_cmd = register_command(cmd_ctx, top_cmd, name, NULL, COMMAND_ANY, descr); \
1784 command_t * top_cmd = new_cmd; \
1788 #define RC_FINAL(name, descr, handler) \
1789 register_command(cmd_ctx, top_cmd, name, handler, COMMAND_ANY, descr);
1791 #define RC_FINAL_BOOL(name, descr, var) \
1792 register_command(cmd_ctx, top_cmd, name, arm11_handle_bool_##var, COMMAND_ANY, descr);
1795 BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
1796 BOOL_WRAPPER(memwrite_error_fatal, "fatal error mode for memory writes")
1799 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1803 arm11_vcr = strtoul(args[0], NULL, 0);
1807 return ERROR_COMMAND_SYNTAX_ERROR;
1810 LOG_INFO("VCR 0x%08X", arm11_vcr);
1814 const u32 arm11_coproc_instruction_limits[] =
1816 15, /* coprocessor */
1821 0xFFFFFFFF, /* value */
1824 const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
1825 const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
1828 arm11_common_t * arm11_find_target(const char * arg)
1830 size_t jtag_target = strtoul(arg, NULL, 0);
1833 for (t = all_targets; t; t = t->next)
1835 if (strcmp(t->type->name,"arm11"))
1838 arm11_common_t * arm11 = t->arch_info;
1840 if (arm11->jtag_info.chain_pos != jtag_target)
1849 int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, bool read)
1851 if (argc != (read ? 6 : 7))
1853 LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
1857 arm11_common_t * arm11 = arm11_find_target(args[0]);
1861 LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
1862 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1868 if (arm11->target->state != TARGET_HALTED)
1870 LOG_WARNING("target was not halted");
1871 return ERROR_TARGET_NOT_HALTED;
1878 for (i = 0; i < (read ? 5 : 6); i++)
1880 values[i] = strtoul(args[i + 1], NULL, 0);
1882 if (values[i] > arm11_coproc_instruction_limits[i])
1884 LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
1885 (long)(i + 2), arm11_coproc_instruction_limits[i],
1886 read ? arm11_mrc_syntax : arm11_mcr_syntax);
1891 u32 instr = 0xEE000010 |
1899 instr |= 0x00100000;
1902 arm11_run_instr_data_prepare(arm11);
1907 arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
1909 LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
1910 values[0], values[1], values[2], values[3], values[4], result, result);
1914 arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
1916 LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
1917 values[0], values[1],
1919 values[2], values[3], values[4]);
1922 arm11_run_instr_data_finish(arm11);
1928 int arm11_handle_mrc(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1930 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
1933 int arm11_handle_mcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1935 return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
1938 int arm11_register_commands(struct command_context_s *cmd_ctx)
1942 command_t * top_cmd = NULL;
1944 RC_TOP( "arm11", "arm11 specific commands",
1946 RC_TOP( "memwrite", "Control memory write transfer mode",
1948 RC_FINAL_BOOL( "burst", "Enable/Disable non-standard but fast burst mode (default: enabled)",
1951 RC_FINAL_BOOL( "error_fatal",
1952 "Terminate program if transfer error was found (default: enabled)",
1953 memwrite_error_fatal)
1956 RC_FINAL( "vcr", "Control (Interrupt) Vector Catch Register",
1959 RC_FINAL( "mrc", "Read Coprocessor register",
1962 RC_FINAL( "mcr", "Write Coprocessor register",