1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
27 #include "embeddedice.h"
31 #define asizeof(x) (sizeof(x) / sizeof((x)[0]))
33 #define NEW(type, variable, items) \
34 type * variable = calloc(1, sizeof(type) * items)
36 /* For MinGW use 'I' prefix to print size_t (instead of 'z') */
44 #define ARM11_REGCACHE_MODEREGS 0
45 #define ARM11_REGCACHE_FREGS 0
47 #define ARM11_REGCACHE_COUNT (20 + \
48 23 * ARM11_REGCACHE_MODEREGS + \
49 9 * ARM11_REGCACHE_FREGS)
51 #define ARM11_TAP_DEFAULT TAP_INVALID
54 #define CHECK_RETVAL(action) \
56 int __retval = (action); \
58 if (__retval != ERROR_OK) \
60 LOG_DEBUG("error while calling \"" # action "\""); \
67 typedef struct arm11_register_history_s
71 }arm11_register_history_t;
73 enum arm11_debug_version
75 ARM11_DEBUG_V6 = 0x01,
76 ARM11_DEBUG_V61 = 0x02,
77 ARM11_DEBUG_V7 = 0x03,
78 ARM11_DEBUG_V7_CP14 = 0x04,
81 typedef struct arm11_common_s
83 target_t * target; /**< Reference back to the owner */
85 arm_jtag_t jtag_info; /**< Handler to access assigned JTAG device */
87 /** \name Processor type detection */
90 u32 device_id; /**< IDCODE readout */
91 u32 didr; /**< DIDR readout (debug capabilities) */
92 u8 implementor; /**< DIDR Implementor readout */
94 size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
95 size_t wrp; /**< Number of Watchpoint Register Pairs from DIDR */
97 enum arm11_debug_version
98 debug_version; /**< ARM debug architecture from DIDR */
101 u32 last_dscr; /**< Last retrieved DSCR value;
102 Use only for debug message generation */
105 bool halt_requested; /**< Keep track if arm11_halt() calls occured
106 during reset. Otherwise do it ASAP. */
108 bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
110 /** \name Shadow registers to save processor state */
113 reg_t * reg_list; /**< target register list */
114 u32 reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
118 arm11_register_history_t
119 reg_history[ARM11_REGCACHE_COUNT]; /**< register state before last resume */
121 size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
122 size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
125 reg_cache_t *core_cache;
130 * ARM11 DBGTAP instructions
132 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
134 enum arm11_instructions
138 ARM11_RESTART = 0x04,
148 ARM11_DSCR_CORE_HALTED = 1 << 0,
149 ARM11_DSCR_CORE_RESTARTED = 1 << 1,
151 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK = 0x0F << 2,
152 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT = 0x00 << 2,
153 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT = 0x01 << 2,
154 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT = 0x02 << 2,
155 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION = 0x03 << 2,
156 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ = 0x04 << 2,
157 ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH = 0x05 << 2,
159 ARM11_DSCR_STICKY_PRECISE_DATA_ABORT = 1 << 6,
160 ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT = 1 << 7,
161 ARM11_DSCR_INTERRUPTS_DISABLE = 1 << 11,
162 ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE = 1 << 13,
163 ARM11_DSCR_MODE_SELECT = 1 << 14,
164 ARM11_DSCR_WDTR_FULL = 1 << 29,
165 ARM11_DSCR_RDTR_FULL = 1 << 30,
170 ARM11_CPSR_T = 1 << 5,
171 ARM11_CPSR_J = 1 << 24,
182 ARM11_SC7_WCR0 = 112,
185 typedef struct arm11_reg_state_s
191 /* poll current target status */
192 int arm11_poll(struct target_s *target);
193 /* architecture specific status reply */
194 int arm11_arch_state(struct target_s *target);
196 /* target request support */
197 int arm11_target_request_data(struct target_s *target, u32 size, u8 *buffer);
199 /* target execution control */
200 int arm11_halt(struct target_s *target);
201 int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
202 int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
203 int arm11_examine(struct target_s *target);
205 /* target reset control */
206 int arm11_assert_reset(struct target_s *target);
207 int arm11_deassert_reset(struct target_s *target);
208 int arm11_soft_reset_halt(struct target_s *target);
210 /* target register access for gdb */
211 int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
213 /* target memory access
214 * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
215 * count: number of items of <size>
217 int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
218 int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
220 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
221 int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8 *buffer);
223 int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
225 /* target break-/watchpoint control
226 * rw: 0 = write, 1 = read, 2 = access
228 int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
229 int arm11_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
230 int arm11_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
231 int arm11_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
233 /* target algorithm support */
234 int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
236 int arm11_register_commands(struct command_context_s *cmd_ctx);
237 int arm11_target_create(struct target_s *target, Jim_Interp *interp);
238 int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
239 int arm11_quit(void);
242 int arm11_build_reg_cache(target_t *target);
243 int arm11_set_reg(reg_t *reg, u8 *buf);
244 int arm11_get_reg(reg_t *reg);
246 void arm11_record_register_history(arm11_common_t * arm11);
247 void arm11_dump_reg_changes(arm11_common_t * arm11);
251 void arm11_setup_field (arm11_common_t * arm11, int num_bits, void * in_data, void * out_data, scan_field_t * field);
252 void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
253 void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
254 void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
255 int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
256 int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
258 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
260 void arm11_run_instr_data_prepare (arm11_common_t * arm11);
261 void arm11_run_instr_data_finish (arm11_common_t * arm11);
262 int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
263 void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
264 int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
265 int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
266 int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
267 int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
268 void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
269 void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
271 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
272 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);
274 /** Used to make a list of read/write commands for scan chain 7
276 * Use with arm11_sc7_run()
278 typedef struct arm11_sc7_action_s
280 bool write; /**< Access mode: true for write, false for read. */
281 u8 address; /**< Register address mode. Use enum #arm11_sc7 */
282 u32 value; /**< If write then set this to value to be written.
283 In read mode this receives the read value when the
285 } arm11_sc7_action_t;
287 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
289 /* Mid-level helper functions */
290 void arm11_sc7_clear_vbw(arm11_common_t * arm11);
291 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
293 int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);