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   1 /***************************************************************************
   2  *   Copyright (C) 2008 digenius technology GmbH.                          *
   3  *   Michael Bruck                                                         *
   4  *                                                                         *
   5  *   Copyright (C) 2008 Georg Acher <acher@in.tum.de>                      *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22
  23 #ifndef ARM11_H
  24 #define ARM11_H
  25
  26 #include "armv4_5.h"
  27
  28 /* TEMPORARY -- till we switch to the shared infrastructure */
  29 #define ARM11_REGCACHE_COUNT            20
  30
  31 #define ARM11_TAP_DEFAULT                       TAP_INVALID
  32
  33 #define CHECK_RETVAL(action)                    \
  34         do {                                    \
  35                 int __retval = (action);        \
  36                 if (__retval != ERROR_OK) {     \
  37                         LOG_DEBUG("error while calling \"%s\"", \
  38                                 # action );     \
  39                         return __retval;        \
  40                 }                               \
  41         } while (0)
  42
  43 struct arm11_register_history
  44 {
  45         uint32_t                value;
  46         uint8_t         valid;
  47 };
  48
  49 enum arm11_debug_version
  50 {
  51         ARM11_DEBUG_V6                  = 0x01,
  52         ARM11_DEBUG_V61                 = 0x02,
  53         ARM11_DEBUG_V7                  = 0x03,
  54         ARM11_DEBUG_V7_CP14             = 0x04,
  55 };
  56
  57 struct arm11_common
  58 {
  59         struct arm      arm;
  60         struct target * target;         /**< Reference back to the owner */
  61
  62         /** \name Processor type detection */
  63         /*@{*/
  64
  65         uint32_t                device_id;              /**< IDCODE readout                             */
  66         uint32_t                didr;                   /**< DIDR readout (debug capabilities)  */
  67         uint8_t         implementor;    /**< DIDR Implementor readout           */
  68
  69         size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
  70         size_t  wrp;                    /**< Number of Watchpoint Register Pairs from DIDR      */
  71
  72         enum arm11_debug_version
  73                 debug_version;          /**< ARM debug architecture from DIDR   */
  74         /*@}*/
  75
  76         uint32_t                last_dscr;              /**< Last retrieved DSCR value;
  77                                                              Use only for debug message generation              */
  78
  79         bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
  80
  81         /** \name Shadow registers to save processor state */
  82         /*@{*/
  83
  84         struct reg *    reg_list;                                                       /**< target register list */
  85         uint32_t                reg_values[ARM11_REGCACHE_COUNT];       /**< data for registers */
  86
  87         /*@}*/
  88
  89         struct arm11_register_history
  90                 reg_history[ARM11_REGCACHE_COUNT];      /**< register state before last resume */
  91
  92         size_t  free_brps;                              /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
  93         size_t  free_wrps;                              /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
  94
  95         // GA
  96         struct reg_cache *core_cache;
  97
  98         struct arm_jtag jtag_info;
  99 };
 100
 101 static inline struct arm11_common *target_to_arm11(struct target *target)
 102 {
 103         return container_of(target->arch_info, struct arm11_common,
 104                         arm);
 105 }
 106
 107 /**
 108  * ARM11 DBGTAP instructions
 109  *
 110  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
 111  */
 112 enum arm11_instructions
 113 {
 114         ARM11_EXTEST    = 0x00,
 115         ARM11_SCAN_N    = 0x02,
 116         ARM11_RESTART   = 0x04,
 117         ARM11_HALT          = 0x08,
 118         ARM11_INTEST    = 0x0C,
 119         ARM11_ITRSEL    = 0x1D,
 120         ARM11_IDCODE    = 0x1E,
 121         ARM11_BYPASS    = 0x1F,
 122 };
 123
 124 enum arm11_dscr
 125 {
 126         ARM11_DSCR_CORE_HALTED                                                                  = 1 << 0,
 127         ARM11_DSCR_CORE_RESTARTED                                                               = 1 << 1,
 128
 129         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK                                   = 0x0F << 2,
 130         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT                                   = 0x00 << 2,
 131         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT                             = 0x01 << 2,
 132         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT                             = 0x02 << 2,
 133         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION               = 0x03 << 2,
 134         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ                                 = 0x04 << 2,
 135         ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH                   = 0x05 << 2,
 136
 137         ARM11_DSCR_STICKY_PRECISE_DATA_ABORT                                    = 1 << 6,
 138         ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT                                  = 1 << 7,
 139         ARM11_DSCR_INTERRUPTS_DISABLE                                                   = 1 << 11,
 140         ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE                               = 1 << 13,
 141         ARM11_DSCR_MODE_SELECT                                                                  = 1 << 14,
 142         ARM11_DSCR_WDTR_FULL                                                                    = 1 << 29,
 143         ARM11_DSCR_RDTR_FULL                                                                    = 1 << 30,
 144 };
 145
 146 enum arm11_cpsr
 147 {
 148         ARM11_CPSR_T                            = 1 << 5,
 149         ARM11_CPSR_J                            = 1 << 24,
 150 };
 151
 152 enum arm11_sc7
 153 {
 154         ARM11_SC7_NULL                          = 0,
 155         ARM11_SC7_VCR                           = 7,
 156         ARM11_SC7_PC                            = 8,
 157         ARM11_SC7_BVR0                          = 64,
 158         ARM11_SC7_BCR0                          = 80,
 159         ARM11_SC7_WVR0                          = 96,
 160         ARM11_SC7_WCR0                          = 112,
 161 };
 162
 163 struct arm11_reg_state
 164 {
 165         uint32_t                                def_index;
 166         struct target *                 target;
 167 };
 168
 169 #endif /* ARM11_H */