1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
30 #define JTAG_DEBUG(expr ...) DEBUG(expr)
32 #define JTAG_DEBUG(expr ...) do {} while(0)
36 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
37 behavior of the FTDI driver IIRC was to go via RTI.
39 Conversely there may be other places in this code where the ARM11 code relies
40 on the driver to hit through RTI when coming from Update-?R.
42 tap_state_t arm11_move_pi_to_si_via_ci[] =
44 TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
48 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
50 if (cmd_queue_cur_state == TAP_IRPAUSE)
51 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
53 jtag_add_ir_scan(num_fields, fields, state);
57 tap_state_t arm11_move_pd_to_sd_via_cd[] =
59 TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
62 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
64 if (cmd_queue_cur_state == TAP_DRPAUSE)
65 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
67 jtag_add_dr_scan(num_fields, fields, state);
72 /** Code de-clutter: Construct scan_field_t to write out a value
74 * \param arm11 Target state variable.
75 * \param num_bits Length of the data field
76 * \param out_data pointer to the data that will be sent out
77 * <em>(data is read when it is added to the JTAG queue)</em>
78 * \param in_data pointer to the memory that will receive data that was clocked in
79 * <em>(data is written when the JTAG queue is executed)</em>
80 * \param field target data structure that will be initialized
82 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
84 field->tap = arm11->jtag_info.tap;
85 field->num_bits = num_bits;
86 field->out_value = out_data;
87 field->in_value = in_data;
91 /** Write JTAG instruction register
93 * \param arm11 Target state variable.
94 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
95 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
97 * \remarks This adds to the JTAG command queue but does \em not execute it.
99 void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
102 tap = arm11->jtag_info.tap;
104 if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
106 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
110 JTAG_DEBUG("IR <= 0x%02x", instr);
114 arm11_setup_field(arm11, 5, &instr, NULL, &field);
116 arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
119 /** Verify shifted out data from Scan Chain Register (SCREG)
120 * Used as parameter to scan_field_t::in_handler in
121 * arm11_add_debug_SCAN_N().
124 static void arm11_in_handler_SCAN_N(u8 *in_value)
126 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
127 u8 v = *in_value & 0x1F;
131 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
132 jtag_set_error(ERROR_FAIL);
135 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
138 /** Select and write to Scan Chain Register (SCREG)
140 * This function sets the instruction register to SCAN_N and writes
141 * the data register with the selected chain number.
143 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
145 * \param arm11 Target state variable.
146 * \param chain Scan chain that will be selected.
147 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
150 * The chain takes effect when Update-DR is passed (usually when subsequently
151 * the INTEXT/EXTEST instructions are written).
153 * \warning (Obsolete) Using this twice in a row will \em fail. The first
154 * call will end in Pause-DR. The second call, due to the IR
155 * caching, will not go through Capture-DR when shifting in the
156 * new scan chain number. As a result the verification in
157 * arm11_in_handler_SCAN_N() must fail.
159 * \remarks This adds to the JTAG command queue but does \em not execute it.
162 void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
164 JTAG_DEBUG("SCREG <= 0x%02x", chain);
166 arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
171 arm11_setup_field(arm11, 5, &chain, &tmp, &field);
173 arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
175 jtag_execute_queue_noclear();
177 arm11_in_handler_SCAN_N(tmp);
180 /** Write an instruction into the ITR register
182 * \param arm11 Target state variable.
183 * \param inst An ARM11 processor instruction/opcode.
184 * \param flag Optional parameter to retrieve the InstCompl flag
185 * (this will be written when the JTAG chain is executed).
186 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
187 * value (Run-Test/Idle).
189 * \remarks By default this ends with Run-Test/Idle state
190 * and causes the instruction to be executed. If
191 * a subsequent write to DTR is needed before
192 * executing the instruction then TAP_DRPAUSE should be
193 * passed to \p state.
195 * \remarks This adds to the JTAG command queue but does \em not execute it.
197 void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
199 JTAG_DEBUG("INST <= 0x%08x", inst);
203 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
204 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
206 arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
209 /** Read the Debug Status and Control Register (DSCR)
213 * \param arm11 Target state variable.
214 * \return DSCR content
216 * \remarks This is a stand-alone function that executes the JTAG command queue.
218 int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
220 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
222 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
225 scan_field_t chain1_field;
227 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
229 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
231 CHECK_RETVAL(jtag_execute_queue());
233 if (arm11->last_dscr != dscr)
234 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
236 arm11->last_dscr = dscr;
243 /** Write the Debug Status and Control Register (DSCR)
247 * \param arm11 Target state variable.
248 * \param dscr DSCR content
250 * \remarks This is a stand-alone function that executes the JTAG command queue.
252 int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
254 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
256 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
258 scan_field_t chain1_field;
260 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
262 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
264 CHECK_RETVAL(jtag_execute_queue());
266 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
268 arm11->last_dscr = dscr;
275 /** Get the debug reason from Debug Status and Control Register (DSCR)
277 * \param dscr DSCR value to analyze
278 * \return Debug reason
281 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
283 switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
285 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
286 LOG_INFO("Debug entry: JTAG HALT");
287 return DBG_REASON_DBGRQ;
289 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
290 LOG_INFO("Debug entry: breakpoint");
291 return DBG_REASON_BREAKPOINT;
293 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
294 LOG_INFO("Debug entry: watchpoint");
295 return DBG_REASON_WATCHPOINT;
297 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
298 LOG_INFO("Debug entry: BKPT instruction");
299 return DBG_REASON_BREAKPOINT;
301 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
302 LOG_INFO("Debug entry: EDBGRQ signal");
303 return DBG_REASON_DBGRQ;
305 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
306 LOG_INFO("Debug entry: VCR vector catch");
307 return DBG_REASON_BREAKPOINT;
310 LOG_INFO("Debug entry: unknown");
311 return DBG_REASON_DBGRQ;
317 /** Prepare the stage for ITR/DTR operations
318 * from the arm11_run_instr... group of functions.
320 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
321 * around a block of arm11_run_instr_... calls.
323 * Select scan chain 5 to allow quick access to DTR. When scan
324 * chain 4 is needed to put in a register the ITRSel instruction
325 * shortcut is used instead of actually changing the Scan_N
328 * \param arm11 Target state variable.
331 void arm11_run_instr_data_prepare(arm11_common_t * arm11)
333 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
336 /** Cleanup after ITR/DTR operations
337 * from the arm11_run_instr... group of functions
339 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
340 * around a block of arm11_run_instr_... calls.
342 * Any IDLE can lead to an instruction execution when
343 * scan chains 4 or 5 are selected and the IR holds
344 * INTEST or EXTEST. So we must disable that before
345 * any following activities lead to an IDLE.
347 * \param arm11 Target state variable.
350 void arm11_run_instr_data_finish(arm11_common_t * arm11)
352 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
356 /** Execute one or multiple instructions via ITR
358 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
360 * \param arm11 Target state variable.
361 * \param opcode Pointer to sequence of ARM opcodes
362 * \param count Number of opcodes to execute
365 int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
367 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
371 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
377 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
379 CHECK_RETVAL(jtag_execute_queue());
389 /** Execute one instruction via ITR
391 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
393 * \param arm11 Target state variable.
394 * \param opcode ARM opcode
397 void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
399 arm11_run_instr_no_data(arm11, &opcode, 1);
403 /** Execute one instruction via ITR repeatedly while
404 * passing data to the core via DTR on each execution.
406 * The executed instruction \em must read data from DTR.
408 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
410 * \param arm11 Target state variable.
411 * \param opcode ARM opcode
412 * \param data Pointer to the data words to be passed to the core
413 * \param count Number of data words and instruction repetitions
416 int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
418 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
420 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
422 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
424 scan_field_t chain5_fields[3];
430 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
431 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
432 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
440 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
442 CHECK_RETVAL(jtag_execute_queue());
444 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
451 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
457 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
459 CHECK_RETVAL(jtag_execute_queue());
461 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
468 /** JTAG path for arm11_run_instr_data_to_core_noack
470 * The repeated TAP_IDLE's do not cause a repeated execution
471 * if passed without leaving the state.
473 * Since this is more than 7 bits (adjustable via adding more
474 * TAP_IDLE's) it produces an artificial delay in the lower
475 * layer (FT2232) that is long enough to finish execution on
476 * the core but still shorter than any manually inducible delays.
478 * To disable this code, try "memwrite burst false"
481 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
483 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
488 /** Execute one instruction via ITR repeatedly while
489 * passing data to the core via DTR on each execution.
491 * No Ready check during transmission.
493 * The executed instruction \em must read data from DTR.
495 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
497 * \param arm11 Target state variable.
498 * \param opcode ARM opcode
499 * \param data Pointer to the data words to be passed to the core
500 * \param count Number of data words and instruction repetitions
503 int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
505 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
507 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
509 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
511 scan_field_t chain5_fields[3];
513 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
514 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
515 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
517 u8 Readies[count + 1];
518 u8 * ReadyPos = Readies;
522 chain5_fields[0].out_value = (void *)(data++);
523 chain5_fields[1].in_value = ReadyPos++;
527 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
528 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
529 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
533 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
537 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
539 chain5_fields[0].out_value = 0;
540 chain5_fields[1].in_value = ReadyPos++;
542 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
544 CHECK_RETVAL(jtag_execute_queue());
546 size_t error_count = 0;
548 for (size_t i = 0; i < asizeof(Readies); i++)
557 LOG_ERROR("Transfer errors " ZU, error_count);
563 /** Execute an instruction via ITR while handing data into the core via DTR.
565 * The executed instruction \em must read data from DTR.
567 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
569 * \param arm11 Target state variable.
570 * \param opcode ARM opcode
571 * \param data Data word to be passed to the core via DTR
574 int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
576 return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
580 /** Execute one instruction via ITR repeatedly while
581 * reading data from the core via DTR on each execution.
583 * The executed instruction \em must write data to DTR.
585 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
587 * \param arm11 Target state variable.
588 * \param opcode ARM opcode
589 * \param data Pointer to an array that receives the data words from the core
590 * \param count Number of data words and instruction repetitions
593 int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
595 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
597 arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
599 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
601 scan_field_t chain5_fields[3];
607 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
608 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
609 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
615 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
617 CHECK_RETVAL(jtag_execute_queue());
619 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
629 /** Execute one instruction via ITR
630 * then load r0 into DTR and read DTR from core.
632 * The first executed instruction (\p opcode) should write data to r0.
634 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
636 * \param arm11 Target state variable.
637 * \param opcode ARM opcode to write r0 with the value of interest
638 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
641 void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
643 arm11_run_instr_no_data1(arm11, opcode);
645 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
646 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
649 /** Load data into core via DTR then move it to r0 then
650 * execute one instruction via ITR
652 * The final executed instruction (\p opcode) should read data from r0.
654 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
656 * \param arm11 Target state variable.
657 * \param opcode ARM opcode to read r0 act upon it
658 * \param data Data word that will be written to r0 before \p opcode is executed
661 void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
663 /* MRC p14,0,r0,c0,c5,0 */
664 arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
666 arm11_run_instr_no_data1(arm11, opcode);
669 /** Apply reads and writes to scan chain 7
671 * \see arm11_sc7_action_t
673 * \param arm11 Target state variable.
674 * \param actions A list of read and/or write instructions
675 * \param count Number of instructions in the list.
678 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
680 arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
682 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
684 scan_field_t chain7_fields[3];
693 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
694 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
695 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
697 for (size_t i = 0; i < count + 1; i++)
701 nRW = actions[i].write ? 1 : 0;
702 DataOut = actions[i].value;
703 AddressOut = actions[i].address;
714 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
716 arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
718 CHECK_RETVAL(jtag_execute_queue());
720 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
722 while (!Ready); /* 'nRW' is 'Ready' on read out */
726 if (actions[i - 1].address != AddressIn)
728 LOG_WARNING("Scan chain 7 shifted out unexpected address");
731 if (!actions[i - 1].write)
733 actions[i - 1].value = DataIn;
737 if (actions[i - 1].value != DataIn)
739 LOG_WARNING("Scan chain 7 shifted out unexpected data");
745 for (size_t i = 0; i < count; i++)
747 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
753 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
755 * \param arm11 Target state variable.
758 void arm11_sc7_clear_vbw(arm11_common_t * arm11)
760 arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
761 arm11_sc7_action_t * pos = clear_bw;
763 for (size_t i = 0; i < asizeof(clear_bw); i++)
765 clear_bw[i].write = true;
766 clear_bw[i].value = 0;
769 for (size_t i = 0; i < arm11->brp; i++)
770 (pos++)->address = ARM11_SC7_BCR0 + i;
773 for (size_t i = 0; i < arm11->wrp; i++)
774 (pos++)->address = ARM11_SC7_WCR0 + i;
777 (pos++)->address = ARM11_SC7_VCR;
779 arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
782 /** Write VCR register
784 * \param arm11 Target state variable.
785 * \param value Value to be written
787 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
789 arm11_sc7_action_t set_vcr;
791 set_vcr.write = true;
792 set_vcr.address = ARM11_SC7_VCR;
793 set_vcr.value = value;
796 arm11_sc7_run(arm11, &set_vcr, 1);
801 /** Read word from address
803 * \param arm11 Target state variable.
804 * \param address Memory address to be read
805 * \param result Pointer where to store result
808 int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
810 arm11_run_instr_data_prepare(arm11);
812 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
813 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
815 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
816 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
818 arm11_run_instr_data_finish(arm11);