1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
5 * Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
28 #include "arm11_dbgtap.h"
30 #include <helper/time_support.h>
33 #define JTAG_DEBUG(expr ...) do { if (1) LOG_DEBUG(expr); } while (0)
35 #define JTAG_DEBUG(expr ...) do { if (0) LOG_DEBUG(expr); } while (0)
39 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
40 behavior of the FTDI driver IIRC was to go via RTI.
42 Conversely there may be other places in this code where the ARM11 code relies
43 on the driver to hit through RTI when coming from Update-?R.
45 static const tap_state_t arm11_move_pi_to_si_via_ci[] =
47 TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
51 /* REVISIT no error handling here! */
52 static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields,
55 if (cmd_queue_cur_state == TAP_IRPAUSE)
56 jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
58 jtag_add_ir_scan(tap, fields, state);
61 static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
63 TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
66 /* REVISIT no error handling here! */
67 void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields,
70 if (cmd_queue_cur_state == TAP_DRPAUSE)
71 jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
73 jtag_add_dr_scan(tap, num_fields, fields, state);
77 /** Code de-clutter: Construct struct scan_field to write out a value
79 * \param arm11 Target state variable.
80 * \param num_bits Length of the data field
81 * \param out_data pointer to the data that will be sent out
82 * <em > (data is read when it is added to the JTAG queue)</em>
83 * \param in_data pointer to the memory that will receive data that was clocked in
84 * <em > (data is written when the JTAG queue is executed)</em>
85 * \param field target data structure that will be initialized
87 void arm11_setup_field(struct arm11_common *arm11, int num_bits,
88 void *out_data, void *in_data, struct scan_field *field)
90 field->num_bits = num_bits;
91 field->out_value = out_data;
92 field->in_value = in_data;
95 static const char *arm11_ir_to_string(uint8_t ir)
97 const char *s = "unknown";
128 /** Write JTAG instruction register
130 * \param arm11 Target state variable.
131 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
132 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
134 * \remarks This adds to the JTAG command queue but does \em not execute it.
136 void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
138 struct jtag_tap *tap = arm11->arm.target->tap;
140 if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
142 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
146 JTAG_DEBUG("IR <= %s (0x%02x)", arm11_ir_to_string(instr), instr);
148 struct scan_field field;
150 arm11_setup_field(arm11, 5, &instr, NULL, &field);
152 arm11_add_ir_scan_vc(arm11->arm.target->tap, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
155 /** Verify data shifted out from Scan Chain Register (SCREG). */
156 static void arm11_in_handler_SCAN_N(uint8_t *in_value)
158 /* Don't expect JTAG layer to modify bits we didn't ask it to read */
159 uint8_t v = *in_value & 0x1F;
163 LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v);
164 jtag_set_error(ERROR_FAIL);
168 /** Select and write to Scan Chain Register (SCREG)
170 * This function sets the instruction register to SCAN_N and writes
171 * the data register with the selected chain number.
173 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
175 * \param arm11 Target state variable.
176 * \param chain Scan chain that will be selected.
177 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
180 * Changes the current scan chain if needed, transitions to the specified
181 * TAP state, and leaves the IR undefined.
183 * The chain takes effect when Update-DR is passed (usually when subsequently
184 * the INTEXT/EXTEST instructions are written).
186 * \warning (Obsolete) Using this twice in a row will \em fail. The first
187 * call will end in Pause-DR. The second call, due to the IR
188 * caching, will not go through Capture-DR when shifting in the
189 * new scan chain number. As a result the verification in
190 * arm11_in_handler_SCAN_N() must fail.
192 * \remarks This adds to the JTAG command queue but does \em not execute it.
195 int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
196 uint8_t chain, tap_state_t state)
198 /* Don't needlessly switch the scan chain.
199 * NOTE: the ITRSEL instruction fakes SCREG changing;
200 * but leaves its actual value unchanged.
202 if (arm11->jtag_info.cur_scan_chain == chain) {
203 JTAG_DEBUG("SCREG <= %d SKIPPED", chain);
204 return jtag_add_statemove((state == ARM11_TAP_DEFAULT)
205 ? TAP_DRPAUSE : state);
207 JTAG_DEBUG("SCREG <= %d", chain);
209 arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
211 struct scan_field field;
214 arm11_setup_field(arm11, 5, &chain, &tmp, &field);
216 arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
218 jtag_execute_queue_noclear();
220 arm11_in_handler_SCAN_N(tmp);
222 arm11->jtag_info.cur_scan_chain = chain;
224 return jtag_execute_queue();
228 * Queue a DR scan of the ITR register. Caller must have selected
229 * scan chain 4 (ITR), possibly using ITRSEL.
231 * \param arm11 Target state variable.
232 * \param inst An ARM11 processor instruction/opcode.
233 * \param flag Optional parameter to retrieve the Ready flag;
234 * this address will be written when the JTAG chain is scanned.
235 * \param state The TAP state to enter after the DR scan.
237 * Going through the TAP_DRUPDATE state writes ITR only if Ready was
238 * previously set. Only the Ready flag is readable by the scan.
240 * An instruction loaded into ITR is executed when going through the
241 * TAP_IDLE state only if Ready was previously set and the debug state
242 * is properly set up. Depending on the instruction, you may also need
243 * to ensure that the rDTR is ready before that Run-Test/Idle state.
245 static void arm11_add_debug_INST(struct arm11_common * arm11,
246 uint32_t inst, uint8_t * flag, tap_state_t state)
248 JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
250 struct scan_field itr[2];
252 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
253 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
255 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(itr), itr, state);
259 * Read and save the Debug Status and Control Register (DSCR).
261 * \param arm11 Target state variable.
262 * \return Error status; arm11->dscr is updated on success.
264 * \remarks This is a stand-alone function that executes the JTAG
265 * command queue. It does not require the ARM11 debug TAP to be
266 * in any particular state.
268 int arm11_read_DSCR(struct arm11_common *arm11)
272 retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
273 if (retval != ERROR_OK)
276 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
279 struct scan_field chain1_field;
281 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
283 arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &chain1_field, TAP_DRPAUSE);
285 CHECK_RETVAL(jtag_execute_queue());
287 if (arm11->dscr != dscr)
288 JTAG_DEBUG("DSCR = %08x (OLD %08x)",
290 (unsigned) arm11->dscr);
297 /** Write the Debug Status and Control Register (DSCR)
301 * \param arm11 Target state variable.
302 * \param dscr DSCR content
304 * \remarks This is a stand-alone function that executes the JTAG command queue.
306 int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
309 retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
310 if (retval != ERROR_OK)
313 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
315 struct scan_field chain1_field;
317 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
319 arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &chain1_field, TAP_DRPAUSE);
321 CHECK_RETVAL(jtag_execute_queue());
323 JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
325 (unsigned) arm11->dscr);
332 /** Prepare the stage for ITR/DTR operations
333 * from the arm11_run_instr... group of functions.
335 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
336 * around a block of arm11_run_instr_... calls.
338 * Select scan chain 5 to allow quick access to DTR. When scan
339 * chain 4 is needed to put in a register the ITRSel instruction
340 * shortcut is used instead of actually changing the Scan_N
343 * \param arm11 Target state variable.
346 int arm11_run_instr_data_prepare(struct arm11_common * arm11)
348 return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
351 /** Cleanup after ITR/DTR operations
352 * from the arm11_run_instr... group of functions
354 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
355 * around a block of arm11_run_instr_... calls.
357 * Any IDLE can lead to an instruction execution when
358 * scan chains 4 or 5 are selected and the IR holds
359 * INTEST or EXTEST. So we must disable that before
360 * any following activities lead to an IDLE.
362 * \param arm11 Target state variable.
365 int arm11_run_instr_data_finish(struct arm11_common * arm11)
367 return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
373 * Execute one or more instructions via ITR.
374 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
375 * is set, the ITR Ready flag is set (as seen on the previous entry to
376 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
378 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
380 * \param arm11 Target state variable.
381 * \param opcode Pointer to sequence of ARM opcodes
382 * \param count Number of opcodes to execute
386 int arm11_run_instr_no_data(struct arm11_common * arm11,
387 uint32_t * opcode, size_t count)
389 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
393 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
400 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
402 CHECK_RETVAL(jtag_execute_queue());
415 if ((timeval_ms()-then) > 1000)
417 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
429 /** Execute one instruction via ITR
431 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
433 * \param arm11 Target state variable.
434 * \param opcode ARM opcode
437 int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode)
439 return arm11_run_instr_no_data(arm11, &opcode, 1);
443 /** Execute one instruction via ITR repeatedly while
444 * passing data to the core via DTR on each execution.
446 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
447 * is set, the ITR Ready flag is set (as seen on the previous entry to
448 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
450 * The executed instruction \em must read data from DTR.
452 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
454 * \param arm11 Target state variable.
455 * \param opcode ARM opcode
456 * \param data Pointer to the data words to be passed to the core
457 * \param count Number of data words and instruction repetitions
460 int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
462 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
464 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
466 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
468 struct scan_field chain5_fields[3];
474 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
475 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
476 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
485 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
487 CHECK_RETVAL(jtag_execute_queue());
489 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
499 if ((timeval_ms()-then) > 1000)
501 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
513 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
520 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
522 CHECK_RETVAL(jtag_execute_queue());
524 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
525 (unsigned) Data, Ready, nRetry);
535 if ((timeval_ms()-then) > 1000)
537 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
549 /** JTAG path for arm11_run_instr_data_to_core_noack
551 * The repeated TAP_IDLE's do not cause a repeated execution
552 * if passed without leaving the state.
554 * Since this is more than 7 bits (adjustable via adding more
555 * TAP_IDLE's) it produces an artificial delay in the lower
556 * layer (FT2232) that is long enough to finish execution on
557 * the core but still shorter than any manually inducible delays.
559 * To disable this code, try "memwrite burst false"
561 * FIX!!! should we use multiple TAP_IDLE here or not???
563 * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
564 * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
566 static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
568 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
571 /* This inner loop can be implemented by the minidriver, oftentimes in hardware... The
572 * minidriver can call the default implementation as a fallback or implement it
575 int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
577 struct scan_field chain5_fields[3];
579 chain5_fields[0].num_bits = 32;
580 chain5_fields[0].out_value = NULL; /*&Data*/
581 chain5_fields[0].in_value = NULL;
583 chain5_fields[1].num_bits = 1;
584 chain5_fields[1].out_value = NULL;
585 chain5_fields[1].in_value = NULL; /*&Ready*/
587 chain5_fields[2].num_bits = 1;
588 chain5_fields[2].out_value = NULL;
589 chain5_fields[2].in_value = NULL;
592 unsigned readiesNum = count;
593 unsigned bytes = sizeof(*Readies)*readiesNum;
595 Readies = (uint8_t *) malloc(bytes);
598 LOG_ERROR("Out of memory allocating %u bytes", bytes);
602 uint8_t * ReadyPos = Readies;
605 chain5_fields[0].out_value = (void *)(data++);
606 chain5_fields[1].in_value = ReadyPos++;
610 jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
611 jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
612 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
615 jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
619 int retval = jtag_execute_queue();
620 if (retval == ERROR_OK)
622 unsigned error_count = 0;
624 for (size_t i = 0; i < readiesNum; i++)
632 if (error_count > 0 )
634 LOG_ERROR("%u words out of %u not transferred",
635 error_count, readiesNum);
644 int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count);
646 #ifndef HAVE_JTAG_MINIDRIVER_H
647 int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
649 return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
653 /** Execute one instruction via ITR repeatedly while
654 * passing data to the core via DTR on each execution.
656 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
657 * is set, the ITR Ready flag is set (as seen on the previous entry to
658 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
660 * No Ready check during transmission.
662 * The executed instruction \em must read data from DTR.
664 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
666 * \param arm11 Target state variable.
667 * \param opcode ARM opcode
668 * \param data Pointer to the data words to be passed to the core
669 * \param count Number of data words and instruction repetitions
672 int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
674 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
676 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
678 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
680 int retval = arm11_run_instr_data_to_core_noack_inner(arm11->arm.target->tap, opcode, data, count);
682 if (retval != ERROR_OK)
685 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
687 struct scan_field chain5_fields[3];
689 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
690 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
691 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
694 chain5_fields[1].in_value = &ready_flag;
696 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
698 retval = jtag_execute_queue();
699 if (retval == ERROR_OK)
703 LOG_ERROR("last word not transferred");
712 /** Execute an instruction via ITR while handing data into the core via DTR.
714 * The executed instruction \em must read data from DTR.
716 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
718 * \param arm11 Target state variable.
719 * \param opcode ARM opcode
720 * \param data Data word to be passed to the core via DTR
723 int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
725 return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
729 /** Execute one instruction via ITR repeatedly while
730 * reading data from the core via DTR on each execution.
732 * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
733 * is set, the ITR Ready flag is set (as seen on the previous entry to
734 * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear.
736 * The executed instruction \em must write data to DTR.
738 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
740 * \param arm11 Target state variable.
741 * \param opcode ARM opcode
742 * \param data Pointer to an array that receives the data words from the core
743 * \param count Number of data words and instruction repetitions
746 int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
748 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
750 arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
752 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
754 struct scan_field chain5_fields[3];
760 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
761 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
762 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
769 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
771 CHECK_RETVAL(jtag_execute_queue());
773 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d",
774 (unsigned) Data, Ready, nRetry);
784 if ((timeval_ms()-then) > 1000)
786 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
801 /** Execute one instruction via ITR
802 * then load r0 into DTR and read DTR from core.
804 * The first executed instruction (\p opcode) should write data to r0.
806 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
808 * \param arm11 Target state variable.
809 * \param opcode ARM opcode to write r0 with the value of interest
810 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
813 int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data)
816 retval = arm11_run_instr_no_data1(arm11, opcode);
817 if (retval != ERROR_OK)
820 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
821 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
826 /** Load data into core via DTR then move it to r0 then
827 * execute one instruction via ITR
829 * The final executed instruction (\p opcode) should read data from r0.
831 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
833 * \param arm11 Target state variable.
834 * \param opcode ARM opcode to read r0 act upon it
835 * \param data Data word that will be written to r0 before \p opcode is executed
838 int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
841 /* MRC p14,0,r0,c0,c5,0 */
842 retval = arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
843 if (retval != ERROR_OK)
846 retval = arm11_run_instr_no_data1(arm11, opcode);
847 if (retval != ERROR_OK)
853 /** Apply reads and writes to scan chain 7
855 * \see struct arm11_sc7_action
857 * \param arm11 Target state variable.
858 * \param actions A list of read and/or write instructions
859 * \param count Number of instructions in the list.
862 int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions, size_t count)
866 retval = arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
867 if (retval != ERROR_OK)
870 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
872 struct scan_field chain7_fields[3];
881 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
882 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
883 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
885 for (size_t i = 0; i < count + 1; i++)
889 nRW = actions[i].write ? 1 : 0;
890 DataOut = actions[i].value;
891 AddressOut = actions[i].address;
900 /* Timeout here so we don't get stuck. */
904 JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
905 (unsigned) AddressOut,
907 nRW ? "write" : "read");
909 arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields),
910 chain7_fields, TAP_DRPAUSE);
912 CHECK_RETVAL(jtag_execute_queue());
914 /* 'nRW' is 'Ready' on read out */
926 if ((timeval_ms()-then) > 1000)
928 LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
937 JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn);
941 if (actions[i - 1].address != AddressIn)
943 LOG_WARNING("Scan chain 7 shifted out unexpected address");
946 if (!actions[i - 1].write)
948 actions[i - 1].value = DataIn;
952 if (actions[i - 1].value != DataIn)
954 LOG_WARNING("Scan chain 7 shifted out unexpected data");
962 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
964 * \param arm11 Target state variable.
967 int arm11_sc7_clear_vbw(struct arm11_common * arm11)
969 size_t clear_bw_size = arm11->brp + 1;
970 struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
971 struct arm11_sc7_action * pos = clear_bw;
973 for (size_t i = 0; i < clear_bw_size; i++)
975 clear_bw[i].write = true;
976 clear_bw[i].value = 0;
979 for (size_t i = 0; i < arm11->brp; i++)
980 (pos++)->address = ARM11_SC7_BCR0 + i;
982 (pos++)->address = ARM11_SC7_VCR;
985 retval = arm11_sc7_run(arm11, clear_bw, clear_bw_size);
992 /** Write VCR register
994 * \param arm11 Target state variable.
995 * \param value Value to be written
997 int arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
999 struct arm11_sc7_action set_vcr;
1001 set_vcr.write = true;
1002 set_vcr.address = ARM11_SC7_VCR;
1003 set_vcr.value = value;
1005 return arm11_sc7_run(arm11, &set_vcr, 1);
1010 /** Read word from address
1012 * \param arm11 Target state variable.
1013 * \param address Memory address to be read
1014 * \param result Pointer where to store result
1017 int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result)
1020 retval = arm11_run_instr_data_prepare(arm11);
1021 if (retval != ERROR_OK)
1024 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
1025 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
1027 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
1028 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
1030 return arm11_run_instr_data_finish(arm11);
1034 /************************************************************************/
1037 * ARM11 provider for the OpenOCD implementation of the standard
1038 * architectural ARM v6/v7 "Debug Programmer's Model" (DPM).
1041 static inline struct arm11_common *dpm_to_arm11(struct arm_dpm *dpm)
1043 return container_of(dpm, struct arm11_common, dpm);
1046 static int arm11_dpm_prepare(struct arm_dpm *dpm)
1048 struct arm11_common *arm11 = dpm_to_arm11(dpm);
1050 arm11 = container_of(dpm->arm, struct arm11_common, arm);
1052 return arm11_run_instr_data_prepare(dpm_to_arm11(dpm));
1055 static int arm11_dpm_finish(struct arm_dpm *dpm)
1057 return arm11_run_instr_data_finish(dpm_to_arm11(dpm));
1060 static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm,
1061 uint32_t opcode, uint32_t data)
1063 return arm11_run_instr_data_to_core(dpm_to_arm11(dpm),
1067 static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm,
1068 uint32_t opcode, uint32_t data)
1070 return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm),
1074 static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm,
1075 uint32_t opcode, uint32_t *data)
1077 return arm11_run_instr_data_from_core(dpm_to_arm11(dpm),
1081 static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
1082 uint32_t opcode, uint32_t *data)
1084 return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm),
1088 /* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint
1089 * and watchpoint operations instead of running them right away. Since we
1090 * pre-allocated our vector, we don't need to worry about space.
1092 static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
1093 uint32_t addr, uint32_t control)
1095 struct arm11_common *arm11 = dpm_to_arm11(dpm);
1096 struct arm11_sc7_action *action;
1098 action = arm11->bpwp_actions + arm11->bpwp_n;
1100 /* Invariant: this bp/wp is disabled.
1101 * It also happens that the core is halted here, but for
1102 * DPM-based cores we don't actually care about that.
1105 action[0].write = action[1].write = true;
1107 action[0].value = addr;
1108 action[1].value = control;
1112 action[0].address = ARM11_SC7_BVR0 + index_t;
1113 action[1].address = ARM11_SC7_BCR0 + index_t;
1117 action[0].address = ARM11_SC7_WVR0 + index_t;
1118 action[1].address = ARM11_SC7_WCR0 + index_t;
1129 static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
1131 struct arm11_common *arm11 = dpm_to_arm11(dpm);
1132 struct arm11_sc7_action *action;
1134 action = arm11->bpwp_actions + arm11->bpwp_n;
1136 action[0].write = true;
1137 action[0].value = 0;
1141 action[0].address = ARM11_SC7_BCR0 + index_t;
1145 action[0].address = ARM11_SC7_WCR0 + index_t;
1156 /** Flush any pending breakpoint and watchpoint updates. */
1157 int arm11_bpwp_flush(struct arm11_common *arm11)
1164 retval = arm11_sc7_run(arm11, arm11->bpwp_actions, arm11->bpwp_n);
1170 /** Set up high-level debug module utilities */
1171 int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
1173 struct arm_dpm *dpm = &arm11->dpm;
1176 dpm->arm = &arm11->arm;
1180 dpm->prepare = arm11_dpm_prepare;
1181 dpm->finish = arm11_dpm_finish;
1183 dpm->instr_write_data_dcc = arm11_dpm_instr_write_data_dcc;
1184 dpm->instr_write_data_r0 = arm11_dpm_instr_write_data_r0;
1186 dpm->instr_read_data_dcc = arm11_dpm_instr_read_data_dcc;
1187 dpm->instr_read_data_r0 = arm11_dpm_instr_read_data_r0;
1189 dpm->bpwp_enable = arm11_bpwp_enable;
1190 dpm->bpwp_disable = arm11_bpwp_disable;
1192 retval = arm_dpm_setup(dpm);
1193 if (retval != ERROR_OK)
1196 /* alloc enough to enable all breakpoints and watchpoints at once */
1197 arm11->bpwp_actions = calloc(2 * (dpm->nbp + dpm->nwp),
1198 sizeof *arm11->bpwp_actions);
1199 if (!arm11->bpwp_actions)
1202 retval = arm_dpm_initialize(dpm);
1203 if (retval != ERROR_OK)
1206 return arm11_bpwp_flush(arm11);