1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
36 #define JTAG_DEBUG(expr ...) do {} while(0)
40 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
41 behavior of the FTDI driver IIRC was to go via RTI.
43 Conversely there may be other places in this code where the ARM11 code relies
44 on the driver to hit through RTI when coming from Update-?R.
46 tap_state_t arm11_move_pi_to_si_via_ci[] =
48 TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
52 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
54 if (cmd_queue_cur_state == TAP_IRPAUSE)
55 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
57 jtag_add_ir_scan(num_fields, fields, state);
61 tap_state_t arm11_move_pd_to_sd_via_cd[] =
63 TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
66 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
68 if (cmd_queue_cur_state == TAP_DRPAUSE)
69 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
71 jtag_add_dr_scan(num_fields, fields, state);
76 /** Code de-clutter: Construct scan_field_t to write out a value
78 * \param arm11 Target state variable.
79 * \param num_bits Length of the data field
80 * \param out_data pointer to the data that will be sent out
81 * <em>(data is read when it is added to the JTAG queue)</em>
82 * \param in_data pointer to the memory that will receive data that was clocked in
83 * <em>(data is written when the JTAG queue is executed)</em>
84 * \param field target data structure that will be initialized
86 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
88 field->tap = arm11->jtag_info.tap;
89 field->num_bits = num_bits;
90 field->out_value = out_data;
91 field->in_value = in_data;
95 /** Write JTAG instruction register
97 * \param arm11 Target state variable.
98 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
99 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
101 * \remarks This adds to the JTAG command queue but does \em not execute it.
103 void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
106 tap = arm11->jtag_info.tap;
108 if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
110 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
114 JTAG_DEBUG("IR <= 0x%02x", instr);
118 arm11_setup_field(arm11, 5, &instr, NULL, &field);
120 arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
123 /** Verify shifted out data from Scan Chain Register (SCREG)
124 * Used as parameter to scan_field_t::in_handler in
125 * arm11_add_debug_SCAN_N().
128 static void arm11_in_handler_SCAN_N(u8 *in_value)
130 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
131 u8 v = *in_value & 0x1F;
135 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
136 jtag_set_error(ERROR_FAIL);
139 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
142 /** Select and write to Scan Chain Register (SCREG)
144 * This function sets the instruction register to SCAN_N and writes
145 * the data register with the selected chain number.
147 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
149 * \param arm11 Target state variable.
150 * \param chain Scan chain that will be selected.
151 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
154 * The chain takes effect when Update-DR is passed (usually when subsequently
155 * the INTEXT/EXTEST instructions are written).
157 * \warning (Obsolete) Using this twice in a row will \em fail. The first
158 * call will end in Pause-DR. The second call, due to the IR
159 * caching, will not go through Capture-DR when shifting in the
160 * new scan chain number. As a result the verification in
161 * arm11_in_handler_SCAN_N() must fail.
163 * \remarks This adds to the JTAG command queue but does \em not execute it.
166 void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
168 JTAG_DEBUG("SCREG <= 0x%02x", chain);
170 arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
175 arm11_setup_field(arm11, 5, &chain, &tmp, &field);
177 arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
179 jtag_execute_queue_noclear();
181 arm11_in_handler_SCAN_N(tmp);
184 /** Write an instruction into the ITR register
186 * \param arm11 Target state variable.
187 * \param inst An ARM11 processor instruction/opcode.
188 * \param flag Optional parameter to retrieve the InstCompl flag
189 * (this will be written when the JTAG chain is executed).
190 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
191 * value (Run-Test/Idle).
193 * \remarks By default this ends with Run-Test/Idle state
194 * and causes the instruction to be executed. If
195 * a subsequent write to DTR is needed before
196 * executing the instruction then TAP_DRPAUSE should be
197 * passed to \p state.
199 * \remarks This adds to the JTAG command queue but does \em not execute it.
201 void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
203 JTAG_DEBUG("INST <= 0x%08x", inst);
207 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
208 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
210 arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
213 /** Read the Debug Status and Control Register (DSCR)
217 * \param arm11 Target state variable.
218 * \return DSCR content
220 * \remarks This is a stand-alone function that executes the JTAG command queue.
222 int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
224 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
226 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
229 scan_field_t chain1_field;
231 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
233 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
235 CHECK_RETVAL(jtag_execute_queue());
237 if (arm11->last_dscr != dscr)
238 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
240 arm11->last_dscr = dscr;
247 /** Write the Debug Status and Control Register (DSCR)
251 * \param arm11 Target state variable.
252 * \param dscr DSCR content
254 * \remarks This is a stand-alone function that executes the JTAG command queue.
256 int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
258 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
260 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
262 scan_field_t chain1_field;
264 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
266 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
268 CHECK_RETVAL(jtag_execute_queue());
270 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
272 arm11->last_dscr = dscr;
279 /** Get the debug reason from Debug Status and Control Register (DSCR)
281 * \param dscr DSCR value to analyze
282 * \return Debug reason
285 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
287 switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
289 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
290 LOG_INFO("Debug entry: JTAG HALT");
291 return DBG_REASON_DBGRQ;
293 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
294 LOG_INFO("Debug entry: breakpoint");
295 return DBG_REASON_BREAKPOINT;
297 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
298 LOG_INFO("Debug entry: watchpoint");
299 return DBG_REASON_WATCHPOINT;
301 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
302 LOG_INFO("Debug entry: BKPT instruction");
303 return DBG_REASON_BREAKPOINT;
305 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
306 LOG_INFO("Debug entry: EDBGRQ signal");
307 return DBG_REASON_DBGRQ;
309 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
310 LOG_INFO("Debug entry: VCR vector catch");
311 return DBG_REASON_BREAKPOINT;
314 LOG_INFO("Debug entry: unknown");
315 return DBG_REASON_DBGRQ;
321 /** Prepare the stage for ITR/DTR operations
322 * from the arm11_run_instr... group of functions.
324 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
325 * around a block of arm11_run_instr_... calls.
327 * Select scan chain 5 to allow quick access to DTR. When scan
328 * chain 4 is needed to put in a register the ITRSel instruction
329 * shortcut is used instead of actually changing the Scan_N
332 * \param arm11 Target state variable.
335 void arm11_run_instr_data_prepare(arm11_common_t * arm11)
337 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
340 /** Cleanup after ITR/DTR operations
341 * from the arm11_run_instr... group of functions
343 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
344 * around a block of arm11_run_instr_... calls.
346 * Any IDLE can lead to an instruction execution when
347 * scan chains 4 or 5 are selected and the IR holds
348 * INTEST or EXTEST. So we must disable that before
349 * any following activities lead to an IDLE.
351 * \param arm11 Target state variable.
354 void arm11_run_instr_data_finish(arm11_common_t * arm11)
356 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
360 /** Execute one or multiple instructions via ITR
362 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
364 * \param arm11 Target state variable.
365 * \param opcode Pointer to sequence of ARM opcodes
366 * \param count Number of opcodes to execute
369 int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
371 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
375 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
381 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
383 CHECK_RETVAL(jtag_execute_queue());
393 /** Execute one instruction via ITR
395 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
397 * \param arm11 Target state variable.
398 * \param opcode ARM opcode
401 void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
403 arm11_run_instr_no_data(arm11, &opcode, 1);
407 /** Execute one instruction via ITR repeatedly while
408 * passing data to the core via DTR on each execution.
410 * The executed instruction \em must read data from DTR.
412 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
414 * \param arm11 Target state variable.
415 * \param opcode ARM opcode
416 * \param data Pointer to the data words to be passed to the core
417 * \param count Number of data words and instruction repetitions
420 int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
422 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
424 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
426 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
428 scan_field_t chain5_fields[3];
434 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
435 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
436 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
444 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
446 CHECK_RETVAL(jtag_execute_queue());
448 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
455 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
461 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
463 CHECK_RETVAL(jtag_execute_queue());
465 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
472 /** JTAG path for arm11_run_instr_data_to_core_noack
474 * The repeated TAP_IDLE's do not cause a repeated execution
475 * if passed without leaving the state.
477 * Since this is more than 7 bits (adjustable via adding more
478 * TAP_IDLE's) it produces an artificial delay in the lower
479 * layer (FT2232) that is long enough to finish execution on
480 * the core but still shorter than any manually inducible delays.
482 * To disable this code, try "memwrite burst false"
485 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
487 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
492 /** Execute one instruction via ITR repeatedly while
493 * passing data to the core via DTR on each execution.
495 * No Ready check during transmission.
497 * The executed instruction \em must read data from DTR.
499 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
501 * \param arm11 Target state variable.
502 * \param opcode ARM opcode
503 * \param data Pointer to the data words to be passed to the core
504 * \param count Number of data words and instruction repetitions
507 int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
509 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
511 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
513 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
515 scan_field_t chain5_fields[3];
517 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
518 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
519 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
521 u8 Readies[count + 1];
522 u8 * ReadyPos = Readies;
526 chain5_fields[0].out_value = (void *)(data++);
527 chain5_fields[1].in_value = ReadyPos++;
531 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
532 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
533 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
537 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
541 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
543 chain5_fields[0].out_value = 0;
544 chain5_fields[1].in_value = ReadyPos++;
546 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
548 CHECK_RETVAL(jtag_execute_queue());
550 size_t error_count = 0;
553 for (i = 0; i < asizeof(Readies); i++)
562 LOG_ERROR("Transfer errors " ZU, error_count);
568 /** Execute an instruction via ITR while handing data into the core via DTR.
570 * The executed instruction \em must read data from DTR.
572 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
574 * \param arm11 Target state variable.
575 * \param opcode ARM opcode
576 * \param data Data word to be passed to the core via DTR
579 int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
581 return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
585 /** Execute one instruction via ITR repeatedly while
586 * reading data from the core via DTR on each execution.
588 * The executed instruction \em must write data to DTR.
590 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
592 * \param arm11 Target state variable.
593 * \param opcode ARM opcode
594 * \param data Pointer to an array that receives the data words from the core
595 * \param count Number of data words and instruction repetitions
598 int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
600 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
602 arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
604 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
606 scan_field_t chain5_fields[3];
612 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
613 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
614 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
620 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
622 CHECK_RETVAL(jtag_execute_queue());
624 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
634 /** Execute one instruction via ITR
635 * then load r0 into DTR and read DTR from core.
637 * The first executed instruction (\p opcode) should write data to r0.
639 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
641 * \param arm11 Target state variable.
642 * \param opcode ARM opcode to write r0 with the value of interest
643 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
646 void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
648 arm11_run_instr_no_data1(arm11, opcode);
650 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
651 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
654 /** Load data into core via DTR then move it to r0 then
655 * execute one instruction via ITR
657 * The final executed instruction (\p opcode) should read data from r0.
659 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
661 * \param arm11 Target state variable.
662 * \param opcode ARM opcode to read r0 act upon it
663 * \param data Data word that will be written to r0 before \p opcode is executed
666 void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
668 /* MRC p14,0,r0,c0,c5,0 */
669 arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
671 arm11_run_instr_no_data1(arm11, opcode);
674 /** Apply reads and writes to scan chain 7
676 * \see arm11_sc7_action_t
678 * \param arm11 Target state variable.
679 * \param actions A list of read and/or write instructions
680 * \param count Number of instructions in the list.
683 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
685 arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
687 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
689 scan_field_t chain7_fields[3];
698 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
699 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
700 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
703 for (i = 0; i < count + 1; i++)
707 nRW = actions[i].write ? 1 : 0;
708 DataOut = actions[i].value;
709 AddressOut = actions[i].address;
720 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
722 arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
724 CHECK_RETVAL(jtag_execute_queue());
726 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
728 while (!Ready); /* 'nRW' is 'Ready' on read out */
732 if (actions[i - 1].address != AddressIn)
734 LOG_WARNING("Scan chain 7 shifted out unexpected address");
737 if (!actions[i - 1].write)
739 actions[i - 1].value = DataIn;
743 if (actions[i - 1].value != DataIn)
745 LOG_WARNING("Scan chain 7 shifted out unexpected data");
752 for (i = 0; i < count; i++)
754 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
760 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
762 * \param arm11 Target state variable.
765 void arm11_sc7_clear_vbw(arm11_common_t * arm11)
767 arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
768 arm11_sc7_action_t * pos = clear_bw;
771 for (i = 0; i < asizeof(clear_bw); i++)
773 clear_bw[i].write = true;
774 clear_bw[i].value = 0;
778 for (i = 0; i < arm11->brp; i++)
779 (pos++)->address = ARM11_SC7_BCR0 + i;
783 for (i = 0; i < arm11->wrp; i++)
784 (pos++)->address = ARM11_SC7_WCR0 + i;
787 (pos++)->address = ARM11_SC7_VCR;
789 arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
792 /** Write VCR register
794 * \param arm11 Target state variable.
795 * \param value Value to be written
797 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
799 arm11_sc7_action_t set_vcr;
801 set_vcr.write = true;
802 set_vcr.address = ARM11_SC7_VCR;
803 set_vcr.value = value;
806 arm11_sc7_run(arm11, &set_vcr, 1);
811 /** Read word from address
813 * \param arm11 Target state variable.
814 * \param address Memory address to be read
815 * \param result Pointer where to store result
818 int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
820 arm11_run_instr_data_prepare(arm11);
822 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
823 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
825 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
826 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
828 arm11_run_instr_data_finish(arm11);