1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
36 #define JTAG_DEBUG(expr ...) do {} while(0)
39 tap_state_t arm11_move_pi_to_si_via_ci[] =
41 TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
45 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
47 if (cmd_queue_cur_state == TAP_IRPAUSE)
48 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
50 jtag_add_ir_scan(num_fields, fields, state);
54 tap_state_t arm11_move_pd_to_sd_via_cd[] =
56 TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
59 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
61 if (cmd_queue_cur_state == TAP_DRPAUSE)
62 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
64 jtag_add_dr_scan(num_fields, fields, state);
69 /** Code de-clutter: Construct scan_field_t to write out a value
71 * \param arm11 Target state variable.
72 * \param num_bits Length of the data field
73 * \param out_data pointer to the data that will be sent out
74 * <em>(data is read when it is added to the JTAG queue)</em>
75 * \param in_data pointer to the memory that will receive data that was clocked in
76 * <em>(data is written when the JTAG queue is executed)</em>
77 * \param field target data structure that will be initialized
79 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
81 field->tap = arm11->jtag_info.tap;
82 field->num_bits = num_bits;
83 field->out_mask = NULL;
84 field->in_check_mask = NULL;
85 field->in_check_value = NULL;
86 field->in_handler = NULL;
87 field->in_handler_priv = NULL;
89 field->out_value = out_data;
90 field->in_value = in_data;
94 /** Write JTAG instruction register
96 * \param arm11 Target state variable.
97 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
98 * \param state Pass the final TAP state or -1 for the default value (Pause-IR).
100 * \remarks This adds to the JTAG command queue but does \em not execute it.
102 void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
105 tap = arm11->jtag_info.tap;
107 /* FIX!!!! error is logged, but not propagated back up the call stack... */
108 LOG_ERROR( "tap is null here! This is bad!");
112 if (buf_get_u32(tap->cur_instr, 0, 5) == instr){
113 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
117 JTAG_DEBUG("IR <= 0x%02x", instr);
121 arm11_setup_field(arm11, 5, &instr, NULL, &field);
123 arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_IRPAUSE : state);
126 /** Verify shifted out data from Scan Chain Register (SCREG)
127 * Used as parameter to scan_field_t::in_handler in
128 * arm11_add_debug_SCAN_N().
131 static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
133 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
134 u8 v = *in_value & 0x1F;
138 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
142 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
146 /** Select and write to Scan Chain Register (SCREG)
148 * This function sets the instruction register to SCAN_N and writes
149 * the data register with the selected chain number.
151 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
153 * \param arm11 Target state variable.
154 * \param chain Scan chain that will be selected.
155 * \param state Pass the final TAP state or -1 for the default
158 * The chain takes effect when Update-DR is passed (usually when subsequently
159 * the INTEXT/EXTEST instructions are written).
161 * \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
162 * in Pause-DR. The second call, due to the IR caching, will not
163 * go through Capture-DR when shifting in the new scan chain number.
164 * As a result the verification in arm11_in_handler_SCAN_N() must
167 * \remarks This adds to the JTAG command queue but does \em not execute it.
170 void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
172 JTAG_DEBUG("SCREG <= 0x%02x", chain);
174 arm11_add_IR(arm11, ARM11_SCAN_N, -1);
178 arm11_setup_field(arm11, 5, &chain, NULL, &field);
180 field.in_handler = arm11_in_handler_SCAN_N;
182 arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_DRPAUSE : state);
185 /** Write an instruction into the ITR register
187 * \param arm11 Target state variable.
188 * \param inst An ARM11 processor instruction/opcode.
189 * \param flag Optional parameter to retrieve the InstCompl flag
190 * (this will be written when the JTAG chain is executed).
191 * \param state Pass the final TAP state or -1 for the default
192 * value (Run-Test/Idle).
194 * \remarks By default this ends with Run-Test/Idle state
195 * and causes the instruction to be executed. If
196 * a subsequent write to DTR is needed before
197 * executing the instruction then TAP_DRPAUSE should be
198 * passed to \p state.
200 * \remarks This adds to the JTAG command queue but does \em not execute it.
202 void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
204 JTAG_DEBUG("INST <= 0x%08x", inst);
208 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
209 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
211 arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_IDLE : state);
214 /** Read the Debug Status and Control Register (DSCR)
218 * \param arm11 Target state variable.
219 * \return DSCR content
221 * \remarks This is a stand-alone function that executes the JTAG command queue.
223 u32 arm11_read_DSCR(arm11_common_t * arm11)
225 arm11_add_debug_SCAN_N(arm11, 0x01, -1);
227 arm11_add_IR(arm11, ARM11_INTEST, -1);
230 scan_field_t chain1_field;
232 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
234 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
236 jtag_execute_queue();
238 if (arm11->last_dscr != dscr)
239 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
241 arm11->last_dscr = dscr;
246 /** Write the Debug Status and Control Register (DSCR)
250 * \param arm11 Target state variable.
251 * \param dscr DSCR content
253 * \remarks This is a stand-alone function that executes the JTAG command queue.
255 void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
257 arm11_add_debug_SCAN_N(arm11, 0x01, -1);
259 arm11_add_IR(arm11, ARM11_EXTEST, -1);
261 scan_field_t chain1_field;
263 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
265 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
267 jtag_execute_queue();
269 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
271 arm11->last_dscr = dscr;
276 /** Get the debug reason from Debug Status and Control Register (DSCR)
278 * \param dscr DSCR value to analyze
279 * \return Debug reason
282 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
284 switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
286 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
287 LOG_INFO("Debug entry: JTAG HALT");
288 return DBG_REASON_DBGRQ;
290 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
291 LOG_INFO("Debug entry: breakpoint");
292 return DBG_REASON_BREAKPOINT;
294 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
295 LOG_INFO("Debug entry: watchpoint");
296 return DBG_REASON_WATCHPOINT;
298 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
299 LOG_INFO("Debug entry: BKPT instruction");
300 return DBG_REASON_BREAKPOINT;
302 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
303 LOG_INFO("Debug entry: EDBGRQ signal");
304 return DBG_REASON_DBGRQ;
306 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
307 LOG_INFO("Debug entry: VCR vector catch");
308 return DBG_REASON_BREAKPOINT;
311 LOG_INFO("Debug entry: unknown");
312 return DBG_REASON_DBGRQ;
318 /** Prepare the stage for ITR/DTR operations
319 * from the arm11_run_instr... group of functions.
321 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
322 * around a block of arm11_run_instr_... calls.
324 * Select scan chain 5 to allow quick access to DTR. When scan
325 * chain 4 is needed to put in a register the ITRSel instruction
326 * shortcut is used instead of actually changing the Scan_N
329 * \param arm11 Target state variable.
332 void arm11_run_instr_data_prepare(arm11_common_t * arm11)
334 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
337 /** Cleanup after ITR/DTR operations
338 * from the arm11_run_instr... group of functions
340 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
341 * around a block of arm11_run_instr_... calls.
343 * Any IDLE can lead to an instruction execution when
344 * scan chains 4 or 5 are selected and the IR holds
345 * INTEST or EXTEST. So we must disable that before
346 * any following activities lead to an IDLE.
348 * \param arm11 Target state variable.
351 void arm11_run_instr_data_finish(arm11_common_t * arm11)
353 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
357 /** Execute one or multiple instructions via ITR
359 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
361 * \param arm11 Target state variable.
362 * \param opcode Pointer to sequence of ARM opcodes
363 * \param count Number of opcodes to execute
366 void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
368 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
372 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
378 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
380 jtag_execute_queue();
388 /** Execute one instruction via ITR
390 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
392 * \param arm11 Target state variable.
393 * \param opcode ARM opcode
396 void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
398 arm11_run_instr_no_data(arm11, &opcode, 1);
402 /** Execute one instruction via ITR repeatedly while
403 * passing data to the core via DTR on each execution.
405 * The executed instruction \em must read data from DTR.
407 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
409 * \param arm11 Target state variable.
410 * \param opcode ARM opcode
411 * \param data Pointer to the data words to be passed to the core
412 * \param count Number of data words and instruction repetitions
415 void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
417 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
419 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
421 arm11_add_IR(arm11, ARM11_EXTEST, -1);
423 scan_field_t chain5_fields[3];
429 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
430 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
431 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
439 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
440 jtag_execute_queue();
442 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
449 arm11_add_IR(arm11, ARM11_INTEST, -1);
455 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
456 jtag_execute_queue();
458 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
463 /** JTAG path for arm11_run_instr_data_to_core_noack
465 * The repeated TAP_IDLE's do not cause a repeated execution
466 * if passed without leaving the state.
468 * Since this is more than 7 bits (adjustable via adding more
469 * TAP_IDLE's) it produces an artificial delay in the lower
470 * layer (FT2232) that is long enough to finish execution on
471 * the core but still shorter than any manually inducible delays.
474 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
476 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
481 /** Execute one instruction via ITR repeatedly while
482 * passing data to the core via DTR on each execution.
484 * No Ready check during transmission.
486 * The executed instruction \em must read data from DTR.
488 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
490 * \param arm11 Target state variable.
491 * \param opcode ARM opcode
492 * \param data Pointer to the data words to be passed to the core
493 * \param count Number of data words and instruction repetitions
496 void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
498 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
500 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
502 arm11_add_IR(arm11, ARM11_EXTEST, -1);
504 scan_field_t chain5_fields[3];
506 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
507 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
508 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
510 u8 Readies[count + 1];
511 u8 * ReadyPos = Readies;
515 chain5_fields[0].out_value = (void *)(data++);
516 chain5_fields[1].in_value = ReadyPos++;
520 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
521 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
522 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
526 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
530 arm11_add_IR(arm11, ARM11_INTEST, -1);
532 chain5_fields[0].out_value = 0;
533 chain5_fields[1].in_value = ReadyPos++;
535 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
537 jtag_execute_queue();
539 size_t error_count = 0;
542 for (i = 0; i < asizeof(Readies); i++)
551 LOG_ERROR("Transfer errors " ZU, error_count);
555 /** Execute an instruction via ITR while handing data into the core via DTR.
557 * The executed instruction \em must read data from DTR.
559 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
561 * \param arm11 Target state variable.
562 * \param opcode ARM opcode
563 * \param data Data word to be passed to the core via DTR
566 void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
568 arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
572 /** Execute one instruction via ITR repeatedly while
573 * reading data from the core via DTR on each execution.
575 * The executed instruction \em must write data to DTR.
577 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
579 * \param arm11 Target state variable.
580 * \param opcode ARM opcode
581 * \param data Pointer to an array that receives the data words from the core
582 * \param count Number of data words and instruction repetitions
585 void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
587 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
589 arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
591 arm11_add_IR(arm11, ARM11_INTEST, -1);
593 scan_field_t chain5_fields[3];
599 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
600 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
601 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
607 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
608 jtag_execute_queue();
610 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
618 /** Execute one instruction via ITR
619 * then load r0 into DTR and read DTR from core.
621 * The first executed instruction (\p opcode) should write data to r0.
623 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
625 * \param arm11 Target state variable.
626 * \param opcode ARM opcode to write r0 with the value of interest
627 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
630 void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
632 arm11_run_instr_no_data1(arm11, opcode);
634 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
635 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
638 /** Load data into core via DTR then move it to r0 then
639 * execute one instruction via ITR
641 * The final executed instruction (\p opcode) should read data from r0.
643 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
645 * \param arm11 Target state variable.
646 * \param opcode ARM opcode to read r0 act upon it
647 * \param data Data word that will be written to r0 before \p opcode is executed
650 void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
652 /* MRC p14,0,r0,c0,c5,0 */
653 arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
655 arm11_run_instr_no_data1(arm11, opcode);
658 /** Apply reads and writes to scan chain 7
660 * \see arm11_sc7_action_t
662 * \param arm11 Target state variable.
663 * \param actions A list of read and/or write instructions
664 * \param count Number of instructions in the list.
667 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
669 arm11_add_debug_SCAN_N(arm11, 0x07, -1);
671 arm11_add_IR(arm11, ARM11_EXTEST, -1);
673 scan_field_t chain7_fields[3];
682 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
683 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
684 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
687 for (i = 0; i < count + 1; i++)
691 nRW = actions[i].write ? 1 : 0;
692 DataOut = actions[i].value;
693 AddressOut = actions[i].address;
704 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
706 arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
707 jtag_execute_queue();
709 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
711 while (!Ready); /* 'nRW' is 'Ready' on read out */
715 if (actions[i - 1].address != AddressIn)
717 LOG_WARNING("Scan chain 7 shifted out unexpected address");
720 if (!actions[i - 1].write)
722 actions[i - 1].value = DataIn;
726 if (actions[i - 1].value != DataIn)
728 LOG_WARNING("Scan chain 7 shifted out unexpected data");
735 for (i = 0; i < count; i++)
737 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
741 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
743 * \param arm11 Target state variable.
746 void arm11_sc7_clear_vbw(arm11_common_t * arm11)
748 arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
749 arm11_sc7_action_t * pos = clear_bw;
752 for (i = 0; i < asizeof(clear_bw); i++)
754 clear_bw[i].write = true;
755 clear_bw[i].value = 0;
759 for (i = 0; i < arm11->brp; i++)
760 (pos++)->address = ARM11_SC7_BCR0 + i;
764 for (i = 0; i < arm11->wrp; i++)
765 (pos++)->address = ARM11_SC7_WCR0 + i;
768 (pos++)->address = ARM11_SC7_VCR;
770 arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
773 /** Write VCR register
775 * \param arm11 Target state variable.
776 * \param value Value to be written
778 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
780 arm11_sc7_action_t set_vcr;
782 set_vcr.write = true;
783 set_vcr.address = ARM11_SC7_VCR;
784 set_vcr.value = value;
787 arm11_sc7_run(arm11, &set_vcr, 1);
792 /** Read word from address
794 * \param arm11 Target state variable.
795 * \param address Memory address to be read
796 * \param result Pointer where to store result
799 void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
801 arm11_run_instr_data_prepare(arm11);
803 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
804 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
806 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
807 arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
809 arm11_run_instr_data_finish(arm11);