1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
32 #define JTAG_DEBUG(expr ...) \
34 log_printf (LOG_DEBUG, __FILE__, __LINE__, __FUNCTION__, expr); \
37 #define JTAG_DEBUG(expr ...) \
41 enum tap_state arm11_move_pi_to_si_via_ci[] =
43 TAP_E2I, TAP_UI, TAP_SDS, TAP_SIS, TAP_CI, TAP_SI
47 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
49 if (cmd_queue_cur_state == TAP_PI)
50 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
52 return jtag_add_ir_scan(num_fields, fields, state);
55 enum tap_state arm11_move_pd_to_sd_via_cd[] =
57 TAP_E2D, TAP_UD, TAP_SDS, TAP_CD, TAP_SD
60 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state)
62 if (cmd_queue_cur_state == TAP_PD)
63 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
65 return jtag_add_dr_scan(num_fields, fields, state);
69 /** Code de-clutter: Construct scan_field_t to write out a value
71 * \param arm11 Target state variable.
72 * \param num_bits Length of the data field
73 * \param out_data pointer to the data that will be sent out
74 * <em>(data is read when it is added to the JTAG queue)</em>
75 * \param in_data pointer to the memory that will receive data that was clocked in
76 * <em>(data is written when the JTAG queue is executed)</em>
77 * \param field target data structure that will be initialized
79 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
81 field->device = arm11->jtag_info.chain_pos;
82 field->num_bits = num_bits;
83 field->out_mask = NULL;
84 field->in_check_mask = NULL;
85 field->in_check_value = NULL;
86 field->in_handler = NULL;
87 field->in_handler_priv = NULL;
89 field->out_value = out_data;
90 field->in_value = in_data;
94 /** Write JTAG instruction register
96 * \param arm11 Target state variable.
97 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
98 * \param state Pass the final TAP state or -1 for the default value (Pause-IR).
100 * \remarks This adds to the JTAG command queue but does \em not execute it.
102 void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state)
104 jtag_device_t *device = jtag_get_device(arm11->jtag_info.chain_pos);
106 if (buf_get_u32(device->cur_instr, 0, 5) == instr)
108 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
112 JTAG_DEBUG("IR <= 0x%02x", instr);
116 arm11_setup_field(arm11, 5, &instr, NULL, &field);
118 arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state);
121 /** Verify shifted out data from Scan Chain Register (SCREG)
122 * Used as parameter to scan_field_t::in_handler in
123 * arm11_add_debug_SCAN_N().
126 static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
128 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
129 u8 v = *in_value & 0x1F;
133 ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
137 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
141 /** Select and write to Scan Chain Register (SCREG)
143 * This function sets the instruction register to SCAN_N and writes
144 * the data register with the selected chain number.
146 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
148 * \param arm11 Target state variable.
149 * \param chain Scan chain that will be selected.
150 * \param state Pass the final TAP state or -1 for the default
153 * The chain takes effect when Update-DR is passed (usually when subsequently
154 * the INTEXT/EXTEST instructions are written).
156 * \warning (Obsolete) Using this twice in a row will \em fail. The first call will end
157 * in Pause-DR. The second call, due to the IR caching, will not
158 * go through Capture-DR when shifting in the new scan chain number.
159 * As a result the verification in arm11_in_handler_SCAN_N() must
162 * \remarks This adds to the JTAG command queue but does \em not execute it.
165 void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state state)
167 JTAG_DEBUG("SCREG <= 0x%02x", chain);
169 arm11_add_IR(arm11, ARM11_SCAN_N, -1);
173 arm11_setup_field(arm11, 5, &chain, NULL, &field);
175 field.in_handler = arm11_in_handler_SCAN_N;
177 arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state);
180 /** Write an instruction into the ITR register
182 * \param arm11 Target state variable.
183 * \param inst An ARM11 processor instruction/opcode.
184 * \param flag Optional parameter to retrieve the InstCompl flag
185 * (this will be written when the JTAG chain is executed).
186 * \param state Pass the final TAP state or -1 for the default
187 * value (Run-Test/Idle).
189 * \remarks By default this ends with Run-Test/Idle state
190 * and causes the instruction to be executed. If
191 * a subsequent write to DTR is needed before
192 * executing the instruction then TAP_PD should be
193 * passed to \p state.
195 * \remarks This adds to the JTAG command queue but does \em not execute it.
197 void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_state state)
199 JTAG_DEBUG("INST <= 0x%08x", inst);
203 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
204 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
206 arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state);
209 /** Read the Debug Status and Control Register (DSCR)
213 * \param arm11 Target state variable.
214 * \return DSCR content
216 * \remarks This is a stand-alone function that executes the JTAG command queue.
218 u32 arm11_read_DSCR(arm11_common_t * arm11)
220 arm11_add_debug_SCAN_N(arm11, 0x01, -1);
222 arm11_add_IR(arm11, ARM11_INTEST, -1);
225 scan_field_t chain1_field;
227 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
229 arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
231 jtag_execute_queue();
233 if (arm11->last_dscr != dscr)
234 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
236 arm11->last_dscr = dscr;
241 /** Write the Debug Status and Control Register (DSCR)
245 * \param arm11 Target state variable.
246 * \param dscr DSCR content
248 * \remarks This is a stand-alone function that executes the JTAG command queue.
250 void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
252 arm11_add_debug_SCAN_N(arm11, 0x01, -1);
254 arm11_add_IR(arm11, ARM11_EXTEST, -1);
256 scan_field_t chain1_field;
258 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
260 arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD);
262 jtag_execute_queue();
264 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
266 arm11->last_dscr = dscr;
271 /** Get the debug reason from Debug Status and Control Register (DSCR)
273 * \param dscr DSCR value to analyze
274 * \return Debug reason
277 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
279 switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
281 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT: return DBG_REASON_DBGRQ;
282 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT: return DBG_REASON_BREAKPOINT;
283 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT: return DBG_REASON_WATCHPOINT;
284 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION: return DBG_REASON_BREAKPOINT;
285 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ: return DBG_REASON_DBGRQ;
286 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH: return DBG_REASON_BREAKPOINT;
289 return DBG_REASON_DBGRQ;
295 /** Prepare the stage for ITR/DTR operations
296 * from the arm11_run_instr... group of functions.
298 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
299 * around a block of arm11_run_instr_... calls.
301 * Select scan chain 5 to allow quick access to DTR. When scan
302 * chain 4 is needed to put in a register the ITRSel instruction
303 * shortcut is used instead of actually changing the Scan_N
306 * \param arm11 Target state variable.
309 void arm11_run_instr_data_prepare(arm11_common_t * arm11)
311 arm11_add_debug_SCAN_N(arm11, 0x05, -1);
314 /** Cleanup after ITR/DTR operations
315 * from the arm11_run_instr... group of functions
317 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
318 * around a block of arm11_run_instr_... calls.
320 * Any RTI can lead to an instruction execution when
321 * scan chains 4 or 5 are selected and the IR holds
322 * INTEST or EXTEST. So we must disable that before
323 * any following activities lead to an RTI.
325 * \param arm11 Target state variable.
328 void arm11_run_instr_data_finish(arm11_common_t * arm11)
330 arm11_add_debug_SCAN_N(arm11, 0x00, -1);
334 /** Execute one or multiple instructions via ITR
336 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
338 * \param arm11 Target state variable.
339 * \param opcode Pointer to sequence of ARM opcodes
340 * \param count Number of opcodes to execute
343 void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
345 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
349 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI);
355 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD);
357 jtag_execute_queue();
365 /** Execute one instruction via ITR
367 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
369 * \param arm11 Target state variable.
370 * \param opcode ARM opcode
373 void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
375 arm11_run_instr_no_data(arm11, &opcode, 1);
379 /** Execute one instruction via ITR repeatedly while
380 * passing data to the core via DTR on each execution.
382 * The executed instruction \em must read data from DTR.
384 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
386 * \param arm11 Target state variable.
387 * \param opcode ARM opcode
388 * \param data Pointer to the data words to be passed to the core
389 * \param count Number of data words and instruction repetitions
392 void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
394 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
396 arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
398 arm11_add_IR(arm11, ARM11_EXTEST, -1);
400 scan_field_t chain5_fields[3];
406 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
407 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
408 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
416 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI);
417 jtag_execute_queue();
419 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
426 arm11_add_IR(arm11, ARM11_INTEST, -1);
432 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
433 jtag_execute_queue();
435 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
440 /** JTAG path for arm11_run_instr_data_to_core_noack
442 * The repeated TAP_RTI's do not cause a repeated execution
443 * if passed without leaving the state.
445 * Since this is more than 7 bits (adjustable via adding more
446 * TAP_RTI's) it produces an artificial delay in the lower
447 * layer (FT2232) that is long enough to finish execution on
448 * the core but still shorter than any manually inducible delays.
451 enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] =
453 TAP_E2D, TAP_UD, TAP_RTI, TAP_RTI, TAP_RTI, TAP_SDS, TAP_CD, TAP_SD
458 /** Execute one instruction via ITR repeatedly while
459 * passing data to the core via DTR on each execution.
461 * No Ready check during transmission.
463 * The executed instruction \em must read data from DTR.
465 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
467 * \param arm11 Target state variable.
468 * \param opcode ARM opcode
469 * \param data Pointer to the data words to be passed to the core
470 * \param count Number of data words and instruction repetitions
473 void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
475 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
477 arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD);
479 arm11_add_IR(arm11, ARM11_EXTEST, -1);
481 scan_field_t chain5_fields[3];
483 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
484 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
485 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
487 u8 Readies[count + 1];
488 u8 * ReadyPos = Readies;
492 chain5_fields[0].out_value = (void *)(data++);
493 chain5_fields[1].in_value = ReadyPos++;
497 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_PD);
498 jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay),
499 arm11_MOVE_PD_RTI_PD_with_delay);
503 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_RTI);
507 arm11_add_IR(arm11, ARM11_INTEST, -1);
509 chain5_fields[0].out_value = 0;
510 chain5_fields[1].in_value = ReadyPos++;
512 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD);
514 jtag_execute_queue();
516 size_t error_count = 0;
519 for (i = 0; i < asizeof(Readies); i++)
528 ERROR("Transfer errors %d", error_count);
532 /** Execute an instruction via ITR while handing data into the core via DTR.
534 * The executed instruction \em must read data from DTR.
536 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
538 * \param arm11 Target state variable.
539 * \param opcode ARM opcode
540 * \param data Data word to be passed to the core via DTR
543 void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
545 arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
549 /** Execute one instruction via ITR repeatedly while
550 * reading data from the core via DTR on each execution.
552 * The executed instruction \em must write data to DTR.
554 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
556 * \param arm11 Target state variable.
557 * \param opcode ARM opcode
558 * \param data Pointer to an array that receives the data words from the core
559 * \param count Number of data words and instruction repetitions
562 void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
564 arm11_add_IR(arm11, ARM11_ITRSEL, -1);
566 arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI);
568 arm11_add_IR(arm11, ARM11_INTEST, -1);
570 scan_field_t chain5_fields[3];
576 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
577 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
578 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
584 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD);
585 jtag_execute_queue();
587 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
595 /** Execute one instruction via ITR
596 * then load r0 into DTR and read DTR from core.
598 * The first executed instruction (\p opcode) should write data to r0.
600 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
602 * \param arm11 Target state variable.
603 * \param opcode ARM opcode to write r0 with the value of interest
604 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
607 void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
609 arm11_run_instr_no_data1(arm11, opcode);
611 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
612 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
615 /** Load data into core via DTR then move it to r0 then
616 * execute one instruction via ITR
618 * The final executed instruction (\p opcode) should read data from r0.
620 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
622 * \param arm11 Target state variable.
623 * \param opcode ARM opcode to read r0 act upon it
624 * \param data Data word that will be written to r0 before \p opcode is executed
627 void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
629 /* MRC p14,0,r0,c0,c5,0 */
630 arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
632 arm11_run_instr_no_data1(arm11, opcode);
635 /** Apply reads and writes to scan chain 7
637 * \see arm11_sc7_action_t
639 * \param arm11 Target state variable.
640 * \param actions A list of read and/or write instructions
641 * \param count Number of instructions in the list.
644 void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
646 arm11_add_debug_SCAN_N(arm11, 0x07, -1);
648 arm11_add_IR(arm11, ARM11_EXTEST, -1);
650 scan_field_t chain7_fields[3];
659 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
660 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
661 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
664 for (i = 0; i < count + 1; i++)
668 nRW = actions[i].write ? 1 : 0;
669 DataOut = actions[i].value;
670 AddressOut = actions[i].address;
681 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
683 arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD);
684 jtag_execute_queue();
686 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
688 while (!Ready); /* 'nRW' is 'Ready' on read out */
692 if (actions[i - 1].address != AddressIn)
694 WARNING("Scan chain 7 shifted out unexpected address");
697 if (!actions[i - 1].write)
699 actions[i - 1].value = DataIn;
703 if (actions[i - 1].value != DataIn)
705 WARNING("Scan chain 7 shifted out unexpected data");
712 for (i = 0; i < count; i++)
714 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
718 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
720 * \param arm11 Target state variable.
723 void arm11_sc7_clear_vbw(arm11_common_t * arm11)
725 arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
726 arm11_sc7_action_t * pos = clear_bw;
729 for (i = 0; i < asizeof(clear_bw); i++)
731 clear_bw[i].write = true;
732 clear_bw[i].value = 0;
736 for (i = 0; i < arm11->brp; i++)
737 (pos++)->address = ARM11_SC7_BCR0 + i;
741 for (i = 0; i < arm11->wrp; i++)
742 (pos++)->address = ARM11_SC7_WCR0 + i;
745 (pos++)->address = ARM11_SC7_VCR;
748 /** Write VCR register
750 * \param arm11 Target state variable.
751 * \param value Value to be written
753 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
755 arm11_sc7_action_t set_vcr;
758 set_vcr.address = ARM11_SC7_VCR;
759 set_vcr.value = value;
762 arm11_sc7_run(arm11, &set_vcr, 1);
767 /** Read word from address
769 * \param arm11 Target state variable.
770 * \param address Memory address to be read
771 * \param result Pointer where to store result
774 void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
776 arm11_run_instr_data_prepare(arm11);
778 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
779 arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
781 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
782 arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
784 arm11_run_instr_data_finish(arm11);