1 /***************************************************************************
2 * Copyright (C) 2008 digenius technology GmbH. *
4 * Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
34 #define JTAG_DEBUG(expr ...) DEBUG(expr)
36 #define JTAG_DEBUG(expr ...) do {} while(0)
40 This pathmove goes from Pause-IR to Shift-IR while avoiding RTI. The
41 behavior of the FTDI driver IIRC was to go via RTI.
43 Conversely there may be other places in this code where the ARM11 code relies
44 on the driver to hit through RTI when coming from Update-?R.
46 tap_state_t arm11_move_pi_to_si_via_ci[] =
48 TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
52 int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
54 if (cmd_queue_cur_state == TAP_IRPAUSE)
55 jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
57 jtag_add_ir_scan(num_fields, fields, state);
61 tap_state_t arm11_move_pd_to_sd_via_cd[] =
63 TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
66 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state)
68 if (cmd_queue_cur_state == TAP_DRPAUSE)
69 jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
71 jtag_add_dr_scan(num_fields, fields, state);
76 /** Code de-clutter: Construct scan_field_t to write out a value
78 * \param arm11 Target state variable.
79 * \param num_bits Length of the data field
80 * \param out_data pointer to the data that will be sent out
81 * <em>(data is read when it is added to the JTAG queue)</em>
82 * \param in_data pointer to the memory that will receive data that was clocked in
83 * <em>(data is written when the JTAG queue is executed)</em>
84 * \param field target data structure that will be initialized
86 void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
88 field->tap = arm11->jtag_info.tap;
89 field->num_bits = num_bits;
90 field->out_mask = NULL;
91 field->in_check_mask = NULL;
92 field->in_check_value = NULL;
93 field->in_handler = NULL;
94 field->in_handler_priv = NULL;
96 field->out_value = out_data;
97 field->in_value = in_data;
101 /** Write JTAG instruction register
103 * \param arm11 Target state variable.
104 * \param instr An ARM11 DBGTAP instruction. Use enum #arm11_instructions.
105 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default value (Pause-IR).
107 * \remarks This adds to the JTAG command queue but does \em not execute it.
109 void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
112 tap = arm11->jtag_info.tap;
114 if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
116 JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
120 JTAG_DEBUG("IR <= 0x%02x", instr);
124 arm11_setup_field(arm11, 5, &instr, NULL, &field);
126 arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
129 /** Verify shifted out data from Scan Chain Register (SCREG)
130 * Used as parameter to scan_field_t::in_handler in
131 * arm11_add_debug_SCAN_N().
134 static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s *field)
136 /** \todo TODO: clarify why this isnt properly masked in jtag.c jtag_read_buffer() */
137 u8 v = *in_value & 0x1F;
141 LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
145 JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
149 /** Select and write to Scan Chain Register (SCREG)
151 * This function sets the instruction register to SCAN_N and writes
152 * the data register with the selected chain number.
154 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/Cacbjhfg.html
156 * \param arm11 Target state variable.
157 * \param chain Scan chain that will be selected.
158 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
161 * The chain takes effect when Update-DR is passed (usually when subsequently
162 * the INTEXT/EXTEST instructions are written).
164 * \warning (Obsolete) Using this twice in a row will \em fail. The first
165 * call will end in Pause-DR. The second call, due to the IR
166 * caching, will not go through Capture-DR when shifting in the
167 * new scan chain number. As a result the verification in
168 * arm11_in_handler_SCAN_N() must fail.
170 * \remarks This adds to the JTAG command queue but does \em not execute it.
173 void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, tap_state_t state)
175 JTAG_DEBUG("SCREG <= 0x%02x", chain);
177 arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
181 arm11_setup_field(arm11, 5, &chain, NULL, &field);
183 field.in_handler = arm11_in_handler_SCAN_N; /* deprecated! invoke this from user code! */
185 arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
188 /** Write an instruction into the ITR register
190 * \param arm11 Target state variable.
191 * \param inst An ARM11 processor instruction/opcode.
192 * \param flag Optional parameter to retrieve the InstCompl flag
193 * (this will be written when the JTAG chain is executed).
194 * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default
195 * value (Run-Test/Idle).
197 * \remarks By default this ends with Run-Test/Idle state
198 * and causes the instruction to be executed. If
199 * a subsequent write to DTR is needed before
200 * executing the instruction then TAP_DRPAUSE should be
201 * passed to \p state.
203 * \remarks This adds to the JTAG command queue but does \em not execute it.
205 void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state)
207 JTAG_DEBUG("INST <= 0x%08x", inst);
211 arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
212 arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
214 arm11_add_dr_scan_vc(asizeof(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state);
217 /** Read the Debug Status and Control Register (DSCR)
221 * \param arm11 Target state variable.
222 * \return DSCR content
224 * \remarks This is a stand-alone function that executes the JTAG command queue.
226 int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
228 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
230 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
233 scan_field_t chain1_field;
235 arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
237 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
239 CHECK_RETVAL(jtag_execute_queue());
241 if (arm11->last_dscr != dscr)
242 JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
244 arm11->last_dscr = dscr;
251 /** Write the Debug Status and Control Register (DSCR)
255 * \param arm11 Target state variable.
256 * \param dscr DSCR content
258 * \remarks This is a stand-alone function that executes the JTAG command queue.
260 int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
262 arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
264 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
266 scan_field_t chain1_field;
268 arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
270 arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
272 CHECK_RETVAL(jtag_execute_queue());
274 JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
276 arm11->last_dscr = dscr;
283 /** Get the debug reason from Debug Status and Control Register (DSCR)
285 * \param dscr DSCR value to analyze
286 * \return Debug reason
289 enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
291 switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
293 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
294 LOG_INFO("Debug entry: JTAG HALT");
295 return DBG_REASON_DBGRQ;
297 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
298 LOG_INFO("Debug entry: breakpoint");
299 return DBG_REASON_BREAKPOINT;
301 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
302 LOG_INFO("Debug entry: watchpoint");
303 return DBG_REASON_WATCHPOINT;
305 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
306 LOG_INFO("Debug entry: BKPT instruction");
307 return DBG_REASON_BREAKPOINT;
309 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
310 LOG_INFO("Debug entry: EDBGRQ signal");
311 return DBG_REASON_DBGRQ;
313 case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
314 LOG_INFO("Debug entry: VCR vector catch");
315 return DBG_REASON_BREAKPOINT;
318 LOG_INFO("Debug entry: unknown");
319 return DBG_REASON_DBGRQ;
325 /** Prepare the stage for ITR/DTR operations
326 * from the arm11_run_instr... group of functions.
328 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
329 * around a block of arm11_run_instr_... calls.
331 * Select scan chain 5 to allow quick access to DTR. When scan
332 * chain 4 is needed to put in a register the ITRSel instruction
333 * shortcut is used instead of actually changing the Scan_N
336 * \param arm11 Target state variable.
339 void arm11_run_instr_data_prepare(arm11_common_t * arm11)
341 arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
344 /** Cleanup after ITR/DTR operations
345 * from the arm11_run_instr... group of functions
347 * Put arm11_run_instr_data_prepare() and arm11_run_instr_data_finish()
348 * around a block of arm11_run_instr_... calls.
350 * Any IDLE can lead to an instruction execution when
351 * scan chains 4 or 5 are selected and the IR holds
352 * INTEST or EXTEST. So we must disable that before
353 * any following activities lead to an IDLE.
355 * \param arm11 Target state variable.
358 void arm11_run_instr_data_finish(arm11_common_t * arm11)
360 arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
364 /** Execute one or multiple instructions via ITR
366 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
368 * \param arm11 Target state variable.
369 * \param opcode Pointer to sequence of ARM opcodes
370 * \param count Number of opcodes to execute
373 int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
375 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
379 arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
385 arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
387 CHECK_RETVAL(jtag_execute_queue());
397 /** Execute one instruction via ITR
399 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
401 * \param arm11 Target state variable.
402 * \param opcode ARM opcode
405 void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
407 arm11_run_instr_no_data(arm11, &opcode, 1);
411 /** Execute one instruction via ITR repeatedly while
412 * passing data to the core via DTR on each execution.
414 * The executed instruction \em must read data from DTR.
416 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
418 * \param arm11 Target state variable.
419 * \param opcode ARM opcode
420 * \param data Pointer to the data words to be passed to the core
421 * \param count Number of data words and instruction repetitions
424 int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
426 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
428 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
430 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
432 scan_field_t chain5_fields[3];
438 arm11_setup_field(arm11, 32, &Data, NULL, chain5_fields + 0);
439 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
440 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
448 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
450 CHECK_RETVAL(jtag_execute_queue());
452 JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
459 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
465 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
467 CHECK_RETVAL(jtag_execute_queue());
469 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
476 /** JTAG path for arm11_run_instr_data_to_core_noack
478 * The repeated TAP_IDLE's do not cause a repeated execution
479 * if passed without leaving the state.
481 * Since this is more than 7 bits (adjustable via adding more
482 * TAP_IDLE's) it produces an artificial delay in the lower
483 * layer (FT2232) that is long enough to finish execution on
484 * the core but still shorter than any manually inducible delays.
486 * To disable this code, try "memwrite burst false"
489 tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
491 TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
496 /** Execute one instruction via ITR repeatedly while
497 * passing data to the core via DTR on each execution.
499 * No Ready check during transmission.
501 * The executed instruction \em must read data from DTR.
503 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
505 * \param arm11 Target state variable.
506 * \param opcode ARM opcode
507 * \param data Pointer to the data words to be passed to the core
508 * \param count Number of data words and instruction repetitions
511 int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
513 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
515 arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE);
517 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
519 scan_field_t chain5_fields[3];
521 arm11_setup_field(arm11, 32, NULL/*&Data*/, NULL, chain5_fields + 0);
522 arm11_setup_field(arm11, 1, NULL, NULL /*&Ready*/, chain5_fields + 1);
523 arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
525 u8 Readies[count + 1];
526 u8 * ReadyPos = Readies;
530 chain5_fields[0].out_value = (void *)(data++);
531 chain5_fields[1].in_value = ReadyPos++;
535 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
536 jtag_add_pathmove(asizeof(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
537 arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
541 jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
545 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
547 chain5_fields[0].out_value = 0;
548 chain5_fields[1].in_value = ReadyPos++;
550 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
552 CHECK_RETVAL(jtag_execute_queue());
554 size_t error_count = 0;
557 for (i = 0; i < asizeof(Readies); i++)
566 LOG_ERROR("Transfer errors " ZU, error_count);
572 /** Execute an instruction via ITR while handing data into the core via DTR.
574 * The executed instruction \em must read data from DTR.
576 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
578 * \param arm11 Target state variable.
579 * \param opcode ARM opcode
580 * \param data Data word to be passed to the core via DTR
583 int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
585 return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
589 /** Execute one instruction via ITR repeatedly while
590 * reading data from the core via DTR on each execution.
592 * The executed instruction \em must write data to DTR.
594 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
596 * \param arm11 Target state variable.
597 * \param opcode ARM opcode
598 * \param data Pointer to an array that receives the data words from the core
599 * \param count Number of data words and instruction repetitions
602 int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
604 arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
606 arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE);
608 arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
610 scan_field_t chain5_fields[3];
616 arm11_setup_field(arm11, 32, NULL, &Data, chain5_fields + 0);
617 arm11_setup_field(arm11, 1, NULL, &Ready, chain5_fields + 1);
618 arm11_setup_field(arm11, 1, NULL, &nRetry, chain5_fields + 2);
624 arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
626 CHECK_RETVAL(jtag_execute_queue());
628 JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
638 /** Execute one instruction via ITR
639 * then load r0 into DTR and read DTR from core.
641 * The first executed instruction (\p opcode) should write data to r0.
643 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
645 * \param arm11 Target state variable.
646 * \param opcode ARM opcode to write r0 with the value of interest
647 * \param data Pointer to a data word that receives the value from r0 after \p opcode was executed.
650 void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 * data)
652 arm11_run_instr_no_data1(arm11, opcode);
654 /* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
655 arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
658 /** Load data into core via DTR then move it to r0 then
659 * execute one instruction via ITR
661 * The final executed instruction (\p opcode) should read data from r0.
663 * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block
665 * \param arm11 Target state variable.
666 * \param opcode ARM opcode to read r0 act upon it
667 * \param data Data word that will be written to r0 before \p opcode is executed
670 void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32 data)
672 /* MRC p14,0,r0,c0,c5,0 */
673 arm11_run_instr_data_to_core1(arm11, 0xEE100E15, data);
675 arm11_run_instr_no_data1(arm11, opcode);
678 /** Apply reads and writes to scan chain 7
680 * \see arm11_sc7_action_t
682 * \param arm11 Target state variable.
683 * \param actions A list of read and/or write instructions
684 * \param count Number of instructions in the list.
687 int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
689 arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
691 arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
693 scan_field_t chain7_fields[3];
702 arm11_setup_field(arm11, 1, &nRW, &Ready, chain7_fields + 0);
703 arm11_setup_field(arm11, 32, &DataOut, &DataIn, chain7_fields + 1);
704 arm11_setup_field(arm11, 7, &AddressOut, &AddressIn, chain7_fields + 2);
707 for (i = 0; i < count + 1; i++)
711 nRW = actions[i].write ? 1 : 0;
712 DataOut = actions[i].value;
713 AddressOut = actions[i].address;
724 JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
726 arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
728 CHECK_RETVAL(jtag_execute_queue());
730 JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
732 while (!Ready); /* 'nRW' is 'Ready' on read out */
736 if (actions[i - 1].address != AddressIn)
738 LOG_WARNING("Scan chain 7 shifted out unexpected address");
741 if (!actions[i - 1].write)
743 actions[i - 1].value = DataIn;
747 if (actions[i - 1].value != DataIn)
749 LOG_WARNING("Scan chain 7 shifted out unexpected data");
756 for (i = 0; i < count; i++)
758 JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
764 /** Clear VCR and all breakpoints and watchpoints via scan chain 7
766 * \param arm11 Target state variable.
769 void arm11_sc7_clear_vbw(arm11_common_t * arm11)
771 arm11_sc7_action_t clear_bw[arm11->brp + arm11->wrp + 1];
772 arm11_sc7_action_t * pos = clear_bw;
775 for (i = 0; i < asizeof(clear_bw); i++)
777 clear_bw[i].write = true;
778 clear_bw[i].value = 0;
782 for (i = 0; i < arm11->brp; i++)
783 (pos++)->address = ARM11_SC7_BCR0 + i;
787 for (i = 0; i < arm11->wrp; i++)
788 (pos++)->address = ARM11_SC7_WCR0 + i;
791 (pos++)->address = ARM11_SC7_VCR;
793 arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw));
796 /** Write VCR register
798 * \param arm11 Target state variable.
799 * \param value Value to be written
801 void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
803 arm11_sc7_action_t set_vcr;
805 set_vcr.write = true;
806 set_vcr.address = ARM11_SC7_VCR;
807 set_vcr.value = value;
810 arm11_sc7_run(arm11, &set_vcr, 1);
815 /** Read word from address
817 * \param arm11 Target state variable.
818 * \param address Memory address to be read
819 * \param result Pointer where to store result
822 int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
824 arm11_run_instr_data_prepare(arm11);
826 /* MRC p14,0,r0,c0,c5,0 (r0 = address) */
827 CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
829 /* LDC p14,c5,[R0],#4 (DTR = [r0]) */
830 CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
832 arm11_run_instr_data_finish(arm11);