1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include <helper/time_support.h>
29 #include "target_type.h"
31 #include "arm_opcodes.h"
35 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
36 * ARM DDI 0229C especially Chapter 9 about debug support.
40 #define _DEBUG_INSTRUCTION_EXECUTION_
43 static int arm720t_scan_cp15(struct target *target,
44 uint32_t out, uint32_t *in, int instruction, int clock)
47 struct arm720t_common *arm720t = target_to_arm720(target);
48 struct arm_jtag *jtag_info;
49 struct scan_field fields[2];
51 uint8_t instruction_buf = instruction;
53 jtag_info = &arm720t->arm7_9_common.jtag_info;
55 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
57 if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
61 if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
66 fields[0].num_bits = 1;
67 fields[0].out_value = &instruction_buf;
68 fields[0].in_value = NULL;
70 fields[1].num_bits = 32;
71 fields[1].out_value = out_buf;
72 fields[1].in_value = NULL;
76 fields[1].in_value = (uint8_t *)in;
77 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
78 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
81 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
85 jtag_add_runtest(0, TAP_DRPAUSE);
87 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
88 if ((retval = jtag_execute_queue()) != ERROR_OK)
94 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
96 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
98 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
104 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
106 /* fetch CP15 opcode */
107 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
109 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
110 /* "EXECUTE" stage (1) */
111 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
112 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
113 /* "EXECUTE" stage (2) */
114 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
115 /* "EXECUTE" stage (3), CDATA is read */
116 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
121 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
123 /* fetch CP15 opcode */
124 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
126 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
127 /* "EXECUTE" stage (1) */
128 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
129 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
130 /* "EXECUTE" stage (2) */
131 arm720t_scan_cp15(target, value, NULL, 0, 1);
132 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
137 static uint32_t arm720t_get_ttb(struct target *target)
141 arm720t_read_cp15(target, 0xee120f10, &ttb);
142 jtag_execute_queue();
149 static void arm720t_disable_mmu_caches(struct target *target,
150 int mmu, int d_u_cache, int i_cache)
152 uint32_t cp15_control;
154 /* read cp15 control register */
155 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
156 jtag_execute_queue();
159 cp15_control &= ~0x1U;
161 if (d_u_cache || i_cache)
162 cp15_control &= ~0x4U;
164 arm720t_write_cp15(target, 0xee010f10, cp15_control);
167 static void arm720t_enable_mmu_caches(struct target *target,
168 int mmu, int d_u_cache, int i_cache)
170 uint32_t cp15_control;
172 /* read cp15 control register */
173 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
174 jtag_execute_queue();
177 cp15_control |= 0x1U;
179 if (d_u_cache || i_cache)
180 cp15_control |= 0x4U;
182 arm720t_write_cp15(target, 0xee010f10, cp15_control);
185 static void arm720t_post_debug_entry(struct target *target)
187 struct arm720t_common *arm720t = target_to_arm720(target);
189 /* examine cp15 control reg */
190 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
191 jtag_execute_queue();
192 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
194 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
195 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
196 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
198 /* save i/d fault status and address register */
199 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
200 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
201 jtag_execute_queue();
204 static void arm720t_pre_restore_context(struct target *target)
206 struct arm720t_common *arm720t = target_to_arm720(target);
208 /* restore i/d fault status and address register */
209 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
210 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
213 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
214 struct arm720t_common *arm720t)
216 if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
217 command_print(cmd_ctx, "target is not an ARM720");
218 return ERROR_TARGET_INVALID;
223 static int arm720t_arch_state(struct target *target)
225 struct arm720t_common *arm720t = target_to_arm720(target);
228 static const char *state[] =
230 "disabled", "enabled"
233 armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
235 arm_arch_state(target);
236 LOG_USER("MMU: %s, Cache: %s",
237 state[arm720t->armv4_5_mmu.mmu_enabled],
238 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
243 static int arm720_mmu(struct target *target, int *enabled)
245 if (target->state != TARGET_HALTED) {
246 LOG_ERROR("%s: target not halted", __func__);
247 return ERROR_TARGET_INVALID;
250 *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
254 static int arm720_virt2phys(struct target *target,
255 uint32_t virtual, uint32_t *physical)
261 struct arm720t_common *arm720t = target_to_arm720(target);
263 uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
272 static int arm720t_read_memory(struct target *target,
273 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
276 struct arm720t_common *arm720t = target_to_arm720(target);
278 /* disable cache, but leave MMU enabled */
279 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
280 arm720t_disable_mmu_caches(target, 0, 1, 0);
282 retval = arm7_9_read_memory(target, address, size, count, buffer);
284 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
285 arm720t_enable_mmu_caches(target, 0, 1, 0);
290 static int arm720t_read_phys_memory(struct target *target,
291 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
293 struct arm720t_common *arm720t = target_to_arm720(target);
295 return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
298 static int arm720t_write_phys_memory(struct target *target,
299 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
301 struct arm720t_common *arm720t = target_to_arm720(target);
303 return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
306 static int arm720t_soft_reset_halt(struct target *target)
308 int retval = ERROR_OK;
309 struct arm720t_common *arm720t = target_to_arm720(target);
310 struct reg *dbg_stat = &arm720t->arm7_9_common
311 .eice_cache->reg_list[EICE_DBG_STAT];
312 struct arm *armv4_5 = &arm720t->arm7_9_common
315 if ((retval = target_halt(target)) != ERROR_OK)
320 long long then = timeval_ms();
322 while (!(timeout = ((timeval_ms()-then) > 1000)))
324 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
326 embeddedice_read_reg(dbg_stat);
327 if ((retval = jtag_execute_queue()) != ERROR_OK)
335 if (debug_level >= 3)
345 LOG_ERROR("Failed to halt CPU after 1 sec");
346 return ERROR_TARGET_TIMEOUT;
349 target->state = TARGET_HALTED;
351 /* SVC, ARM state, IRQ and FIQ disabled */
354 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
357 arm_set_cpsr(armv4_5, cpsr);
358 armv4_5->cpsr->dirty = 1;
360 /* start fetching from 0x0 */
361 buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
362 armv4_5->pc->dirty = 1;
363 armv4_5->pc->valid = 1;
365 arm720t_disable_mmu_caches(target, 1, 1, 1);
366 arm720t->armv4_5_mmu.mmu_enabled = 0;
367 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
368 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
370 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
378 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
380 return arm7tdmi_init_target(cmd_ctx, target);
383 /* FIXME remove forward decls */
384 static int arm720t_mrc(struct target *target, int cpnum,
385 uint32_t op1, uint32_t op2,
386 uint32_t CRn, uint32_t CRm,
388 static int arm720t_mcr(struct target *target, int cpnum,
389 uint32_t op1, uint32_t op2,
390 uint32_t CRn, uint32_t CRm,
393 static int arm720t_init_arch_info(struct target *target,
394 struct arm720t_common *arm720t, struct jtag_tap *tap)
396 struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
398 arm7_9->armv4_5_common.mrc = arm720t_mrc;
399 arm7_9->armv4_5_common.mcr = arm720t_mcr;
401 arm7tdmi_init_arch_info(target, arm7_9, tap);
403 arm720t->common_magic = ARM720T_COMMON_MAGIC;
405 arm7_9->post_debug_entry = arm720t_post_debug_entry;
406 arm7_9->pre_restore_context = arm720t_pre_restore_context;
408 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
409 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
410 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
411 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
412 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
413 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
414 arm720t->armv4_5_mmu.has_tiny_pages = 0;
415 arm720t->armv4_5_mmu.mmu_enabled = 0;
420 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
422 struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
424 arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
425 return arm720t_init_arch_info(target, arm720t, target->tap);
428 COMMAND_HANDLER(arm720t_handle_cp15_command)
431 struct target *target = get_current_target(CMD_CTX);
432 struct arm720t_common *arm720t = target_to_arm720(target);
433 struct arm_jtag *jtag_info;
435 retval = arm720t_verify_pointer(CMD_CTX, arm720t);
436 if (retval != ERROR_OK)
439 jtag_info = &arm720t->arm7_9_common.jtag_info;
441 if (target->state != TARGET_HALTED)
443 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
447 /* one or more argument, access a single register (write if second argument is given */
451 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
456 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
458 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
462 if ((retval = jtag_execute_queue()) != ERROR_OK)
467 command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
469 else if (CMD_ARGC == 2)
472 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
474 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
476 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
479 command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
486 static int arm720t_mrc(struct target *target, int cpnum,
487 uint32_t op1, uint32_t op2,
488 uint32_t CRn, uint32_t CRm,
493 LOG_ERROR("Only cp15 is supported");
498 return arm720t_read_cp15(target,
499 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
504 static int arm720t_mcr(struct target *target, int cpnum,
505 uint32_t op1, uint32_t op2,
506 uint32_t CRn, uint32_t CRm,
511 LOG_ERROR("Only cp15 is supported");
515 /* write "from" r0 */
516 return arm720t_write_cp15(target,
517 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
521 static const struct command_registration arm720t_exec_command_handlers[] = {
524 .handler = arm720t_handle_cp15_command,
525 .mode = COMMAND_EXEC,
526 /* prefer using less error-prone "arm mcr" or "arm mrc" */
527 .help = "display/modify cp15 register using ARM opcode"
529 .usage = "instruction [value]",
531 COMMAND_REGISTRATION_DONE
534 static const struct command_registration arm720t_command_handlers[] = {
536 .chain = arm7_9_command_handlers,
541 .help = "arm720t command group",
542 .chain = arm720t_exec_command_handlers,
544 COMMAND_REGISTRATION_DONE
547 /** Holds methods for ARM720 targets. */
548 struct target_type arm720t_target =
553 .arch_state = arm720t_arch_state,
556 .resume = arm7_9_resume,
559 .assert_reset = arm7_9_assert_reset,
560 .deassert_reset = arm7_9_deassert_reset,
561 .soft_reset_halt = arm720t_soft_reset_halt,
563 .get_gdb_reg_list = arm_get_gdb_reg_list,
565 .read_memory = arm720t_read_memory,
566 .write_memory = arm7_9_write_memory,
567 .read_phys_memory = arm720t_read_phys_memory,
568 .write_phys_memory = arm720t_write_phys_memory,
570 .virt2phys = arm720_virt2phys,
572 .bulk_write_memory = arm7_9_bulk_write_memory,
574 .checksum_memory = arm_checksum_memory,
575 .blank_check_memory = arm_blank_check_memory,
577 .run_algorithm = armv4_5_run_algorithm,
579 .add_breakpoint = arm7_9_add_breakpoint,
580 .remove_breakpoint = arm7_9_remove_breakpoint,
581 .add_watchpoint = arm7_9_add_watchpoint,
582 .remove_watchpoint = arm7_9_remove_watchpoint,
584 .commands = arm720t_command_handlers,
585 .target_create = arm720t_target_create,
586 .init_target = arm720t_init_target,
587 .examine = arm7_9_examine,
588 .check_reset = arm7_9_check_reset,