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1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   Copyright (C) 2009 by Ã˜yvind Harboe                                   *
6  *   oyvind.harboe@zylin.com                                               *
7  *                                                                         *
8  *   This program is free software; you can redistribute it and/or modify  *
9  *   it under the terms of the GNU General Public License as published by  *
10  *   the Free Software Foundation; either version 2 of the License, or     *
11  *   (at your option) any later version.                                   *
12  *                                                                         *
13  *   This program is distributed in the hope that it will be useful,       *
14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
16  *   GNU General Public License for more details.                          *
17  *                                                                         *
18  *   You should have received a copy of the GNU General Public License     *
19  *   along with this program; if not, write to the                         *
20  *   Free Software Foundation, Inc.,                                       *
21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
22  ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "arm720t.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
30 #include "register.h"
31 #include "arm_opcodes.h"
32
33
34 /*
35  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
36  * ARM DDI 0229C especially Chapter 9 about debug support.
37  */
38
39 #if 0
40 #define _DEBUG_INSTRUCTION_EXECUTION_
41 #endif
42
43 static int arm720t_scan_cp15(struct target *target,
44                 uint32_t out, uint32_t *in, int instruction, int clock_arg)
45 {
46         int retval;
47         struct arm720t_common *arm720t = target_to_arm720(target);
48         struct arm_jtag *jtag_info;
49         struct scan_field fields[2];
50         uint8_t out_buf[4];
51         uint8_t instruction_buf = instruction;
52
53         jtag_info = &arm720t->arm7_9_common.jtag_info;
54
55         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
56
57         if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
58         {
59                 return retval;
60         }
61         if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
62         {
63                 return retval;
64         }
65
66         fields[0].num_bits = 1;
67         fields[0].out_value = &instruction_buf;
68         fields[0].in_value = NULL;
69
70         fields[1].num_bits = 32;
71         fields[1].out_value = out_buf;
72         fields[1].in_value = NULL;
73
74         if (in)
75         {
76                 fields[1].in_value = (uint8_t *)in;
77                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
78                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
79         } else
80         {
81                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
82         }
83
84         if (clock_arg)
85                 jtag_add_runtest(0, TAP_DRPAUSE);
86
87 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
88         if ((retval = jtag_execute_queue()) != ERROR_OK)
89         {
90                 return retval;
91         }
92
93         if (in)
94                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
95         else
96                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
97 #else
98                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
99 #endif
100
101         return ERROR_OK;
102 }
103
104 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
105 {
106         /* fetch CP15 opcode */
107         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
108         /* "DECODE" stage */
109         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
110         /* "EXECUTE" stage (1) */
111         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
112         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
113         /* "EXECUTE" stage (2) */
114         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
115         /* "EXECUTE" stage (3), CDATA is read */
116         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
117
118         return ERROR_OK;
119 }
120
121 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
122 {
123         /* fetch CP15 opcode */
124         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
125         /* "DECODE" stage */
126         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
127         /* "EXECUTE" stage (1) */
128         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
129         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
130         /* "EXECUTE" stage (2) */
131         arm720t_scan_cp15(target, value, NULL, 0, 1);
132         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
133
134         return ERROR_OK;
135 }
136
137 static int arm720t_get_ttb(struct target *target, uint32_t *result)
138 {
139         uint32_t ttb = 0x0;
140
141         int retval;
142
143         retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
144         if (retval != ERROR_OK)
145                 return retval;
146         retval = jtag_execute_queue();
147         if (retval != ERROR_OK)
148                 return retval;
149
150         ttb &= 0xffffc000;
151
152         *result = ttb;
153
154         return ERROR_OK;
155 }
156
157 static int arm720t_disable_mmu_caches(struct target *target,
158                 int mmu, int d_u_cache, int i_cache)
159 {
160         uint32_t cp15_control;
161         int retval;
162
163         /* read cp15 control register */
164         retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
165         if (retval != ERROR_OK)
166                 return retval;
167         retval = jtag_execute_queue();
168         if (retval != ERROR_OK)
169                 return retval;
170
171         if (mmu)
172                 cp15_control &= ~0x1U;
173
174         if (d_u_cache || i_cache)
175                 cp15_control &= ~0x4U;
176
177         retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
178         return retval;
179 }
180
181 static int arm720t_enable_mmu_caches(struct target *target,
182                 int mmu, int d_u_cache, int i_cache)
183 {
184         uint32_t cp15_control;
185         int retval;
186
187         /* read cp15 control register */
188         retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
189         if (retval != ERROR_OK)
190                 return retval;
191         retval = jtag_execute_queue();
192         if (retval != ERROR_OK)
193                 return retval;
194
195         if (mmu)
196                 cp15_control |= 0x1U;
197
198         if (d_u_cache || i_cache)
199                 cp15_control |= 0x4U;
200
201         retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
202         return retval;
203 }
204
205 static int arm720t_post_debug_entry(struct target *target)
206 {
207         struct arm720t_common *arm720t = target_to_arm720(target);
208         int retval;
209
210         /* examine cp15 control reg */
211         retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
212         if (retval != ERROR_OK)
213                 return retval;
214         retval = jtag_execute_queue();
215         if (retval != ERROR_OK)
216                 return retval;
217         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
218
219         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
220         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
221         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
222
223         /* save i/d fault status and address register */
224         retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
225         if (retval != ERROR_OK)
226                 return retval;
227         retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
228         if (retval != ERROR_OK)
229                 return retval;
230         retval = jtag_execute_queue();
231         return retval;
232 }
233
234 static void arm720t_pre_restore_context(struct target *target)
235 {
236         struct arm720t_common *arm720t = target_to_arm720(target);
237
238         /* restore i/d fault status and address register */
239         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
240         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
241 }
242
243 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
244                 struct arm720t_common *arm720t)
245 {
246         if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
247                 command_print(cmd_ctx, "target is not an ARM720");
248                 return ERROR_TARGET_INVALID;
249         }
250         return ERROR_OK;
251 }
252
253 static int arm720t_arch_state(struct target *target)
254 {
255         struct arm720t_common *arm720t = target_to_arm720(target);
256         struct arm *armv4_5;
257
258         static const char *state[] =
259         {
260                 "disabled", "enabled"
261         };
262
263         armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
264
265         arm_arch_state(target);
266         LOG_USER("MMU: %s, Cache: %s",
267                          state[arm720t->armv4_5_mmu.mmu_enabled],
268                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
269
270         return ERROR_OK;
271 }
272
273 static int arm720_mmu(struct target *target, int *enabled)
274 {
275         if (target->state != TARGET_HALTED) {
276                 LOG_ERROR("%s: target not halted", __func__);
277                 return ERROR_TARGET_INVALID;
278         }
279
280         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
281         return ERROR_OK;
282 }
283
284 static int arm720_virt2phys(struct target *target,
285                 uint32_t virtual, uint32_t *physical)
286 {
287         uint32_t cb;
288         struct arm720t_common *arm720t = target_to_arm720(target);
289
290         uint32_t ret;
291         int retval = armv4_5_mmu_translate_va(target,
292                         &arm720t->armv4_5_mmu, virtual, &cb, &ret);
293         if (retval != ERROR_OK)
294                 return retval;
295         *physical = ret;
296         return ERROR_OK;
297 }
298
299 static int arm720t_read_memory(struct target *target,
300                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
301 {
302         int retval;
303         struct arm720t_common *arm720t = target_to_arm720(target);
304
305         /* disable cache, but leave MMU enabled */
306         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
307         {
308                 retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
309                 if (retval != ERROR_OK)
310                         return retval;
311         }
312         retval = arm7_9_read_memory(target, address, size, count, buffer);
313
314         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
315         {
316                 retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
317                 if (retval != ERROR_OK)
318                         return retval;
319         }
320
321         return retval;
322 }
323
324 static int arm720t_read_phys_memory(struct target *target,
325                 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
326 {
327         struct arm720t_common *arm720t = target_to_arm720(target);
328
329         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
330 }
331
332 static int arm720t_write_phys_memory(struct target *target,
333                 uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
334 {
335         struct arm720t_common *arm720t = target_to_arm720(target);
336
337         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
338 }
339
340 static int arm720t_soft_reset_halt(struct target *target)
341 {
342         int retval = ERROR_OK;
343         struct arm720t_common *arm720t = target_to_arm720(target);
344         struct reg *dbg_stat = &arm720t->arm7_9_common
345                         .eice_cache->reg_list[EICE_DBG_STAT];
346         struct arm *armv4_5 = &arm720t->arm7_9_common
347                         .armv4_5_common;
348
349         if ((retval = target_halt(target)) != ERROR_OK)
350         {
351                 return retval;
352         }
353
354         long long then = timeval_ms();
355         int timeout;
356         while (!(timeout = ((timeval_ms()-then) > 1000)))
357         {
358                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
359                 {
360                         embeddedice_read_reg(dbg_stat);
361                         if ((retval = jtag_execute_queue()) != ERROR_OK)
362                         {
363                                 return retval;
364                         }
365                 } else
366                 {
367                         break;
368                 }
369                 if (debug_level >= 3)
370                 {
371                         alive_sleep(100);
372                 } else
373                 {
374                         keep_alive();
375                 }
376         }
377         if (timeout)
378         {
379                 LOG_ERROR("Failed to halt CPU after 1 sec");
380                 return ERROR_TARGET_TIMEOUT;
381         }
382
383         target->state = TARGET_HALTED;
384
385         /* SVC, ARM state, IRQ and FIQ disabled */
386         uint32_t cpsr;
387
388         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
389         cpsr &= ~0xff;
390         cpsr |= 0xd3;
391         arm_set_cpsr(armv4_5, cpsr);
392         armv4_5->cpsr->dirty = 1;
393
394         /* start fetching from 0x0 */
395         buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
396         armv4_5->pc->dirty = 1;
397         armv4_5->pc->valid = 1;
398
399         retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
400         if (retval != ERROR_OK)
401                 return retval;
402         arm720t->armv4_5_mmu.mmu_enabled = 0;
403         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
404         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
405
406         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
407         {
408                 return retval;
409         }
410
411         return ERROR_OK;
412 }
413
414 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
415 {
416         return arm7tdmi_init_target(cmd_ctx, target);
417 }
418
419 /* FIXME remove forward decls */
420 static int arm720t_mrc(struct target *target, int cpnum,
421                 uint32_t op1, uint32_t op2,
422                 uint32_t CRn, uint32_t CRm,
423                 uint32_t *value);
424 static int arm720t_mcr(struct target *target, int cpnum,
425                 uint32_t op1, uint32_t op2,
426                 uint32_t CRn, uint32_t CRm,
427                 uint32_t value);
428
429 static int arm720t_init_arch_info(struct target *target,
430                 struct arm720t_common *arm720t, struct jtag_tap *tap)
431 {
432         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
433
434         arm7_9->armv4_5_common.mrc = arm720t_mrc;
435         arm7_9->armv4_5_common.mcr = arm720t_mcr;
436
437         arm7tdmi_init_arch_info(target, arm7_9, tap);
438
439         arm720t->common_magic = ARM720T_COMMON_MAGIC;
440
441         arm7_9->post_debug_entry = arm720t_post_debug_entry;
442         arm7_9->pre_restore_context = arm720t_pre_restore_context;
443
444         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
445         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
446         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
447         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
448         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
449         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
450         arm720t->armv4_5_mmu.has_tiny_pages = 0;
451         arm720t->armv4_5_mmu.mmu_enabled = 0;
452
453         return ERROR_OK;
454 }
455
456 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
457 {
458         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
459
460         arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
461         return arm720t_init_arch_info(target, arm720t, target->tap);
462 }
463
464 COMMAND_HANDLER(arm720t_handle_cp15_command)
465 {
466         int retval;
467         struct target *target = get_current_target(CMD_CTX);
468         struct arm720t_common *arm720t = target_to_arm720(target);
469         struct arm_jtag *jtag_info;
470
471         retval = arm720t_verify_pointer(CMD_CTX, arm720t);
472         if (retval != ERROR_OK)
473                 return retval;
474
475         jtag_info = &arm720t->arm7_9_common.jtag_info;
476
477         if (target->state != TARGET_HALTED)
478         {
479                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
480                 return ERROR_OK;
481         }
482
483         /* one or more argument, access a single register (write if second argument is given */
484         if (CMD_ARGC >= 1)
485         {
486                 uint32_t opcode;
487                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
488
489                 if (CMD_ARGC == 1)
490                 {
491                         uint32_t value;
492                         if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
493                         {
494                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
495                                 return ERROR_OK;
496                         }
497
498                         if ((retval = jtag_execute_queue()) != ERROR_OK)
499                         {
500                                 return retval;
501                         }
502
503                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
504                 }
505                 else if (CMD_ARGC == 2)
506                 {
507                         uint32_t value;
508                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
509
510                         if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
511                         {
512                                 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
513                                 return ERROR_OK;
514                         }
515                         command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
516                 }
517         }
518
519         return ERROR_OK;
520 }
521
522 static int arm720t_mrc(struct target *target, int cpnum,
523                 uint32_t op1, uint32_t op2,
524                 uint32_t CRn, uint32_t CRm,
525                 uint32_t *value)
526 {
527         if (cpnum!=15)
528         {
529                 LOG_ERROR("Only cp15 is supported");
530                 return ERROR_FAIL;
531         }
532
533         /* read "to" r0 */
534         return arm720t_read_cp15(target,
535                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
536                         value);
537
538 }
539
540 static int arm720t_mcr(struct target *target, int cpnum,
541                 uint32_t op1, uint32_t op2,
542                 uint32_t CRn, uint32_t CRm,
543                 uint32_t value)
544 {
545         if (cpnum!=15)
546         {
547                 LOG_ERROR("Only cp15 is supported");
548                 return ERROR_FAIL;
549         }
550
551         /* write "from" r0 */
552         return arm720t_write_cp15(target,
553                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
554                         value);
555 }
556
557 static const struct command_registration arm720t_exec_command_handlers[] = {
558         {
559                 .name = "cp15",
560                 .handler = arm720t_handle_cp15_command,
561                 .mode = COMMAND_EXEC,
562                 /* prefer using less error-prone "arm mcr" or "arm mrc" */
563                 .help = "display/modify cp15 register using ARM opcode"
564                         " (DEPRECATED)",
565                 .usage = "instruction [value]",
566         },
567         COMMAND_REGISTRATION_DONE
568 };
569
570 static const struct command_registration arm720t_command_handlers[] = {
571         {
572                 .chain = arm7_9_command_handlers,
573         },
574         {
575                 .name = "arm720t",
576                 .mode = COMMAND_ANY,
577                 .help = "arm720t command group",
578                 .chain = arm720t_exec_command_handlers,
579         },
580         COMMAND_REGISTRATION_DONE
581 };
582
583 /** Holds methods for ARM720 targets. */
584 struct target_type arm720t_target =
585 {
586         .name = "arm720t",
587
588         .poll = arm7_9_poll,
589         .arch_state = arm720t_arch_state,
590
591         .halt = arm7_9_halt,
592         .resume = arm7_9_resume,
593         .step = arm7_9_step,
594
595         .assert_reset = arm7_9_assert_reset,
596         .deassert_reset = arm7_9_deassert_reset,
597         .soft_reset_halt = arm720t_soft_reset_halt,
598
599         .get_gdb_reg_list = arm_get_gdb_reg_list,
600
601         .read_memory = arm720t_read_memory,
602         .write_memory = arm7_9_write_memory,
603         .read_phys_memory = arm720t_read_phys_memory,
604         .write_phys_memory = arm720t_write_phys_memory,
605         .mmu = arm720_mmu,
606         .virt2phys = arm720_virt2phys,
607
608         .bulk_write_memory = arm7_9_bulk_write_memory,
609
610         .checksum_memory = arm_checksum_memory,
611         .blank_check_memory = arm_blank_check_memory,
612
613         .run_algorithm = armv4_5_run_algorithm,
614
615         .add_breakpoint = arm7_9_add_breakpoint,
616         .remove_breakpoint = arm7_9_remove_breakpoint,
617         .add_watchpoint = arm7_9_add_watchpoint,
618         .remove_watchpoint = arm7_9_remove_watchpoint,
619
620         .commands = arm720t_command_handlers,
621         .target_create = arm720t_target_create,
622         .init_target = arm720t_init_target,
623         .examine = arm7_9_examine,
624         .check_reset = arm7_9_check_reset,
625 };