1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include "time_support.h"
26 #include "target_type.h"
30 #define _DEBUG_INSTRUCTION_EXECUTION_
34 int arm720t_register_commands(struct command_context_s *cmd_ctx);
36 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 /* forward declarations */
41 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
42 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
43 int arm720t_quit(void);
44 int arm720t_arch_state(struct target_s *target);
45 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
46 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
47 int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
48 int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
49 int arm720t_soft_reset_halt(struct target_s *target);
51 target_type_t arm720t_target =
56 .arch_state = arm720t_arch_state,
59 .resume = arm7_9_resume,
62 .assert_reset = arm7_9_assert_reset,
63 .deassert_reset = arm7_9_deassert_reset,
64 .soft_reset_halt = arm720t_soft_reset_halt,
66 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
68 .read_memory = arm720t_read_memory,
69 .write_memory = arm720t_write_memory,
70 .read_phys_memory = arm720t_read_phys_memory,
71 .write_phys_memory = arm720t_write_phys_memory,
72 .bulk_write_memory = arm7_9_bulk_write_memory,
73 .checksum_memory = arm7_9_checksum_memory,
74 .blank_check_memory = arm7_9_blank_check_memory,
76 .run_algorithm = armv4_5_run_algorithm,
78 .add_breakpoint = arm7_9_add_breakpoint,
79 .remove_breakpoint = arm7_9_remove_breakpoint,
80 .add_watchpoint = arm7_9_add_watchpoint,
81 .remove_watchpoint = arm7_9_remove_watchpoint,
83 .register_commands = arm720t_register_commands,
84 .target_create = arm720t_target_create,
85 .init_target = arm720t_init_target,
86 .examine = arm7tdmi_examine,
91 int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
93 int retval = ERROR_OK;
94 armv4_5_common_t *armv4_5 = target->arch_info;
95 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
96 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
97 scan_field_t fields[2];
99 uint8_t instruction_buf = instruction;
101 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
103 jtag_set_end_state(TAP_DRPAUSE);
104 if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
108 if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
113 fields[0].tap = jtag_info->tap;
114 fields[0].num_bits = 1;
115 fields[0].out_value = &instruction_buf;
116 fields[0].in_value = NULL;
118 fields[1].tap = jtag_info->tap;
119 fields[1].num_bits = 32;
120 fields[1].out_value = out_buf;
121 fields[1].in_value = NULL;
125 fields[1].in_value = (uint8_t *)in;
126 jtag_add_dr_scan(2, fields, jtag_get_end_state());
127 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
130 jtag_add_dr_scan(2, fields, jtag_get_end_state());
134 jtag_add_runtest(0, jtag_get_end_state());
136 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
137 if ((retval = jtag_execute_queue()) != ERROR_OK)
143 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
145 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
147 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
153 int arm720t_read_cp15(target_t *target, uint32_t opcode, uint32_t *value)
155 /* fetch CP15 opcode */
156 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
158 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
159 /* "EXECUTE" stage (1) */
160 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
161 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
162 /* "EXECUTE" stage (2) */
163 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
164 /* "EXECUTE" stage (3), CDATA is read */
165 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
170 int arm720t_write_cp15(target_t *target, uint32_t opcode, uint32_t value)
172 /* fetch CP15 opcode */
173 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
175 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
176 /* "EXECUTE" stage (1) */
177 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
178 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
179 /* "EXECUTE" stage (2) */
180 arm720t_scan_cp15(target, value, NULL, 0, 1);
181 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
186 uint32_t arm720t_get_ttb(target_t *target)
190 arm720t_read_cp15(target, 0xee120f10, &ttb);
191 jtag_execute_queue();
198 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
200 uint32_t cp15_control;
202 /* read cp15 control register */
203 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
204 jtag_execute_queue();
207 cp15_control &= ~0x1U;
209 if (d_u_cache || i_cache)
210 cp15_control &= ~0x4U;
212 arm720t_write_cp15(target, 0xee010f10, cp15_control);
215 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
217 uint32_t cp15_control;
219 /* read cp15 control register */
220 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
221 jtag_execute_queue();
224 cp15_control |= 0x1U;
226 if (d_u_cache || i_cache)
227 cp15_control |= 0x4U;
229 arm720t_write_cp15(target, 0xee010f10, cp15_control);
232 void arm720t_post_debug_entry(target_t *target)
234 armv4_5_common_t *armv4_5 = target->arch_info;
235 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
236 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
237 arm720t_common_t *arm720t = arm7tdmi->arch_info;
239 /* examine cp15 control reg */
240 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
241 jtag_execute_queue();
242 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
244 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
245 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
246 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
248 /* save i/d fault status and address register */
249 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
250 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
251 jtag_execute_queue();
254 void arm720t_pre_restore_context(target_t *target)
256 armv4_5_common_t *armv4_5 = target->arch_info;
257 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
258 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
259 arm720t_common_t *arm720t = arm7tdmi->arch_info;
261 /* restore i/d fault status and address register */
262 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
263 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
266 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
268 armv4_5_common_t *armv4_5 = target->arch_info;
269 arm7_9_common_t *arm7_9;
270 arm7tdmi_common_t *arm7tdmi;
271 arm720t_common_t *arm720t;
273 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
278 arm7_9 = armv4_5->arch_info;
279 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
284 arm7tdmi = arm7_9->arch_info;
285 if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
290 arm720t = arm7tdmi->arch_info;
291 if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
296 *armv4_5_p = armv4_5;
298 *arm7tdmi_p = arm7tdmi;
299 *arm720t_p = arm720t;
304 int arm720t_arch_state(struct target_s *target)
306 armv4_5_common_t *armv4_5 = target->arch_info;
307 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
308 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
309 arm720t_common_t *arm720t = arm7tdmi->arch_info;
313 "disabled", "enabled"
316 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
318 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
322 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
323 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
324 "MMU: %s, Cache: %s",
325 armv4_5_state_strings[armv4_5->core_state],
326 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
327 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
328 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
329 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
330 state[arm720t->armv4_5_mmu.mmu_enabled],
331 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
336 int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
339 armv4_5_common_t *armv4_5 = target->arch_info;
340 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
341 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
342 arm720t_common_t *arm720t = arm7tdmi->arch_info;
344 /* disable cache, but leave MMU enabled */
345 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
346 arm720t_disable_mmu_caches(target, 0, 1, 0);
348 retval = arm7_9_read_memory(target, address, size, count, buffer);
350 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
351 arm720t_enable_mmu_caches(target, 0, 1, 0);
356 int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
360 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
367 int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
369 armv4_5_common_t *armv4_5 = target->arch_info;
370 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
371 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
372 arm720t_common_t *arm720t = arm7tdmi->arch_info;
374 return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
377 int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
379 armv4_5_common_t *armv4_5 = target->arch_info;
380 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
381 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
382 arm720t_common_t *arm720t = arm7tdmi->arch_info;
384 return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
388 int arm720t_soft_reset_halt(struct target_s *target)
390 int retval = ERROR_OK;
391 armv4_5_common_t *armv4_5 = target->arch_info;
392 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
393 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
394 arm720t_common_t *arm720t = arm7tdmi->arch_info;
395 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
397 if ((retval = target_halt(target)) != ERROR_OK)
402 long long then = timeval_ms();
404 while (!(timeout = ((timeval_ms()-then) > 1000)))
406 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
408 embeddedice_read_reg(dbg_stat);
409 if ((retval = jtag_execute_queue()) != ERROR_OK)
417 if (debug_level >= 3)
427 LOG_ERROR("Failed to halt CPU after 1 sec");
428 return ERROR_TARGET_TIMEOUT;
431 target->state = TARGET_HALTED;
433 /* SVC, ARM state, IRQ and FIQ disabled */
434 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
435 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
436 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
438 /* start fetching from 0x0 */
439 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
440 armv4_5->core_cache->reg_list[15].dirty = 1;
441 armv4_5->core_cache->reg_list[15].valid = 1;
443 armv4_5->core_mode = ARMV4_5_MODE_SVC;
444 armv4_5->core_state = ARMV4_5_STATE_ARM;
446 arm720t_disable_mmu_caches(target, 1, 1, 1);
447 arm720t->armv4_5_mmu.mmu_enabled = 0;
448 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
449 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
451 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
459 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
461 arm7tdmi_init_target(cmd_ctx, target);
466 int arm720t_quit(void)
471 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
473 arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
474 arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
476 arm7tdmi_init_arch_info(target, arm7tdmi, tap);
478 arm7tdmi->arch_info = arm720t;
479 arm720t->common_magic = ARM720T_COMMON_MAGIC;
481 arm7_9->post_debug_entry = arm720t_post_debug_entry;
482 arm7_9->pre_restore_context = arm720t_pre_restore_context;
484 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
485 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
486 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
487 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
488 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
489 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
490 arm720t->armv4_5_mmu.has_tiny_pages = 0;
491 arm720t->armv4_5_mmu.mmu_enabled = 0;
496 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
498 arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
500 arm720t_init_arch_info(target, arm720t, target->tap);
505 int arm720t_register_commands(struct command_context_s *cmd_ctx)
508 command_t *arm720t_cmd;
511 retval = arm7tdmi_register_commands(cmd_ctx);
513 arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
515 register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
517 register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
518 register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
519 register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
521 register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
522 register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
523 register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
528 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
531 target_t *target = get_current_target(cmd_ctx);
532 armv4_5_common_t *armv4_5;
533 arm7_9_common_t *arm7_9;
534 arm7tdmi_common_t *arm7tdmi;
535 arm720t_common_t *arm720t;
536 arm_jtag_t *jtag_info;
538 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
540 command_print(cmd_ctx, "current target isn't an ARM720t target");
544 jtag_info = &arm7_9->jtag_info;
546 if (target->state != TARGET_HALTED)
548 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
552 /* one or more argument, access a single register (write if second argument is given */
555 uint32_t opcode = strtoul(args[0], NULL, 0);
560 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
562 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
566 if ((retval = jtag_execute_queue()) != ERROR_OK)
571 command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
575 uint32_t value = strtoul(args[1], NULL, 0);
576 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
578 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
581 command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
588 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
590 target_t *target = get_current_target(cmd_ctx);
591 armv4_5_common_t *armv4_5;
592 arm7_9_common_t *arm7_9;
593 arm7tdmi_common_t *arm7tdmi;
594 arm720t_common_t *arm720t;
595 arm_jtag_t *jtag_info;
597 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
599 command_print(cmd_ctx, "current target isn't an ARM720t target");
603 jtag_info = &arm7_9->jtag_info;
605 if (target->state != TARGET_HALTED)
607 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
611 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
614 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
616 target_t *target = get_current_target(cmd_ctx);
617 armv4_5_common_t *armv4_5;
618 arm7_9_common_t *arm7_9;
619 arm7tdmi_common_t *arm7tdmi;
620 arm720t_common_t *arm720t;
621 arm_jtag_t *jtag_info;
623 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
625 command_print(cmd_ctx, "current target isn't an ARM720t target");
629 jtag_info = &arm7_9->jtag_info;
631 if (target->state != TARGET_HALTED)
633 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
637 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);