1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm720t_register_commands(struct command_context_s *cmd_ctx);
39 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 /* forward declarations */
45 int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
46 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
47 int arm720t_quit(void);
48 int arm720t_arch_state(struct target_s *target);
49 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
50 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
51 int arm720t_soft_reset_halt(struct target_s *target);
53 target_type_t arm720t_target =
58 .arch_state = arm720t_arch_state,
61 .resume = arm7_9_resume,
64 .assert_reset = arm7_9_assert_reset,
65 .deassert_reset = arm7_9_deassert_reset,
66 .soft_reset_halt = arm720t_soft_reset_halt,
68 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
70 .read_memory = arm720t_read_memory,
71 .write_memory = arm720t_write_memory,
72 .bulk_write_memory = arm7_9_bulk_write_memory,
73 .checksum_memory = arm7_9_checksum_memory,
74 .blank_check_memory = arm7_9_blank_check_memory,
76 .run_algorithm = armv4_5_run_algorithm,
78 .add_breakpoint = arm7_9_add_breakpoint,
79 .remove_breakpoint = arm7_9_remove_breakpoint,
80 .add_watchpoint = arm7_9_add_watchpoint,
81 .remove_watchpoint = arm7_9_remove_watchpoint,
83 .register_commands = arm720t_register_commands,
84 .target_create = arm720t_target_create,
85 .init_target = arm720t_init_target,
86 .examine = arm7tdmi_examine,
90 int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int clock)
92 int retval = ERROR_OK;
93 armv4_5_common_t *armv4_5 = target->arch_info;
94 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
95 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
96 scan_field_t fields[2];
98 u8 instruction_buf = instruction;
100 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
102 jtag_add_end_state(TAP_DRPAUSE);
103 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
107 if((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
112 fields[0].tap = jtag_info->tap;
113 fields[0].num_bits = 1;
114 fields[0].out_value = &instruction_buf;
115 fields[0].in_value = NULL;
117 fields[1].tap = jtag_info->tap;
118 fields[1].num_bits = 32;
119 fields[1].out_value = out_buf;
120 fields[1].in_value = NULL;
125 fields[1].in_value = tmp;
126 jtag_add_dr_scan_now(2, fields, TAP_INVALID);
127 *in=flip_u32(le_to_h_u32(tmp), 32);
130 jtag_add_dr_scan(2, fields, TAP_INVALID);
134 jtag_add_runtest(0, TAP_INVALID);
136 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
137 if((retval = jtag_execute_queue()) != ERROR_OK)
143 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
145 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
147 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
153 int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value)
155 /* fetch CP15 opcode */
156 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
158 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
159 /* "EXECUTE" stage (1) */
160 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
161 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
162 /* "EXECUTE" stage (2) */
163 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
164 /* "EXECUTE" stage (3), CDATA is read */
165 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
170 int arm720t_write_cp15(target_t *target, u32 opcode, u32 value)
172 /* fetch CP15 opcode */
173 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
175 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
176 /* "EXECUTE" stage (1) */
177 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
178 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
179 /* "EXECUTE" stage (2) */
180 arm720t_scan_cp15(target, value, NULL, 0, 1);
181 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
186 u32 arm720t_get_ttb(target_t *target)
190 arm720t_read_cp15(target, 0xee120f10, &ttb);
191 jtag_execute_queue();
198 void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
202 /* read cp15 control register */
203 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
204 jtag_execute_queue();
207 cp15_control &= ~0x1U;
209 if (d_u_cache || i_cache)
210 cp15_control &= ~0x4U;
212 arm720t_write_cp15(target, 0xee010f10, cp15_control);
215 void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
219 /* read cp15 control register */
220 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
221 jtag_execute_queue();
224 cp15_control |= 0x1U;
226 if (d_u_cache || i_cache)
227 cp15_control |= 0x4U;
229 arm720t_write_cp15(target, 0xee010f10, cp15_control);
232 void arm720t_post_debug_entry(target_t *target)
234 armv4_5_common_t *armv4_5 = target->arch_info;
235 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
236 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
237 arm720t_common_t *arm720t = arm7tdmi->arch_info;
239 /* examine cp15 control reg */
240 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
241 jtag_execute_queue();
242 LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
244 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
245 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
246 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
248 /* save i/d fault status and address register */
249 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
250 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
251 jtag_execute_queue();
254 void arm720t_pre_restore_context(target_t *target)
256 armv4_5_common_t *armv4_5 = target->arch_info;
257 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
258 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
259 arm720t_common_t *arm720t = arm7tdmi->arch_info;
261 /* restore i/d fault status and address register */
262 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
263 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
266 int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm7tdmi_common_t **arm7tdmi_p, arm720t_common_t **arm720t_p)
268 armv4_5_common_t *armv4_5 = target->arch_info;
269 arm7_9_common_t *arm7_9;
270 arm7tdmi_common_t *arm7tdmi;
271 arm720t_common_t *arm720t;
273 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
278 arm7_9 = armv4_5->arch_info;
279 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
284 arm7tdmi = arm7_9->arch_info;
285 if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC)
290 arm720t = arm7tdmi->arch_info;
291 if (arm720t->common_magic != ARM720T_COMMON_MAGIC)
296 *armv4_5_p = armv4_5;
298 *arm7tdmi_p = arm7tdmi;
299 *arm720t_p = arm720t;
304 int arm720t_arch_state(struct target_s *target)
306 armv4_5_common_t *armv4_5 = target->arch_info;
307 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
308 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
309 arm720t_common_t *arm720t = arm7tdmi->arch_info;
313 "disabled", "enabled"
316 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
318 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
322 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
323 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
324 "MMU: %s, Cache: %s",
325 armv4_5_state_strings[armv4_5->core_state],
326 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
327 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
328 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
329 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
330 state[arm720t->armv4_5_mmu.mmu_enabled],
331 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
336 int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
339 armv4_5_common_t *armv4_5 = target->arch_info;
340 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
341 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
342 arm720t_common_t *arm720t = arm7tdmi->arch_info;
344 /* disable cache, but leave MMU enabled */
345 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
346 arm720t_disable_mmu_caches(target, 0, 1, 0);
348 retval = arm7_9_read_memory(target, address, size, count, buffer);
350 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
351 arm720t_enable_mmu_caches(target, 0, 1, 0);
356 int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
360 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
366 int arm720t_soft_reset_halt(struct target_s *target)
368 int retval = ERROR_OK;
369 armv4_5_common_t *armv4_5 = target->arch_info;
370 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
371 arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
372 arm720t_common_t *arm720t = arm7tdmi->arch_info;
373 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
375 if ((retval = target_halt(target)) != ERROR_OK)
380 long long then=timeval_ms();
382 while (!(timeout=((timeval_ms()-then)>1000)))
384 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
386 embeddedice_read_reg(dbg_stat);
387 if ((retval = jtag_execute_queue()) != ERROR_OK)
405 LOG_ERROR("Failed to halt CPU after 1 sec");
406 return ERROR_TARGET_TIMEOUT;
409 target->state = TARGET_HALTED;
411 /* SVC, ARM state, IRQ and FIQ disabled */
412 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
413 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
414 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
416 /* start fetching from 0x0 */
417 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
418 armv4_5->core_cache->reg_list[15].dirty = 1;
419 armv4_5->core_cache->reg_list[15].valid = 1;
421 armv4_5->core_mode = ARMV4_5_MODE_SVC;
422 armv4_5->core_state = ARMV4_5_STATE_ARM;
424 arm720t_disable_mmu_caches(target, 1, 1, 1);
425 arm720t->armv4_5_mmu.mmu_enabled = 0;
426 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
427 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
429 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
437 int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
439 arm7tdmi_init_target(cmd_ctx, target);
444 int arm720t_quit(void)
449 int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap_t *tap)
451 arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common;
452 arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common;
454 arm7tdmi_init_arch_info(target, arm7tdmi, tap);
456 arm7tdmi->arch_info = arm720t;
457 arm720t->common_magic = ARM720T_COMMON_MAGIC;
459 arm7_9->post_debug_entry = arm720t_post_debug_entry;
460 arm7_9->pre_restore_context = arm720t_pre_restore_context;
462 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
463 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
464 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
465 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
466 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
467 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
468 arm720t->armv4_5_mmu.has_tiny_pages = 0;
469 arm720t->armv4_5_mmu.mmu_enabled = 0;
474 int arm720t_target_create(struct target_s *target, Jim_Interp *interp)
476 arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t));
478 arm720t_init_arch_info(target, arm720t, target->tap);
483 int arm720t_register_commands(struct command_context_s *cmd_ctx)
486 command_t *arm720t_cmd;
489 retval = arm7tdmi_register_commands(cmd_ctx);
491 arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
493 register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
494 register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
496 register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
497 register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
498 register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
500 register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
501 register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
502 register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
507 int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
510 target_t *target = get_current_target(cmd_ctx);
511 armv4_5_common_t *armv4_5;
512 arm7_9_common_t *arm7_9;
513 arm7tdmi_common_t *arm7tdmi;
514 arm720t_common_t *arm720t;
515 arm_jtag_t *jtag_info;
517 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
519 command_print(cmd_ctx, "current target isn't an ARM720t target");
523 jtag_info = &arm7_9->jtag_info;
525 if (target->state != TARGET_HALTED)
527 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
531 /* one or more argument, access a single register (write if second argument is given */
534 u32 opcode = strtoul(args[0], NULL, 0);
539 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
541 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
545 if ((retval = jtag_execute_queue()) != ERROR_OK)
550 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
554 u32 value = strtoul(args[1], NULL, 0);
555 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
557 command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
560 command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
567 int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
569 target_t *target = get_current_target(cmd_ctx);
570 armv4_5_common_t *armv4_5;
571 arm7_9_common_t *arm7_9;
572 arm7tdmi_common_t *arm7tdmi;
573 arm720t_common_t *arm720t;
574 arm_jtag_t *jtag_info;
576 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
578 command_print(cmd_ctx, "current target isn't an ARM720t target");
582 jtag_info = &arm7_9->jtag_info;
584 if (target->state != TARGET_HALTED)
586 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
590 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
593 int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
595 target_t *target = get_current_target(cmd_ctx);
596 armv4_5_common_t *armv4_5;
597 arm7_9_common_t *arm7_9;
598 arm7tdmi_common_t *arm7tdmi;
599 arm720t_common_t *arm720t;
600 arm_jtag_t *jtag_info;
602 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
604 command_print(cmd_ctx, "current target isn't an ARM720t target");
608 jtag_info = &arm7_9->jtag_info;
610 if (target->state != TARGET_HALTED)
612 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
616 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
619 int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
621 target_t *target = get_current_target(cmd_ctx);
622 armv4_5_common_t *armv4_5;
623 arm7_9_common_t *arm7_9;
624 arm7tdmi_common_t *arm7tdmi;
625 arm720t_common_t *arm720t;
626 arm_jtag_t *jtag_info;
628 if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
630 command_print(cmd_ctx, "current target isn't an ARM720t target");
634 jtag_info = &arm7_9->jtag_info;
636 if (target->state != TARGET_HALTED)
638 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
642 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);