1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "time_support.h"
29 #include "target_type.h"
34 * ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
35 * ARM DDI 0229C especially Chapter 9 about debug support.
39 #define _DEBUG_INSTRUCTION_EXECUTION_
42 static int arm720t_scan_cp15(struct target *target,
43 uint32_t out, uint32_t *in, int instruction, int clock)
46 struct arm720t_common *arm720t = target_to_arm720(target);
47 struct arm_jtag *jtag_info;
48 struct scan_field fields[2];
50 uint8_t instruction_buf = instruction;
52 jtag_info = &arm720t->arm7_9_common.jtag_info;
54 buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
56 jtag_set_end_state(TAP_DRPAUSE);
57 if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
61 if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
66 fields[0].tap = jtag_info->tap;
67 fields[0].num_bits = 1;
68 fields[0].out_value = &instruction_buf;
69 fields[0].in_value = NULL;
71 fields[1].tap = jtag_info->tap;
72 fields[1].num_bits = 32;
73 fields[1].out_value = out_buf;
74 fields[1].in_value = NULL;
78 fields[1].in_value = (uint8_t *)in;
79 jtag_add_dr_scan(2, fields, jtag_get_end_state());
80 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
83 jtag_add_dr_scan(2, fields, jtag_get_end_state());
87 jtag_add_runtest(0, jtag_get_end_state());
89 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
90 if ((retval = jtag_execute_queue()) != ERROR_OK)
96 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
98 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
100 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
106 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
108 /* fetch CP15 opcode */
109 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
111 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
112 /* "EXECUTE" stage (1) */
113 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
114 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
115 /* "EXECUTE" stage (2) */
116 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
117 /* "EXECUTE" stage (3), CDATA is read */
118 arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
123 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
125 /* fetch CP15 opcode */
126 arm720t_scan_cp15(target, opcode, NULL, 1, 1);
128 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
129 /* "EXECUTE" stage (1) */
130 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
131 arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
132 /* "EXECUTE" stage (2) */
133 arm720t_scan_cp15(target, value, NULL, 0, 1);
134 arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
139 static uint32_t arm720t_get_ttb(struct target *target)
143 arm720t_read_cp15(target, 0xee120f10, &ttb);
144 jtag_execute_queue();
151 static void arm720t_disable_mmu_caches(struct target *target,
152 int mmu, int d_u_cache, int i_cache)
154 uint32_t cp15_control;
156 /* read cp15 control register */
157 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
158 jtag_execute_queue();
161 cp15_control &= ~0x1U;
163 if (d_u_cache || i_cache)
164 cp15_control &= ~0x4U;
166 arm720t_write_cp15(target, 0xee010f10, cp15_control);
169 static void arm720t_enable_mmu_caches(struct target *target,
170 int mmu, int d_u_cache, int i_cache)
172 uint32_t cp15_control;
174 /* read cp15 control register */
175 arm720t_read_cp15(target, 0xee110f10, &cp15_control);
176 jtag_execute_queue();
179 cp15_control |= 0x1U;
181 if (d_u_cache || i_cache)
182 cp15_control |= 0x4U;
184 arm720t_write_cp15(target, 0xee010f10, cp15_control);
187 static void arm720t_post_debug_entry(struct target *target)
189 struct arm720t_common *arm720t = target_to_arm720(target);
191 /* examine cp15 control reg */
192 arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
193 jtag_execute_queue();
194 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
196 arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
197 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
198 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
200 /* save i/d fault status and address register */
201 arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
202 arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
203 jtag_execute_queue();
206 static void arm720t_pre_restore_context(struct target *target)
208 struct arm720t_common *arm720t = target_to_arm720(target);
210 /* restore i/d fault status and address register */
211 arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
212 arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
215 static int arm720t_verify_pointer(struct command_context *cmd_ctx,
216 struct arm720t_common *arm720t)
218 if (arm720t->common_magic != ARM720T_COMMON_MAGIC) {
219 command_print(cmd_ctx, "target is not an ARM720");
220 return ERROR_TARGET_INVALID;
225 static int arm720t_arch_state(struct target *target)
227 struct arm720t_common *arm720t = target_to_arm720(target);
230 static const char *state[] =
232 "disabled", "enabled"
235 armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
237 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
238 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
239 "MMU: %s, Cache: %s",
240 armv4_5_state_strings[armv4_5->core_state],
241 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
242 arm_mode_name(armv4_5->core_mode),
243 buf_get_u32(armv4_5->cpsr->value, 0, 32),
244 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
245 state[arm720t->armv4_5_mmu.mmu_enabled],
246 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
251 static int arm720_mmu(struct target *target, int *enabled)
253 if (target->state != TARGET_HALTED) {
254 LOG_ERROR("%s: target not halted", __func__);
255 return ERROR_TARGET_INVALID;
258 *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
262 static int arm720_virt2phys(struct target *target,
263 uint32_t virt, uint32_t *phys)
265 /** @todo Implement this! */
266 LOG_ERROR("%s: not implemented", __func__);
270 static int arm720t_read_memory(struct target *target,
271 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
274 struct arm720t_common *arm720t = target_to_arm720(target);
276 /* disable cache, but leave MMU enabled */
277 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
278 arm720t_disable_mmu_caches(target, 0, 1, 0);
280 retval = arm7_9_read_memory(target, address, size, count, buffer);
282 if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
283 arm720t_enable_mmu_caches(target, 0, 1, 0);
288 static int arm720t_read_phys_memory(struct target *target,
289 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
291 struct arm720t_common *arm720t = target_to_arm720(target);
293 return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
296 static int arm720t_write_phys_memory(struct target *target,
297 uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
299 struct arm720t_common *arm720t = target_to_arm720(target);
301 return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
304 static int arm720t_soft_reset_halt(struct target *target)
306 int retval = ERROR_OK;
307 struct arm720t_common *arm720t = target_to_arm720(target);
308 struct reg *dbg_stat = &arm720t->arm7_9_common
309 .eice_cache->reg_list[EICE_DBG_STAT];
310 struct arm *armv4_5 = &arm720t->arm7_9_common
313 if ((retval = target_halt(target)) != ERROR_OK)
318 long long then = timeval_ms();
320 while (!(timeout = ((timeval_ms()-then) > 1000)))
322 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
324 embeddedice_read_reg(dbg_stat);
325 if ((retval = jtag_execute_queue()) != ERROR_OK)
333 if (debug_level >= 3)
343 LOG_ERROR("Failed to halt CPU after 1 sec");
344 return ERROR_TARGET_TIMEOUT;
347 target->state = TARGET_HALTED;
349 /* SVC, ARM state, IRQ and FIQ disabled */
352 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
355 arm_set_cpsr(armv4_5, cpsr);
356 armv4_5->cpsr->dirty = 1;
358 /* start fetching from 0x0 */
359 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
360 armv4_5->core_cache->reg_list[15].dirty = 1;
361 armv4_5->core_cache->reg_list[15].valid = 1;
363 arm720t_disable_mmu_caches(target, 1, 1, 1);
364 arm720t->armv4_5_mmu.mmu_enabled = 0;
365 arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
366 arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
368 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
376 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
378 return arm7tdmi_init_target(cmd_ctx, target);
381 static int arm720t_init_arch_info(struct target *target,
382 struct arm720t_common *arm720t, struct jtag_tap *tap)
384 struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
386 arm7tdmi_init_arch_info(target, arm7_9, tap);
388 arm720t->common_magic = ARM720T_COMMON_MAGIC;
390 arm7_9->post_debug_entry = arm720t_post_debug_entry;
391 arm7_9->pre_restore_context = arm720t_pre_restore_context;
393 arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
394 arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
395 arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
396 arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
397 arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
398 arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
399 arm720t->armv4_5_mmu.has_tiny_pages = 0;
400 arm720t->armv4_5_mmu.mmu_enabled = 0;
405 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
407 struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
409 arm720t->arm7_9_common.armv4_5_common.is_armv4 = true;
410 return arm720t_init_arch_info(target, arm720t, target->tap);
413 COMMAND_HANDLER(arm720t_handle_cp15_command)
416 struct target *target = get_current_target(CMD_CTX);
417 struct arm720t_common *arm720t = target_to_arm720(target);
418 struct arm_jtag *jtag_info;
420 retval = arm720t_verify_pointer(CMD_CTX, arm720t);
421 if (retval != ERROR_OK)
424 jtag_info = &arm720t->arm7_9_common.jtag_info;
426 if (target->state != TARGET_HALTED)
428 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
432 /* one or more argument, access a single register (write if second argument is given */
436 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
441 if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
443 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
447 if ((retval = jtag_execute_queue()) != ERROR_OK)
452 command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
454 else if (CMD_ARGC == 2)
457 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
459 if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
461 command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
464 command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
471 static int arm720t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
475 LOG_ERROR("Only cp15 is supported");
479 return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
483 static int arm720t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
487 LOG_ERROR("Only cp15 is supported");
491 return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
494 static const struct command_registration arm720t_exec_command_handlers[] = {
497 .handler = arm720t_handle_cp15_command,
498 .mode = COMMAND_EXEC,
499 .usage = "<opcode> [value]",
500 .help = "display/modify cp15 register",
502 COMMAND_REGISTRATION_DONE
505 static const struct command_registration arm720t_command_handlers[] = {
507 .chain = arm7_9_command_handlers,
512 .help = "arm720t command group",
513 .chain = arm720t_exec_command_handlers,
515 COMMAND_REGISTRATION_DONE
518 /** Holds methods for ARM720 targets. */
519 struct target_type arm720t_target =
524 .arch_state = arm720t_arch_state,
527 .resume = arm7_9_resume,
530 .assert_reset = arm7_9_assert_reset,
531 .deassert_reset = arm7_9_deassert_reset,
532 .soft_reset_halt = arm720t_soft_reset_halt,
534 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
536 .read_memory = arm720t_read_memory,
537 .write_memory = arm7_9_write_memory,
538 .read_phys_memory = arm720t_read_phys_memory,
539 .write_phys_memory = arm720t_write_phys_memory,
541 .virt2phys = arm720_virt2phys,
543 .bulk_write_memory = arm7_9_bulk_write_memory,
545 .checksum_memory = arm_checksum_memory,
546 .blank_check_memory = arm_blank_check_memory,
548 .run_algorithm = armv4_5_run_algorithm,
550 .add_breakpoint = arm7_9_add_breakpoint,
551 .remove_breakpoint = arm7_9_remove_breakpoint,
552 .add_watchpoint = arm7_9_add_watchpoint,
553 .remove_watchpoint = arm7_9_remove_watchpoint,
555 .commands = arm720t_command_handlers,
556 .target_create = arm720t_target_create,
557 .init_target = arm720t_init_target,
558 .examine = arm7_9_examine,