1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008 Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2008 by Hongtao Zheng *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
33 #include "breakpoints.h"
34 #include "embeddedice.h"
35 #include "target_request.h"
37 #include <helper/time_support.h>
38 #include "arm_simulator.h"
39 #include "algorithm.h"
45 * Hold common code supporting the ARM7 and ARM9 core generations.
47 * While the ARM core implementations evolved substantially during these
48 * two generations, they look quite similar from the JTAG perspective.
49 * Both have similar debug facilities, based on the same two scan chains
50 * providing access to the core and to an EmbeddedICE module. Both can
51 * support similar ETM and ETB modules, for tracing. And both expose
52 * what could be viewed as "ARM Classic", with multiple processor modes,
53 * shadowed registers, and support for the Thumb instruction set.
55 * Processor differences include things like presence or absence of MMU
56 * and cache, pipeline sizes, use of a modified Harvard Architecure
57 * (with separate instruction and data busses from the CPU), support
58 * for cpu clock gating during idle, and more.
61 static int arm7_9_debug_entry(struct target *target);
64 * Clear watchpoints for an ARM7/9 target.
66 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
67 * @return JTAG error status after executing queue
69 static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
72 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
73 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
74 arm7_9->sw_breakpoint_count = 0;
75 arm7_9->sw_breakpoints_added = 0;
77 arm7_9->wp1_used = arm7_9->wp1_used_default;
78 arm7_9->wp_available = arm7_9->wp_available_max;
80 return jtag_execute_queue();
84 * Assign a watchpoint to one of the two available hardware comparators in an
85 * ARM7 or ARM9 target.
87 * @param arm7_9 Pointer to the common struct for an ARM7/9 target
88 * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
90 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
92 if (!arm7_9->wp0_used)
96 arm7_9->wp_available--;
98 else if (!arm7_9->wp1_used)
100 arm7_9->wp1_used = 1;
102 arm7_9->wp_available--;
106 LOG_ERROR("BUG: no hardware comparator available");
108 LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
109 breakpoint->unique_id,
115 * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
117 * @param arm7_9 Pointer to common struct for ARM7/9 targets
118 * @return Error codes if there is a problem finding a watchpoint or the result
119 * of executing the JTAG queue
121 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
123 if (arm7_9->sw_breakpoints_added)
127 if (arm7_9->wp_available < 1)
129 LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
130 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
132 arm7_9->wp_available--;
134 /* pick a breakpoint unit */
135 if (!arm7_9->wp0_used)
137 arm7_9->sw_breakpoints_added = 1;
138 arm7_9->wp0_used = 3;
139 } else if (!arm7_9->wp1_used)
141 arm7_9->sw_breakpoints_added = 2;
142 arm7_9->wp1_used = 3;
146 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
150 if (arm7_9->sw_breakpoints_added == 1)
152 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
153 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
154 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
155 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
158 else if (arm7_9->sw_breakpoints_added == 2)
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
161 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
162 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
163 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
164 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
168 LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
171 LOG_DEBUG("SW BP using hw wp: %d",
172 arm7_9->sw_breakpoints_added );
174 return jtag_execute_queue();
178 * Setup the common pieces for an ARM7/9 target after reset or on startup.
180 * @param target Pointer to an ARM7/9 target to setup
181 * @return Result of clearing the watchpoints on the target
183 int arm7_9_setup(struct target *target)
185 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
187 return arm7_9_clear_watchpoints(arm7_9);
191 * Set either a hardware or software breakpoint on an ARM7/9 target. The
192 * breakpoint is set up even if it is already set. Some actions, e.g. reset,
193 * might have erased the values in Embedded ICE.
195 * @param target Pointer to the target device to set the breakpoints on
196 * @param breakpoint Pointer to the breakpoint to be set
197 * @return For hardware breakpoints, this is the result of executing the JTAG
198 * queue. For software breakpoints, this will be the status of the
199 * required memory reads and writes
201 int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
203 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
204 int retval = ERROR_OK;
206 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
207 breakpoint->unique_id,
211 if (target->state != TARGET_HALTED)
213 LOG_WARNING("target not halted");
214 return ERROR_TARGET_NOT_HALTED;
217 if (breakpoint->type == BKPT_HARD)
219 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
220 uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
222 /* reassign a hw breakpoint */
223 if (breakpoint->set == 0)
225 arm7_9_assign_wp(arm7_9, breakpoint);
228 if (breakpoint->set == 1)
230 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
231 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
232 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
233 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
236 else if (breakpoint->set == 2)
238 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
239 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
240 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
241 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
242 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
246 LOG_ERROR("BUG: no hardware comparator available");
250 retval = jtag_execute_queue();
252 else if (breakpoint->type == BKPT_SOFT)
254 /* did we already set this breakpoint? */
258 if (breakpoint->length == 4)
260 uint32_t verify = 0xffffffff;
261 /* keep the original instruction in target endianness */
262 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
266 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
267 if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
272 if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
276 if (verify != arm7_9->arm_bkpt)
278 LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
284 uint16_t verify = 0xffff;
285 /* keep the original instruction in target endianness */
286 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
290 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
291 if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
296 if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
300 if (verify != arm7_9->thumb_bkpt)
302 LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
307 if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
310 arm7_9->sw_breakpoint_count++;
319 * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
320 * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
321 * will be updated. Otherwise, the software breakpoint will be restored to its
322 * original instruction if it hasn't already been modified.
324 * @param target Pointer to ARM7/9 target to unset the breakpoint from
325 * @param breakpoint Pointer to breakpoint to be unset
326 * @return For hardware breakpoints, this is the result of executing the JTAG
327 * queue. For software breakpoints, this will be the status of the
328 * required memory reads and writes
330 int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
332 int retval = ERROR_OK;
333 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
335 LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
336 breakpoint->unique_id,
337 breakpoint->address );
339 if (!breakpoint->set)
341 LOG_WARNING("breakpoint not set");
345 if (breakpoint->type == BKPT_HARD)
347 LOG_DEBUG("BPID: %d Releasing hw wp: %d",
348 breakpoint->unique_id,
350 if (breakpoint->set == 1)
352 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
353 arm7_9->wp0_used = 0;
354 arm7_9->wp_available++;
356 else if (breakpoint->set == 2)
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
359 arm7_9->wp1_used = 0;
360 arm7_9->wp_available++;
362 retval = jtag_execute_queue();
367 /* restore original instruction (kept in target endianness) */
368 if (breakpoint->length == 4)
370 uint32_t current_instr;
371 /* check that user program as not modified breakpoint instruction */
372 if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)¤t_instr)) != ERROR_OK)
376 if (current_instr == arm7_9->arm_bkpt)
377 if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
384 uint16_t current_instr;
385 /* check that user program as not modified breakpoint instruction */
386 if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)¤t_instr)) != ERROR_OK)
390 if (current_instr == arm7_9->thumb_bkpt)
391 if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
397 if (--arm7_9->sw_breakpoint_count==0)
399 /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
400 if (arm7_9->sw_breakpoints_added == 1)
402 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
404 else if (arm7_9->sw_breakpoints_added == 2)
406 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
417 * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
418 * dangling breakpoints and that the desired breakpoint can be added.
420 * @param target Pointer to the target ARM7/9 device to add a breakpoint to
421 * @param breakpoint Pointer to the breakpoint to be added
422 * @return An error status if there is a problem adding the breakpoint or the
423 * result of setting the breakpoint
425 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
427 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
429 if (arm7_9->breakpoint_count == 0)
431 /* make sure we don't have any dangling breakpoints. This is vital upon
432 * GDB connect/disconnect
434 arm7_9_clear_watchpoints(arm7_9);
437 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
439 LOG_INFO("no watchpoint unit available for hardware breakpoint");
440 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
443 if ((breakpoint->length != 2) && (breakpoint->length != 4))
445 LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
446 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
449 if (breakpoint->type == BKPT_HARD)
451 arm7_9_assign_wp(arm7_9, breakpoint);
454 arm7_9->breakpoint_count++;
456 return arm7_9_set_breakpoint(target, breakpoint);
460 * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
461 * dangling breakpoints and updates available watchpoints if it is a hardware
464 * @param target Pointer to the target to have a breakpoint removed
465 * @param breakpoint Pointer to the breakpoint to be removed
466 * @return Error status if there was a problem unsetting the breakpoint or the
467 * watchpoints could not be cleared
469 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
471 int retval = ERROR_OK;
472 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
474 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
479 if (breakpoint->type == BKPT_HARD)
480 arm7_9->wp_available++;
482 arm7_9->breakpoint_count--;
483 if (arm7_9->breakpoint_count == 0)
485 /* make sure we don't have any dangling breakpoints */
486 if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
496 * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
497 * considered a bug to call this function when there are no available watchpoint
500 * @param target Pointer to an ARM7/9 target to set a watchpoint on
501 * @param watchpoint Pointer to the watchpoint to be set
502 * @return Error status if watchpoint set fails or the result of executing the
505 int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
507 int retval = ERROR_OK;
508 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
512 mask = watchpoint->length - 1;
514 if (target->state != TARGET_HALTED)
516 LOG_WARNING("target not halted");
517 return ERROR_TARGET_NOT_HALTED;
520 if (watchpoint->rw == WPT_ACCESS)
525 if (!arm7_9->wp0_used)
527 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
528 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
529 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
530 if (watchpoint->mask != 0xffffffffu)
531 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
532 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
533 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
535 if ((retval = jtag_execute_queue()) != ERROR_OK)
540 arm7_9->wp0_used = 2;
542 else if (!arm7_9->wp1_used)
544 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
545 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
546 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
547 if (watchpoint->mask != 0xffffffffu)
548 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
549 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
550 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
552 if ((retval = jtag_execute_queue()) != ERROR_OK)
557 arm7_9->wp1_used = 2;
561 LOG_ERROR("BUG: no hardware comparator available");
569 * Unset an existing watchpoint and clear the used watchpoint unit.
571 * @param target Pointer to the target to have the watchpoint removed
572 * @param watchpoint Pointer to the watchpoint to be removed
573 * @return Error status while trying to unset the watchpoint or the result of
574 * executing the JTAG queue
576 int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
578 int retval = ERROR_OK;
579 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
581 if (target->state != TARGET_HALTED)
583 LOG_WARNING("target not halted");
584 return ERROR_TARGET_NOT_HALTED;
587 if (!watchpoint->set)
589 LOG_WARNING("breakpoint not set");
593 if (watchpoint->set == 1)
595 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
596 if ((retval = jtag_execute_queue()) != ERROR_OK)
600 arm7_9->wp0_used = 0;
602 else if (watchpoint->set == 2)
604 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
605 if ((retval = jtag_execute_queue()) != ERROR_OK)
609 arm7_9->wp1_used = 0;
617 * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
618 * available, an error response is returned.
620 * @param target Pointer to the ARM7/9 target to add a watchpoint to
621 * @param watchpoint Pointer to the watchpoint to be added
622 * @return Error status while trying to add the watchpoint
624 int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
626 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
628 if (arm7_9->wp_available < 1)
630 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
633 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
635 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
638 arm7_9->wp_available--;
644 * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
645 * the used watchpoint unit will be reopened.
647 * @param target Pointer to the target to remove a watchpoint from
648 * @param watchpoint Pointer to the watchpoint to be removed
649 * @return Result of trying to unset the watchpoint
651 int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
653 int retval = ERROR_OK;
654 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
658 if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
664 arm7_9->wp_available++;
670 * Restarts the target by sending a RESTART instruction and moving the JTAG
671 * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
672 * asserted by the processor.
674 * @param target Pointer to target to issue commands to
675 * @return Error status if there is a timeout or a problem while executing the
678 int arm7_9_execute_sys_speed(struct target *target)
681 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
682 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
683 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
685 /* set RESTART instruction */
686 jtag_set_end_state(TAP_IDLE);
687 if (arm7_9->need_bypass_before_restart) {
688 arm7_9->need_bypass_before_restart = 0;
689 arm_jtag_set_instr(jtag_info, 0xf, NULL);
691 arm_jtag_set_instr(jtag_info, 0x4, NULL);
693 long long then = timeval_ms();
695 while (!(timeout = ((timeval_ms()-then) > 1000)))
697 /* read debug status register */
698 embeddedice_read_reg(dbg_stat);
699 if ((retval = jtag_execute_queue()) != ERROR_OK)
701 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
702 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
704 if (debug_level >= 3)
714 LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
715 return ERROR_TARGET_TIMEOUT;
722 * Restarts the target by sending a RESTART instruction and moving the JTAG
723 * state to IDLE. This validates that DBGACK and SYSCOMP are set without
724 * waiting until they are.
726 * @param target Pointer to the target to issue commands to
727 * @return Always ERROR_OK
729 int arm7_9_execute_fast_sys_speed(struct target *target)
732 static uint8_t check_value[4], check_mask[4];
734 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
735 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
736 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
738 /* set RESTART instruction */
739 jtag_set_end_state(TAP_IDLE);
740 if (arm7_9->need_bypass_before_restart) {
741 arm7_9->need_bypass_before_restart = 0;
742 arm_jtag_set_instr(jtag_info, 0xf, NULL);
744 arm_jtag_set_instr(jtag_info, 0x4, NULL);
748 /* check for DBGACK and SYSCOMP set (others don't care) */
750 /* NB! These are constants that must be available until after next jtag_execute() and
751 * we evaluate the values upon first execution in lieu of setting up these constants
752 * during early setup.
754 buf_set_u32(check_value, 0, 32, 0x9);
755 buf_set_u32(check_mask, 0, 32, 0x9);
759 /* read debug status register */
760 embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
766 * Get some data from the ARM7/9 target.
768 * @param target Pointer to the ARM7/9 target to read data from
769 * @param size The number of 32bit words to be read
770 * @param buffer Pointer to the buffer that will hold the data
771 * @return The result of receiving data from the Embedded ICE unit
773 int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *buffer)
775 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
776 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
778 int retval = ERROR_OK;
781 data = malloc(size * (sizeof(uint32_t)));
783 retval = embeddedice_receive(jtag_info, data, size);
785 /* return the 32-bit ints in the 8-bit array */
786 for (i = 0; i < size; i++)
788 h_u32_to_le(buffer + (i * 4), data[i]);
797 * Handles requests to an ARM7/9 target. If debug messaging is enabled, the
798 * target is running and the DCC control register has the W bit high, this will
799 * execute the request on the target.
801 * @param priv Void pointer expected to be a struct target pointer
802 * @return ERROR_OK unless there are issues with the JTAG queue or when reading
803 * from the Embedded ICE unit
805 int arm7_9_handle_target_request(void *priv)
807 int retval = ERROR_OK;
808 struct target *target = priv;
809 if (!target_was_examined(target))
811 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
812 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
813 struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
815 if (!target->dbg_msg_enabled)
818 if (target->state == TARGET_RUNNING)
820 /* read DCC control register */
821 embeddedice_read_reg(dcc_control);
822 if ((retval = jtag_execute_queue()) != ERROR_OK)
828 if (buf_get_u32(dcc_control->value, 1, 1) == 1)
832 if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
836 if ((retval = target_request(target, request)) != ERROR_OK)
847 * Polls an ARM7/9 target for its current status. If DBGACK is set, the target
848 * is manipulated to the right halted state based on its current state. This is
852 * <tr><th > State</th><th > Action</th></tr>
853 * <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode. If TARGET_RESET, pc may be checked</td></tr>
854 * <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
855 * <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
856 * <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
859 * If the target does not end up in the halted state, a warning is produced. If
860 * DBGACK is cleared, then the target is expected to either be running or
863 * @param target Pointer to the ARM7/9 target to poll
864 * @return ERROR_OK or an error status if a command fails
866 int arm7_9_poll(struct target *target)
869 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
870 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
872 /* read debug status register */
873 embeddedice_read_reg(dbg_stat);
874 if ((retval = jtag_execute_queue()) != ERROR_OK)
879 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
881 /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
882 if (target->state == TARGET_UNKNOWN)
884 /* Starting OpenOCD with target in debug-halt */
885 target->state = TARGET_RUNNING;
886 LOG_DEBUG("DBGACK already set during server startup.");
888 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
891 if (target->state == TARGET_RESET)
893 if (target->reset_halt)
895 enum reset_types jtag_reset_config = jtag_get_reset_config();
896 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
903 target->state = TARGET_HALTED;
905 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
910 struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
911 uint32_t t=*((uint32_t *)reg->value);
914 LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
918 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
923 if (target->state == TARGET_DEBUG_RUNNING)
925 target->state = TARGET_HALTED;
926 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
929 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
934 if (target->state != TARGET_HALTED)
936 LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
941 if (target->state != TARGET_DEBUG_RUNNING)
942 target->state = TARGET_RUNNING;
949 * Asserts the reset (SRST) on an ARM7/9 target. Some -S targets (ARM966E-S in
950 * the STR912 isn't affected, ARM926EJ-S in the LPC3180 and AT91SAM9260 is
951 * affected) completely stop the JTAG clock while the core is held in reset
952 * (SRST). It isn't possible to program the halt condition once reset is
953 * asserted, hence a hook that allows the target to set up its reset-halt
954 * condition is setup prior to asserting reset.
956 * @param target Pointer to an ARM7/9 target to assert reset on
957 * @return ERROR_FAIL if the JTAG device does not have SRST, otherwise ERROR_OK
959 int arm7_9_assert_reset(struct target *target)
961 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
963 LOG_DEBUG("target->state: %s",
964 target_state_name(target));
966 enum reset_types jtag_reset_config = jtag_get_reset_config();
967 if (!(jtag_reset_config & RESET_HAS_SRST))
969 LOG_ERROR("Can't assert SRST");
973 /* At this point trst has been asserted/deasserted once. We would
974 * like to program EmbeddedICE while SRST is asserted, instead of
975 * depending on SRST to leave that module alone. However, many CPUs
976 * gate the JTAG clock while SRST is asserted; or JTAG may need
977 * clock stability guarantees (adaptive clocking might help).
979 * So we assume JTAG access during SRST is off the menu unless it's
980 * been specifically enabled.
982 bool srst_asserted = false;
984 if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
985 && (jtag_reset_config & RESET_SRST_NO_GATING))
987 jtag_add_reset(0, 1);
988 srst_asserted = true;
991 if (target->reset_halt)
994 * Some targets do not support communication while SRST is asserted. We need to
995 * set up the reset vector catch here.
997 * If TRST is asserted, then these settings will be reset anyway, so setting them
1000 if (arm7_9->has_vector_catch)
1002 /* program vector catch register to catch reset vector */
1003 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
1005 /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
1006 jtag_add_runtest(1, jtag_get_end_state());
1010 /* program watchpoint unit to match on reset vector address */
1011 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
1012 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
1013 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1014 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1015 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1019 /* here we should issue an SRST only, but we may have to assert TRST as well */
1020 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1022 jtag_add_reset(1, 1);
1023 } else if (!srst_asserted)
1025 jtag_add_reset(0, 1);
1028 target->state = TARGET_RESET;
1029 jtag_add_sleep(50000);
1031 register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
1033 if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
1035 /* debug entry was already prepared in arm7_9_assert_reset() */
1036 target->debug_reason = DBG_REASON_DBGRQ;
1043 * Deassert the reset (SRST) signal on an ARM7/9 target. If SRST pulls TRST
1044 * and the target is being reset into a halt, a warning will be triggered
1045 * because it is not possible to reset into a halted mode in this case. The
1046 * target is halted using the target's functions.
1048 * @param target Pointer to the target to have the reset deasserted
1049 * @return ERROR_OK or an error from polling or halting the target
1051 int arm7_9_deassert_reset(struct target *target)
1053 int retval = ERROR_OK;
1054 LOG_DEBUG("target->state: %s",
1055 target_state_name(target));
1057 /* deassert reset lines */
1058 jtag_add_reset(0, 0);
1060 enum reset_types jtag_reset_config = jtag_get_reset_config();
1061 if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
1063 LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
1064 /* set up embedded ice registers again */
1065 if ((retval = target_examine_one(target)) != ERROR_OK)
1068 if ((retval = target_poll(target)) != ERROR_OK)
1073 if ((retval = target_halt(target)) != ERROR_OK)
1083 * Clears the halt condition for an ARM7/9 target. If it isn't coming out of
1084 * reset and if DBGRQ is used, it is progammed to be deasserted. If the reset
1085 * vector catch was used, it is restored. Otherwise, the control value is
1086 * restored and the watchpoint unit is restored if it was in use.
1088 * @param target Pointer to the ARM7/9 target to have halt cleared
1089 * @return Always ERROR_OK
1091 int arm7_9_clear_halt(struct target *target)
1093 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1094 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1096 /* we used DBGRQ only if we didn't come out of reset */
1097 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
1099 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
1101 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1102 embeddedice_store_reg(dbg_ctrl);
1106 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
1108 /* if we came out of reset, and vector catch is supported, we used
1109 * vector catch to enter debug state
1110 * restore the register in that case
1112 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
1116 /* restore registers if watchpoint unit 0 was in use
1118 if (arm7_9->wp0_used)
1120 if (arm7_9->debug_entry_from_reset)
1122 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
1124 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1125 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1126 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1128 /* control value always has to be restored, as it was either disabled,
1129 * or enabled with possibly different bits
1131 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1139 * Issue a software reset and halt to an ARM7/9 target. The target is halted
1140 * and then there is a wait until the processor shows the halt. This wait can
1141 * timeout and results in an error being returned. The software reset involves
1142 * clearing the halt, updating the debug control register, changing to ARM mode,
1143 * reset of the program counter, and reset of all of the registers.
1145 * @param target Pointer to the ARM7/9 target to be reset and halted by software
1146 * @return Error status if any of the commands fail, otherwise ERROR_OK
1148 int arm7_9_soft_reset_halt(struct target *target)
1150 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1151 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1152 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1153 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1157 /* FIX!!! replace some of this code with tcl commands
1159 * halt # the halt command is synchronous
1160 * armv4_5 core_state arm
1164 if ((retval = target_halt(target)) != ERROR_OK)
1167 long long then = timeval_ms();
1169 while (!(timeout = ((timeval_ms()-then) > 1000)))
1171 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
1173 embeddedice_read_reg(dbg_stat);
1174 if ((retval = jtag_execute_queue()) != ERROR_OK)
1176 if (debug_level >= 3)
1186 LOG_ERROR("Failed to halt CPU after 1 sec");
1187 return ERROR_TARGET_TIMEOUT;
1189 target->state = TARGET_HALTED;
1191 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1192 * ensure that DBGRQ is cleared
1194 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1195 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1196 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1197 embeddedice_store_reg(dbg_ctrl);
1199 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1204 /* if the target is in Thumb state, change to ARM state */
1205 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1207 uint32_t r0_thumb, pc_thumb;
1208 LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
1209 /* Entered debug from Thumb mode */
1210 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1211 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1214 /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */
1216 /* all register content is now invalid */
1217 register_cache_invalidate(armv4_5->core_cache);
1219 /* SVC, ARM state, IRQ and FIQ disabled */
1222 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
1225 arm_set_cpsr(armv4_5, cpsr);
1226 armv4_5->cpsr->dirty = 1;
1228 /* start fetching from 0x0 */
1229 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
1230 armv4_5->core_cache->reg_list[15].dirty = 1;
1231 armv4_5->core_cache->reg_list[15].valid = 1;
1233 /* reset registers */
1234 for (i = 0; i <= 14; i++)
1236 struct reg *r = arm_reg_current(armv4_5, i);
1238 buf_set_u32(r->value, 0, 32, 0xffffffff);
1243 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
1252 * Halt an ARM7/9 target. This is accomplished by either asserting the DBGRQ
1253 * line or by programming a watchpoint to trigger on any address. It is
1254 * considered a bug to call this function while the target is in the
1255 * TARGET_RESET state.
1257 * @param target Pointer to the ARM7/9 target to be halted
1258 * @return Always ERROR_OK
1260 int arm7_9_halt(struct target *target)
1262 if (target->state == TARGET_RESET)
1264 LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
1268 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1269 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1271 LOG_DEBUG("target->state: %s",
1272 target_state_name(target));
1274 if (target->state == TARGET_HALTED)
1276 LOG_DEBUG("target was already halted");
1280 if (target->state == TARGET_UNKNOWN)
1282 LOG_WARNING("target was in unknown state when halt was requested");
1285 if (arm7_9->use_dbgrq)
1287 /* program EmbeddedICE Debug Control Register to assert DBGRQ
1289 if (arm7_9->set_special_dbgrq) {
1290 arm7_9->set_special_dbgrq(target);
1292 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
1293 embeddedice_store_reg(dbg_ctrl);
1298 /* program watchpoint unit to match on any address
1300 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1301 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1302 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1303 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1306 target->debug_reason = DBG_REASON_DBGRQ;
1312 * Handle an ARM7/9 target's entry into debug mode. The halt is cleared on the
1313 * ARM. The JTAG queue is then executed and the reason for debug entry is
1314 * examined. Once done, the target is verified to be halted and the processor
1315 * is forced into ARM mode. The core registers are saved for the current core
1316 * mode and the program counter (register 15) is updated as needed. The core
1317 * registers and CPSR and SPSR are saved for restoration later.
1319 * @param target Pointer to target that is entering debug mode
1320 * @return Error code if anything fails, otherwise ERROR_OK
1322 static int arm7_9_debug_entry(struct target *target)
1325 uint32_t context[16];
1326 uint32_t* context_p[16];
1327 uint32_t r0_thumb, pc_thumb;
1328 uint32_t cpsr, cpsr_mask = 0;
1330 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1331 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1332 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
1333 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1335 #ifdef _DEBUG_ARM7_9_
1339 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
1340 * ensure that DBGRQ is cleared
1342 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1343 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
1344 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
1345 embeddedice_store_reg(dbg_ctrl);
1347 if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
1352 if ((retval = jtag_execute_queue()) != ERROR_OK)
1357 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
1361 if (target->state != TARGET_HALTED)
1363 LOG_WARNING("target not halted");
1364 return ERROR_TARGET_NOT_HALTED;
1367 /* if the target is in Thumb state, change to ARM state */
1368 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
1370 LOG_DEBUG("target entered debug from Thumb state");
1371 /* Entered debug from Thumb mode */
1372 armv4_5->core_state = ARMV4_5_STATE_THUMB;
1374 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
1375 LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32
1376 ", pc_thumb: 0x%8.8" PRIx32, r0_thumb, pc_thumb);
1377 } else if (buf_get_u32(dbg_stat->value, 5, 1)) {
1378 /* \todo Get some vaguely correct handling of Jazelle, if
1379 * anyone ever uses it and full info becomes available.
1380 * See ARM9EJS TRM B.7.1 for how to switch J->ARM; and
1381 * B.7.3 for the reverse. That'd be the bare minimum...
1383 LOG_DEBUG("target entered debug from Jazelle state");
1384 armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
1385 cpsr_mask = 1 << 24;
1386 LOG_ERROR("Jazelle debug entry -- BROKEN!");
1388 LOG_DEBUG("target entered debug from ARM state");
1389 /* Entered debug from ARM mode */
1390 armv4_5->core_state = ARMV4_5_STATE_ARM;
1393 for (i = 0; i < 16; i++)
1394 context_p[i] = &context[i];
1395 /* save core registers (r0 - r15 of current core mode) */
1396 arm7_9->read_core_regs(target, 0xffff, context_p);
1398 arm7_9->read_xpsr(target, &cpsr, 0);
1400 if ((retval = jtag_execute_queue()) != ERROR_OK)
1403 /* Sync our CPSR copy with J or T bits EICE reported, but
1404 * which we then erased by putting the core into ARM mode.
1406 arm_set_cpsr(armv4_5, cpsr | cpsr_mask);
1408 if (!is_arm_mode(armv4_5->core_mode))
1410 target->state = TARGET_UNKNOWN;
1411 LOG_ERROR("cpsr contains invalid mode value - communication failure");
1412 return ERROR_TARGET_FAILURE;
1415 LOG_DEBUG("target entered debug state in %s mode",
1416 arm_mode_name(armv4_5->core_mode));
1418 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1420 LOG_DEBUG("thumb state, applying fixups");
1421 context[0] = r0_thumb;
1422 context[15] = pc_thumb;
1423 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1425 /* adjust value stored by STM */
1426 context[15] -= 3 * 4;
1429 if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
1430 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1432 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1434 for (i = 0; i <= 15; i++)
1436 struct reg *r = arm_reg_current(armv4_5, i);
1438 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
1440 buf_set_u32(r->value, 0, 32, context[i]);
1441 /* r0 and r15 (pc) have to be restored later */
1442 r->dirty = (i == 0) || (i == 15);
1446 LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
1448 /* exceptions other than USR & SYS have a saved program status register */
1449 if (armv4_5->spsr) {
1451 arm7_9->read_xpsr(target, &spsr, 1);
1452 if ((retval = jtag_execute_queue()) != ERROR_OK)
1456 buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
1457 armv4_5->spsr->dirty = 0;
1458 armv4_5->spsr->valid = 1;
1461 if ((retval = jtag_execute_queue()) != ERROR_OK)
1464 if (arm7_9->post_debug_entry)
1465 arm7_9->post_debug_entry(target);
1471 * Validate the full context for an ARM7/9 target in all processor modes. If
1472 * there are any invalid registers for the target, they will all be read. This
1475 * @param target Pointer to the ARM7/9 target to capture the full context from
1476 * @return Error if the target is not halted, has an invalid core mode, or if
1477 * the JTAG queue fails to execute
1479 int arm7_9_full_context(struct target *target)
1483 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1484 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1488 if (target->state != TARGET_HALTED)
1490 LOG_WARNING("target not halted");
1491 return ERROR_TARGET_NOT_HALTED;
1494 if (!is_arm_mode(armv4_5->core_mode))
1497 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1498 * SYS shares registers with User, so we don't touch SYS
1500 for (i = 0; i < 6; i++)
1503 uint32_t* reg_p[16];
1507 /* check if there are invalid registers in the current mode
1509 for (j = 0; j <= 16; j++)
1511 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1519 /* change processor mode (and mask T bit) */
1520 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8)
1522 tmp_cpsr |= armv4_5_number_to_mode(i);
1524 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1526 for (j = 0; j < 15; j++)
1528 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1530 reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1532 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1533 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1537 /* if only the PSR is invalid, mask is all zeroes */
1539 arm7_9->read_core_regs(target, mask, reg_p);
1541 /* check if the PSR has to be read */
1542 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1544 arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1545 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1546 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1551 /* restore processor mode (mask T bit) */
1552 arm7_9->write_xpsr_im8(target,
1553 buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20,
1556 if ((retval = jtag_execute_queue()) != ERROR_OK)
1564 * Restore the processor context on an ARM7/9 target. The full processor
1565 * context is analyzed to see if any of the registers are dirty on this end, but
1566 * have a valid new value. If this is the case, the processor is changed to the
1567 * appropriate mode and the new register values are written out to the
1568 * processor. If there happens to be a dirty register with an invalid value, an
1569 * error will be logged.
1571 * @param target Pointer to the ARM7/9 target to have its context restored
1572 * @return Error status if the target is not halted or the core mode in the
1573 * armv4_5 struct is invalid.
1575 int arm7_9_restore_context(struct target *target)
1577 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1578 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1580 struct arm_reg *reg_arch_info;
1581 enum armv4_5_mode current_mode = armv4_5->core_mode;
1588 if (target->state != TARGET_HALTED)
1590 LOG_WARNING("target not halted");
1591 return ERROR_TARGET_NOT_HALTED;
1594 if (arm7_9->pre_restore_context)
1595 arm7_9->pre_restore_context(target);
1597 if (!is_arm_mode(armv4_5->core_mode))
1600 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1601 * SYS shares registers with User, so we don't touch SYS
1603 for (i = 0; i < 6; i++)
1605 LOG_DEBUG("examining %s mode",
1606 arm_mode_name(armv4_5->core_mode));
1609 /* check if there are dirty registers in the current mode
1611 for (j = 0; j <= 16; j++)
1613 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1614 reg_arch_info = reg->arch_info;
1615 if (reg->dirty == 1)
1617 if (reg->valid == 1)
1620 LOG_DEBUG("examining dirty reg: %s", reg->name);
1621 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1622 && (reg_arch_info->mode != current_mode)
1623 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1624 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1627 LOG_DEBUG("require mode change");
1632 LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1639 uint32_t mask = 0x0;
1647 /* change processor mode (mask T bit) */
1648 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value,
1650 tmp_cpsr |= armv4_5_number_to_mode(i);
1652 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1653 current_mode = armv4_5_number_to_mode(i);
1656 for (j = 0; j <= 14; j++)
1658 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1659 reg_arch_info = reg->arch_info;
1662 if (reg->dirty == 1)
1664 regs[j] = buf_get_u32(reg->value, 0, 32);
1669 LOG_DEBUG("writing register %i mode %s "
1670 "with value 0x%8.8" PRIx32, j,
1671 arm_mode_name(armv4_5->core_mode),
1678 arm7_9->write_core_regs(target, mask, regs);
1681 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1682 reg_arch_info = reg->arch_info;
1683 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1685 LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
1686 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1691 if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode))
1693 /* restore processor mode (mask T bit) */
1696 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
1697 tmp_cpsr |= armv4_5_number_to_mode(i);
1699 LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
1700 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1702 else if (armv4_5->cpsr->dirty)
1704 /* CPSR has been changed, full restore necessary (mask T bit) */
1705 LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1706 buf_get_u32(armv4_5->cpsr->value, 0, 32));
1707 arm7_9->write_xpsr(target,
1708 buf_get_u32(armv4_5->cpsr->value, 0, 32)
1710 armv4_5->cpsr->dirty = 0;
1711 armv4_5->cpsr->valid = 1;
1715 LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1716 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1717 armv4_5->core_cache->reg_list[15].dirty = 0;
1719 if (arm7_9->post_restore_context)
1720 arm7_9->post_restore_context(target);
1726 * Restart the core of an ARM7/9 target. A RESTART command is sent to the
1727 * instruction register and the JTAG state is set to TAP_IDLE causing a core
1730 * @param target Pointer to the ARM7/9 target to be restarted
1731 * @return Result of executing the JTAG queue
1733 int arm7_9_restart_core(struct target *target)
1735 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1736 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
1738 /* set RESTART instruction */
1739 jtag_set_end_state(TAP_IDLE);
1740 if (arm7_9->need_bypass_before_restart) {
1741 arm7_9->need_bypass_before_restart = 0;
1742 arm_jtag_set_instr(jtag_info, 0xf, NULL);
1744 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1746 jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
1747 return jtag_execute_queue();
1751 * Enable the watchpoints on an ARM7/9 target. The target's watchpoints are
1752 * iterated through and are set on the target if they aren't already set.
1754 * @param target Pointer to the ARM7/9 target to enable watchpoints on
1756 void arm7_9_enable_watchpoints(struct target *target)
1758 struct watchpoint *watchpoint = target->watchpoints;
1762 if (watchpoint->set == 0)
1763 arm7_9_set_watchpoint(target, watchpoint);
1764 watchpoint = watchpoint->next;
1769 * Enable the breakpoints on an ARM7/9 target. The target's breakpoints are
1770 * iterated through and are set on the target.
1772 * @param target Pointer to the ARM7/9 target to enable breakpoints on
1774 void arm7_9_enable_breakpoints(struct target *target)
1776 struct breakpoint *breakpoint = target->breakpoints;
1778 /* set any pending breakpoints */
1781 arm7_9_set_breakpoint(target, breakpoint);
1782 breakpoint = breakpoint->next;
1786 int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
1788 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1789 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1790 struct breakpoint *breakpoint = target->breakpoints;
1791 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1792 int err, retval = ERROR_OK;
1796 if (target->state != TARGET_HALTED)
1798 LOG_WARNING("target not halted");
1799 return ERROR_TARGET_NOT_HALTED;
1802 if (!debug_execution)
1804 target_free_all_working_areas(target);
1807 /* current = 1: continue on current pc, otherwise continue at <address> */
1809 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1811 uint32_t current_pc;
1812 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1814 /* the front-end may request us not to handle breakpoints */
1815 if (handle_breakpoints)
1817 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1819 LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
1820 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
1825 /* calculate PC of next instruction */
1827 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
1829 uint32_t current_opcode;
1830 target_read_u32(target, current_pc, ¤t_opcode);
1831 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
1835 LOG_DEBUG("enable single-step");
1836 arm7_9->enable_single_step(target, next_pc);
1838 target->debug_reason = DBG_REASON_SINGLESTEP;
1840 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1845 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1846 arm7_9->branch_resume(target);
1847 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1849 arm7_9->branch_resume_thumb(target);
1853 LOG_ERROR("unhandled core state");
1857 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1858 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1859 err = arm7_9_execute_sys_speed(target);
1861 LOG_DEBUG("disable single-step");
1862 arm7_9->disable_single_step(target);
1864 if (err != ERROR_OK)
1866 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1870 target->state = TARGET_UNKNOWN;
1874 arm7_9_debug_entry(target);
1875 LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1877 LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1878 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
1885 /* enable any pending breakpoints and watchpoints */
1886 arm7_9_enable_breakpoints(target);
1887 arm7_9_enable_watchpoints(target);
1889 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
1894 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1896 arm7_9->branch_resume(target);
1898 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1900 arm7_9->branch_resume_thumb(target);
1904 LOG_ERROR("unhandled core state");
1908 /* deassert DBGACK and INTDIS */
1909 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1910 /* INTDIS only when we really resume, not during debug execution */
1911 if (!debug_execution)
1912 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1913 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1915 if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
1920 target->debug_reason = DBG_REASON_NOTHALTED;
1922 if (!debug_execution)
1924 /* registers are now invalid */
1925 register_cache_invalidate(armv4_5->core_cache);
1926 target->state = TARGET_RUNNING;
1927 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
1934 target->state = TARGET_DEBUG_RUNNING;
1935 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
1941 LOG_DEBUG("target resumed");
1946 void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
1948 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1949 struct arm *armv4_5 = &arm7_9->armv4_5_common;
1950 uint32_t current_pc;
1951 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1953 if (next_pc != current_pc)
1955 /* setup an inverse breakpoint on the current PC
1956 * - comparator 1 matches the current address
1957 * - rangeout from comparator 1 is connected to comparator 0 rangein
1958 * - comparator 0 matches any address, as long as rangein is low */
1959 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1960 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1961 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1962 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
1963 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
1964 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1965 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1966 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1967 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1971 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1972 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1973 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
1974 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff);
1975 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
1976 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1977 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1978 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
1979 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
1983 void arm7_9_disable_eice_step(struct target *target)
1985 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
1987 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1988 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1989 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1990 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1991 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1992 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1993 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1994 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1995 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1998 int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
2000 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2001 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2002 struct breakpoint *breakpoint = NULL;
2005 if (target->state != TARGET_HALTED)
2007 LOG_WARNING("target not halted");
2008 return ERROR_TARGET_NOT_HALTED;
2011 /* current = 1: continue on current pc, otherwise continue at <address> */
2013 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
2015 uint32_t current_pc;
2016 current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2018 /* the front-end may request us not to handle breakpoints */
2019 if (handle_breakpoints)
2020 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
2021 if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
2026 target->debug_reason = DBG_REASON_SINGLESTEP;
2028 /* calculate PC of next instruction */
2030 if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
2032 uint32_t current_opcode;
2033 target_read_u32(target, current_pc, ¤t_opcode);
2034 LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
2038 if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
2043 arm7_9->enable_single_step(target, next_pc);
2045 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
2047 arm7_9->branch_resume(target);
2049 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
2051 arm7_9->branch_resume_thumb(target);
2055 LOG_ERROR("unhandled core state");
2059 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
2064 err = arm7_9_execute_sys_speed(target);
2065 arm7_9->disable_single_step(target);
2067 /* registers are now invalid */
2068 register_cache_invalidate(armv4_5->core_cache);
2070 if (err != ERROR_OK)
2072 target->state = TARGET_UNKNOWN;
2074 arm7_9_debug_entry(target);
2075 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
2079 LOG_DEBUG("target stepped");
2083 if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
2091 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
2092 int num, enum armv4_5_mode mode)
2094 uint32_t* reg_p[16];
2097 struct arm_reg *areg = r->arch_info;
2098 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2099 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2101 if (!is_arm_mode(armv4_5->core_mode))
2103 if ((num < 0) || (num > 16))
2104 return ERROR_INVALID_ARGUMENTS;
2106 if ((mode != ARMV4_5_MODE_ANY)
2107 && (mode != armv4_5->core_mode)
2108 && (areg->mode != ARMV4_5_MODE_ANY))
2112 /* change processor mode (mask T bit) */
2113 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2116 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2119 if ((num >= 0) && (num <= 15))
2121 /* read a normal core register */
2122 reg_p[num] = &value;
2124 arm7_9->read_core_regs(target, 1 << num, reg_p);
2128 /* read a program status register
2129 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
2131 arm7_9->read_xpsr(target, &value, areg->mode != ARMV4_5_MODE_ANY);
2134 if ((retval = jtag_execute_queue()) != ERROR_OK)
2141 buf_set_u32(r->value, 0, 32, value);
2143 if ((mode != ARMV4_5_MODE_ANY)
2144 && (mode != armv4_5->core_mode)
2145 && (areg->mode != ARMV4_5_MODE_ANY)) {
2146 /* restore processor mode (mask T bit) */
2147 arm7_9->write_xpsr_im8(target,
2148 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2155 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
2156 int num, enum armv4_5_mode mode, uint32_t value)
2159 struct arm_reg *areg = r->arch_info;
2160 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2161 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2163 if (!is_arm_mode(armv4_5->core_mode))
2165 if ((num < 0) || (num > 16))
2166 return ERROR_INVALID_ARGUMENTS;
2168 if ((mode != ARMV4_5_MODE_ANY)
2169 && (mode != armv4_5->core_mode)
2170 && (areg->mode != ARMV4_5_MODE_ANY)) {
2173 /* change processor mode (mask T bit) */
2174 tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0;
2177 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
2180 if ((num >= 0) && (num <= 15))
2182 /* write a normal core register */
2185 arm7_9->write_core_regs(target, 1 << num, reg);
2189 /* write a program status register
2190 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
2192 int spsr = (areg->mode != ARMV4_5_MODE_ANY);
2194 /* if we're writing the CPSR, mask the T bit */
2198 arm7_9->write_xpsr(target, value, spsr);
2204 if ((mode != ARMV4_5_MODE_ANY)
2205 && (mode != armv4_5->core_mode)
2206 && (areg->mode != ARMV4_5_MODE_ANY)) {
2207 /* restore processor mode (mask T bit) */
2208 arm7_9->write_xpsr_im8(target,
2209 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2213 return jtag_execute_queue();
2216 int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2218 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2219 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2221 uint32_t num_accesses = 0;
2222 int thisrun_accesses;
2228 LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
2230 if (target->state != TARGET_HALTED)
2232 LOG_WARNING("target not halted");
2233 return ERROR_TARGET_NOT_HALTED;
2236 /* sanitize arguments */
2237 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2238 return ERROR_INVALID_ARGUMENTS;
2240 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2241 return ERROR_TARGET_UNALIGNED_ACCESS;
2243 /* load the base register with the address of the first word */
2245 arm7_9->write_core_regs(target, 0x1, reg);
2252 while (num_accesses < count)
2255 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2256 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2258 if (last_reg <= thisrun_accesses)
2259 last_reg = thisrun_accesses;
2261 arm7_9->load_word_regs(target, reg_list);
2263 /* fast memory reads are only safe when the target is running
2264 * from a sufficiently high clock (32 kHz is usually too slow)
2266 if (arm7_9->fast_memory_access)
2267 retval = arm7_9_execute_fast_sys_speed(target);
2269 retval = arm7_9_execute_sys_speed(target);
2270 if (retval != ERROR_OK)
2273 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
2275 /* advance buffer, count number of accesses */
2276 buffer += thisrun_accesses * 4;
2277 num_accesses += thisrun_accesses;
2279 if ((j++%1024) == 0)
2286 while (num_accesses < count)
2289 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2290 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2292 for (i = 1; i <= thisrun_accesses; i++)
2296 arm7_9->load_hword_reg(target, i);
2297 /* fast memory reads are only safe when the target is running
2298 * from a sufficiently high clock (32 kHz is usually too slow)
2300 if (arm7_9->fast_memory_access)
2301 retval = arm7_9_execute_fast_sys_speed(target);
2303 retval = arm7_9_execute_sys_speed(target);
2304 if (retval != ERROR_OK)
2311 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
2313 /* advance buffer, count number of accesses */
2314 buffer += thisrun_accesses * 2;
2315 num_accesses += thisrun_accesses;
2317 if ((j++%1024) == 0)
2324 while (num_accesses < count)
2327 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2328 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2330 for (i = 1; i <= thisrun_accesses; i++)
2334 arm7_9->load_byte_reg(target, i);
2335 /* fast memory reads are only safe when the target is running
2336 * from a sufficiently high clock (32 kHz is usually too slow)
2338 if (arm7_9->fast_memory_access)
2339 retval = arm7_9_execute_fast_sys_speed(target);
2341 retval = arm7_9_execute_sys_speed(target);
2342 if (retval != ERROR_OK)
2348 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
2350 /* advance buffer, count number of accesses */
2351 buffer += thisrun_accesses * 1;
2352 num_accesses += thisrun_accesses;
2354 if ((j++%1024) == 0)
2361 LOG_ERROR("BUG: we shouldn't get here");
2366 if (!is_arm_mode(armv4_5->core_mode))
2369 for (i = 0; i <= last_reg; i++) {
2370 struct reg *r = arm_reg_current(armv4_5, i);
2372 r->dirty = r->valid;
2375 arm7_9->read_xpsr(target, &cpsr, 0);
2376 if ((retval = jtag_execute_queue()) != ERROR_OK)
2378 LOG_ERROR("JTAG error while reading cpsr");
2379 return ERROR_TARGET_DATA_ABORT;
2382 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2384 LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2386 arm7_9->write_xpsr_im8(target,
2387 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2390 return ERROR_TARGET_DATA_ABORT;
2396 int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
2398 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2399 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2400 struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
2403 uint32_t num_accesses = 0;
2404 int thisrun_accesses;
2410 #ifdef _DEBUG_ARM7_9_
2411 LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
2414 if (target->state != TARGET_HALTED)
2416 LOG_WARNING("target not halted");
2417 return ERROR_TARGET_NOT_HALTED;
2420 /* sanitize arguments */
2421 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
2422 return ERROR_INVALID_ARGUMENTS;
2424 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
2425 return ERROR_TARGET_UNALIGNED_ACCESS;
2427 /* load the base register with the address of the first word */
2429 arm7_9->write_core_regs(target, 0x1, reg);
2431 /* Clear DBGACK, to make sure memory fetches work as expected */
2432 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
2433 embeddedice_store_reg(dbg_ctrl);
2438 while (num_accesses < count)
2441 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2442 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2444 for (i = 1; i <= thisrun_accesses; i++)
2448 reg[i] = target_buffer_get_u32(target, buffer);
2452 arm7_9->write_core_regs(target, reg_list, reg);
2454 arm7_9->store_word_regs(target, reg_list);
2456 /* fast memory writes are only safe when the target is running
2457 * from a sufficiently high clock (32 kHz is usually too slow)
2459 if (arm7_9->fast_memory_access)
2460 retval = arm7_9_execute_fast_sys_speed(target);
2462 retval = arm7_9_execute_sys_speed(target);
2463 if (retval != ERROR_OK)
2468 num_accesses += thisrun_accesses;
2472 while (num_accesses < count)
2475 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2476 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2478 for (i = 1; i <= thisrun_accesses; i++)
2482 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
2486 arm7_9->write_core_regs(target, reg_list, reg);
2488 for (i = 1; i <= thisrun_accesses; i++)
2490 arm7_9->store_hword_reg(target, i);
2492 /* fast memory writes are only safe when the target is running
2493 * from a sufficiently high clock (32 kHz is usually too slow)
2495 if (arm7_9->fast_memory_access)
2496 retval = arm7_9_execute_fast_sys_speed(target);
2498 retval = arm7_9_execute_sys_speed(target);
2499 if (retval != ERROR_OK)
2505 num_accesses += thisrun_accesses;
2509 while (num_accesses < count)
2512 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
2513 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
2515 for (i = 1; i <= thisrun_accesses; i++)
2519 reg[i] = *buffer++ & 0xff;
2522 arm7_9->write_core_regs(target, reg_list, reg);
2524 for (i = 1; i <= thisrun_accesses; i++)
2526 arm7_9->store_byte_reg(target, i);
2527 /* fast memory writes are only safe when the target is running
2528 * from a sufficiently high clock (32 kHz is usually too slow)
2530 if (arm7_9->fast_memory_access)
2531 retval = arm7_9_execute_fast_sys_speed(target);
2533 retval = arm7_9_execute_sys_speed(target);
2534 if (retval != ERROR_OK)
2541 num_accesses += thisrun_accesses;
2545 LOG_ERROR("BUG: we shouldn't get here");
2551 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2552 embeddedice_store_reg(dbg_ctrl);
2554 if (!is_arm_mode(armv4_5->core_mode))
2557 for (i = 0; i <= last_reg; i++) {
2558 struct reg *r = arm_reg_current(armv4_5, i);
2560 r->dirty = r->valid;
2563 arm7_9->read_xpsr(target, &cpsr, 0);
2564 if ((retval = jtag_execute_queue()) != ERROR_OK)
2566 LOG_ERROR("JTAG error while reading cpsr");
2567 return ERROR_TARGET_DATA_ABORT;
2570 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2572 LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
2574 arm7_9->write_xpsr_im8(target,
2575 buf_get_u32(armv4_5->cpsr->value, 0, 8)
2578 return ERROR_TARGET_DATA_ABORT;
2584 static int dcc_count;
2585 static uint8_t *dcc_buffer;
2587 static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
2589 int retval = ERROR_OK;
2590 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2592 if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
2595 int little = target->endianness == TARGET_LITTLE_ENDIAN;
2596 int count = dcc_count;
2597 uint8_t *buffer = dcc_buffer;
2600 /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
2601 * core function repeated. */
2602 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2605 struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
2606 uint8_t reg_addr = ice_reg->addr & 0x1f;
2607 struct jtag_tap *tap;
2608 tap = ice_reg->jtag_info->tap;
2610 embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
2611 buffer += (count-2)*4;
2613 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2617 for (i = 0; i < count; i++)
2619 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
2624 if ((retval = target_halt(target))!= ERROR_OK)
2628 return target_wait_state(target, TARGET_HALTED, 500);
2631 static const uint32_t dcc_code[] =
2633 /* r0 == input, points to memory buffer
2637 /* spin until DCC control (c0) reports data arrived */
2638 0xee101e10, /* w: mrc p14, #0, r1, c0, c0 */
2639 0xe3110001, /* tst r1, #1 */
2640 0x0afffffc, /* bne w */
2642 /* read word from DCC (c1), write to memory */
2643 0xee111e10, /* mrc p14, #0, r1, c1, c0 */
2644 0xe4801004, /* str r1, [r0], #4 */
2647 0xeafffff9 /* b w */
2650 extern int armv4_5_run_algorithm_inner(struct target *target,
2651 int num_mem_params, struct mem_param *mem_params,
2652 int num_reg_params, struct reg_param *reg_params,
2653 uint32_t entry_point, uint32_t exit_point,
2654 int timeout_ms, void *arch_info,
2655 int (*run_it)(struct target *target, uint32_t exit_point,
2656 int timeout_ms, void *arch_info));
2658 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
2661 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2664 if (!arm7_9->dcc_downloads)
2665 return target_write_memory(target, address, 4, count, buffer);
2667 /* regrab previously allocated working_area, or allocate a new one */
2668 if (!arm7_9->dcc_working_area)
2670 uint8_t dcc_code_buf[6 * 4];
2672 /* make sure we have a working area */
2673 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2675 LOG_INFO("no working area available, falling back to memory writes");
2676 return target_write_memory(target, address, 4, count, buffer);
2679 /* copy target instructions to target endianness */
2680 for (i = 0; i < 6; i++)
2682 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2685 /* write DCC code to working area */
2686 if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
2692 struct armv4_5_algorithm armv4_5_info;
2693 struct reg_param reg_params[1];
2695 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2696 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2697 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2699 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
2701 buf_set_u32(reg_params[0].value, 0, 32, address);
2704 dcc_buffer = buffer;
2705 retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
2706 arm7_9->dcc_working_area->address,
2707 arm7_9->dcc_working_area->address + 6*4,
2708 20*1000, &armv4_5_info, arm7_9_dcc_completion);
2710 if (retval == ERROR_OK)
2712 uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
2713 if (endaddress != (address + count*4))
2715 LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
2716 retval = ERROR_FAIL;
2720 destroy_reg_param(®_params[0]);
2726 * Perform per-target setup that requires JTAG access.
2728 int arm7_9_examine(struct target *target)
2730 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2733 if (!target_was_examined(target)) {
2734 struct reg_cache *t, **cache_p;
2736 t = embeddedice_build_reg_cache(target, arm7_9);
2740 cache_p = register_get_last_cache_p(&target->reg_cache);
2742 arm7_9->eice_cache = (*cache_p);
2744 if (arm7_9->armv4_5_common.etm)
2745 (*cache_p)->next = etm_build_reg_cache(target,
2747 arm7_9->armv4_5_common.etm);
2749 target_set_examined(target);
2752 retval = embeddedice_setup(target);
2753 if (retval == ERROR_OK)
2754 retval = arm7_9_setup(target);
2755 if (retval == ERROR_OK && arm7_9->armv4_5_common.etm)
2756 retval = etm_setup(target);
2760 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
2762 struct target *target = get_current_target(CMD_CTX);
2763 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2765 if (!is_arm7_9(arm7_9))
2767 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2768 return ERROR_TARGET_INVALID;
2772 COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
2774 command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2779 COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
2781 struct target *target = get_current_target(CMD_CTX);
2782 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2784 if (!is_arm7_9(arm7_9))
2786 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2787 return ERROR_TARGET_INVALID;
2791 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
2793 command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2798 COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
2800 struct target *target = get_current_target(CMD_CTX);
2801 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
2803 if (!is_arm7_9(arm7_9))
2805 command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
2806 return ERROR_TARGET_INVALID;
2810 COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
2812 command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2817 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
2819 int retval = ERROR_OK;
2820 struct arm *armv4_5 = &arm7_9->armv4_5_common;
2822 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2824 if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
2827 /* caller must have allocated via calloc(), so everything's zeroed */
2829 arm7_9->wp_available_max = 2;
2831 arm7_9->fast_memory_access = false;
2832 arm7_9->dcc_downloads = false;
2834 armv4_5->arch_info = arm7_9;
2835 armv4_5->read_core_reg = arm7_9_read_core_reg;
2836 armv4_5->write_core_reg = arm7_9_write_core_reg;
2837 armv4_5->full_context = arm7_9_full_context;
2839 if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
2842 return target_register_timer_callback(arm7_9_handle_target_request,
2846 static const struct command_registration arm7_9_any_command_handlers[] = {
2849 .handler = &handle_arm7_9_dbgrq_command,
2850 .mode = COMMAND_ANY,
2851 .usage = "<enable|disable>",
2852 .help = "use EmbeddedICE dbgrq instead of breakpoint "
2853 "for target halt requests",
2856 "fast_memory_access",
2857 .handler = &handle_arm7_9_fast_memory_access_command,
2858 .mode = COMMAND_ANY,
2859 .usage = "<enable|disable>",
2860 .help = "use fast memory accesses instead of slower "
2861 "but potentially safer accesses",
2865 .handler = &handle_arm7_9_dcc_downloads_command,
2866 .mode = COMMAND_ANY,
2867 .usage = "<enable | disable>",
2868 .help = "use DCC downloads for larger memory writes",
2870 COMMAND_REGISTRATION_DONE
2872 const struct command_registration arm7_9_command_handlers[] = {
2874 .chain = arm_command_handlers,
2877 .chain = etm_command_handlers,
2881 .mode = COMMAND_ANY,
2882 .help = "arm7/9 specific commands",
2883 .chain = arm7_9_any_command_handlers,
2885 COMMAND_REGISTRATION_DONE