1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
39 #include <sys/types.h>
44 int arm7_9_debug_entry(target_t *target);
45 int arm7_9_enable_sw_bkpts(struct target_s *target);
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
57 int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
59 int arm7_9_reinit_embeddedice(target_t *target)
61 armv4_5_common_t *armv4_5 = target->arch_info;
62 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
64 breakpoint_t *breakpoint = target->breakpoints;
66 arm7_9->wp_available = 2;
70 /* mark all hardware breakpoints as unset */
73 if (breakpoint->type == BKPT_HARD)
77 breakpoint = breakpoint->next;
80 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
82 arm7_9->sw_bkpts_enabled = 0;
83 arm7_9_enable_sw_bkpts(target);
86 arm7_9->reinit_embeddedice = 0;
91 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
93 target_t *target = priv;
94 armv4_5_common_t *armv4_5 = target->arch_info;
95 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
97 /* a test-logic reset occured
98 * the EmbeddedICE registers have been reset
99 * hardware breakpoints have been cleared
101 if (event == JTAG_TRST_ASSERTED)
103 arm7_9->reinit_embeddedice = 1;
109 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
111 armv4_5_common_t *armv4_5 = target->arch_info;
112 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
114 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
119 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
124 *armv4_5_p = armv4_5;
130 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
132 armv4_5_common_t *armv4_5 = target->arch_info;
133 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
135 if (target->state != TARGET_HALTED)
137 WARNING("target not halted");
138 return ERROR_TARGET_NOT_HALTED;
141 if (arm7_9->force_hw_bkpts)
142 breakpoint->type = BKPT_HARD;
146 WARNING("breakpoint already set");
150 if (breakpoint->type == BKPT_HARD)
152 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
153 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
154 if (!arm7_9->wp0_used)
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
160 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
162 jtag_execute_queue();
163 arm7_9->wp0_used = 1;
166 else if (!arm7_9->wp1_used)
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
172 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
174 jtag_execute_queue();
175 arm7_9->wp1_used = 1;
180 ERROR("BUG: no hardware comparator available");
184 else if (breakpoint->type == BKPT_SOFT)
186 if (breakpoint->length == 4)
188 /* keep the original instruction in target endianness */
189 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
190 /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
191 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
195 /* keep the original instruction in target endianness */
196 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
197 /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
198 target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
207 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
209 armv4_5_common_t *armv4_5 = target->arch_info;
210 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
212 if (target->state != TARGET_HALTED)
214 WARNING("target not halted");
215 return ERROR_TARGET_NOT_HALTED;
218 if (!breakpoint->set)
220 WARNING("breakpoint not set");
224 if (breakpoint->type == BKPT_HARD)
226 if (breakpoint->set == 1)
228 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
229 jtag_execute_queue();
230 arm7_9->wp0_used = 0;
232 else if (breakpoint->set == 2)
234 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
235 jtag_execute_queue();
236 arm7_9->wp1_used = 0;
242 /* restore original instruction (kept in target endianness) */
243 if (breakpoint->length == 4)
245 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
249 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
257 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
259 armv4_5_common_t *armv4_5 = target->arch_info;
260 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
262 if (target->state != TARGET_HALTED)
264 WARNING("target not halted");
265 return ERROR_TARGET_NOT_HALTED;
268 if (arm7_9->force_hw_bkpts)
270 DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
271 breakpoint->type = BKPT_HARD;
274 if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
276 INFO("sw breakpoint requested, but software breakpoints not enabled");
277 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
280 if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
282 INFO("no watchpoint unit available for hardware breakpoint");
283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
286 if ((breakpoint->length != 2) && (breakpoint->length != 4))
288 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
289 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
292 if (breakpoint->type == BKPT_HARD)
293 arm7_9->wp_available--;
298 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
300 armv4_5_common_t *armv4_5 = target->arch_info;
301 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
303 if (target->state != TARGET_HALTED)
305 WARNING("target not halted");
306 return ERROR_TARGET_NOT_HALTED;
311 arm7_9_unset_breakpoint(target, breakpoint);
314 if (breakpoint->type == BKPT_HARD)
315 arm7_9->wp_available++;
320 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
322 armv4_5_common_t *armv4_5 = target->arch_info;
323 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
327 mask = watchpoint->length - 1;
329 if (target->state != TARGET_HALTED)
331 WARNING("target not halted");
332 return ERROR_TARGET_NOT_HALTED;
335 if (watchpoint->rw == WPT_ACCESS)
340 if (!arm7_9->wp0_used)
342 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
343 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
344 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
345 if( watchpoint->mask != 0xffffffffu )
346 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
347 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
348 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
350 jtag_execute_queue();
352 arm7_9->wp0_used = 2;
354 else if (!arm7_9->wp1_used)
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
357 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
359 if( watchpoint->mask != 0xffffffffu )
360 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
361 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
362 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
364 jtag_execute_queue();
366 arm7_9->wp1_used = 2;
370 ERROR("BUG: no hardware comparator available");
377 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
379 armv4_5_common_t *armv4_5 = target->arch_info;
380 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
382 if (target->state != TARGET_HALTED)
384 WARNING("target not halted");
385 return ERROR_TARGET_NOT_HALTED;
388 if (!watchpoint->set)
390 WARNING("breakpoint not set");
394 if (watchpoint->set == 1)
396 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
397 jtag_execute_queue();
398 arm7_9->wp0_used = 0;
400 else if (watchpoint->set == 2)
402 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
403 jtag_execute_queue();
404 arm7_9->wp1_used = 0;
411 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
413 armv4_5_common_t *armv4_5 = target->arch_info;
414 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
416 if (target->state != TARGET_HALTED)
418 WARNING("target not halted");
419 return ERROR_TARGET_NOT_HALTED;
422 if (arm7_9->wp_available < 1)
424 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
427 if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
429 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
432 arm7_9->wp_available--;
437 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
439 armv4_5_common_t *armv4_5 = target->arch_info;
440 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
442 if (target->state != TARGET_HALTED)
444 WARNING("target not halted");
445 return ERROR_TARGET_NOT_HALTED;
450 arm7_9_unset_watchpoint(target, watchpoint);
453 arm7_9->wp_available++;
458 int arm7_9_enable_sw_bkpts(struct target_s *target)
460 armv4_5_common_t *armv4_5 = target->arch_info;
461 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
464 if (arm7_9->sw_bkpts_enabled)
467 if (arm7_9->wp_available < 1)
469 WARNING("can't enable sw breakpoints with no watchpoint unit available");
470 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
472 arm7_9->wp_available--;
474 if (!arm7_9->wp0_used)
476 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
477 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
478 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
479 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
480 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
481 arm7_9->sw_bkpts_enabled = 1;
482 arm7_9->wp0_used = 3;
484 else if (!arm7_9->wp1_used)
486 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
487 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
488 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
489 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
490 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
491 arm7_9->sw_bkpts_enabled = 2;
492 arm7_9->wp1_used = 3;
496 ERROR("BUG: both watchpoints used, but wp_available >= 1");
500 if ((retval = jtag_execute_queue()) != ERROR_OK)
502 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
509 int arm7_9_disable_sw_bkpts(struct target_s *target)
511 armv4_5_common_t *armv4_5 = target->arch_info;
512 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
514 if (!arm7_9->sw_bkpts_enabled)
517 if (arm7_9->sw_bkpts_enabled == 1)
519 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
520 arm7_9->sw_bkpts_enabled = 0;
521 arm7_9->wp0_used = 0;
522 arm7_9->wp_available++;
524 else if (arm7_9->sw_bkpts_enabled == 2)
526 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
527 arm7_9->sw_bkpts_enabled = 0;
528 arm7_9->wp1_used = 0;
529 arm7_9->wp_available++;
535 int arm7_9_execute_sys_speed(struct target_s *target)
540 armv4_5_common_t *armv4_5 = target->arch_info;
541 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
542 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
543 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
545 /* set RESTART instruction */
546 jtag_add_end_state(TAP_RTI);
547 arm_jtag_set_instr(jtag_info, 0x4, NULL);
549 for (timeout=0; timeout<50; timeout++)
551 /* read debug status register */
552 embeddedice_read_reg(dbg_stat);
553 if ((retval = jtag_execute_queue()) != ERROR_OK)
555 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
556 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
562 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
563 return ERROR_TARGET_TIMEOUT;
569 int arm7_9_execute_fast_sys_speed(struct target_s *target)
571 u8 check_value[4], check_mask[4];
573 armv4_5_common_t *armv4_5 = target->arch_info;
574 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
575 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
576 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
578 /* set RESTART instruction */
579 jtag_add_end_state(TAP_RTI);
580 arm_jtag_set_instr(jtag_info, 0x4, NULL);
582 /* check for DBGACK and SYSCOMP set (others don't care) */
583 buf_set_u32(check_value, 0, 32, 0x9);
584 buf_set_u32(check_mask, 0, 32, 0x9);
586 /* read debug status register */
587 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
592 enum target_state arm7_9_poll(target_t *target)
595 armv4_5_common_t *armv4_5 = target->arch_info;
596 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
597 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
599 if (arm7_9->reinit_embeddedice)
601 arm7_9_reinit_embeddedice(target);
604 /* read debug status register */
605 embeddedice_read_reg(dbg_stat);
606 if ((retval = jtag_execute_queue()) != ERROR_OK)
610 case ERROR_JTAG_QUEUE_FAILED:
611 ERROR("JTAG queue failed while reading EmbeddedICE status register");
619 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
621 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
622 if ((target->state == TARGET_UNKNOWN))
624 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
625 target->state = TARGET_RUNNING;
627 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
629 target->state = TARGET_HALTED;
630 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
633 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
635 if (target->state == TARGET_DEBUG_RUNNING)
637 target->state = TARGET_HALTED;
638 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
641 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
646 if (target->state != TARGET_DEBUG_RUNNING)
647 target->state = TARGET_RUNNING;
650 return target->state;
653 int arm7_9_assert_reset(target_t *target)
657 DEBUG("target->state: %s", target_state_strings[target->state]);
659 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
661 /* if the target wasn't running, there might be working areas allocated */
662 target_free_all_working_areas(target);
664 /* assert SRST and TRST */
665 /* system would get ouf sync if we didn't reset test-logic, too */
666 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
668 if (retval == ERROR_JTAG_RESET_CANT_SRST)
670 WARNING("can't assert srst");
675 ERROR("unknown error");
679 jtag_add_sleep(5000);
680 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
682 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
684 WARNING("srst resets test logic, too");
685 retval = jtag_add_reset(1, 1);
691 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
693 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
695 WARNING("srst resets test logic, too");
696 retval = jtag_add_reset(1, 1);
699 if (retval == ERROR_JTAG_RESET_CANT_SRST)
701 WARNING("can't assert srst");
704 else if (retval != ERROR_OK)
706 ERROR("unknown error");
712 target->state = TARGET_RESET;
713 jtag_add_sleep(50000);
715 armv4_5_invalidate_core_regs(target);
721 int arm7_9_deassert_reset(target_t *target)
723 DEBUG("target->state: %s", target_state_strings[target->state]);
725 /* deassert reset lines */
726 jtag_add_reset(0, 0);
731 int arm7_9_clear_halt(target_t *target)
733 armv4_5_common_t *armv4_5 = target->arch_info;
734 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
735 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
737 /* we used DBGRQ only if we didn't come out of reset */
738 if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
740 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
742 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
743 embeddedice_store_reg(dbg_ctrl);
747 if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
749 /* if we came out of reset, and vector catch is supported, we used
750 * vector catch to enter debug state
751 * restore the register in that case
753 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
757 /* restore registers if watchpoint unit 0 was in use
759 if (arm7_9->wp0_used)
761 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
762 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
763 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
765 /* control value always has to be restored, as it was either disabled,
766 * or enabled with possibly different bits
768 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
775 int arm7_9_soft_reset_halt(struct target_s *target)
777 armv4_5_common_t *armv4_5 = target->arch_info;
778 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
779 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
780 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
783 if (target->state == TARGET_RUNNING)
785 target->type->halt(target);
788 while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
790 embeddedice_read_reg(dbg_stat);
791 jtag_execute_queue();
793 target->state = TARGET_HALTED;
795 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
796 * ensure that DBGRQ is cleared
798 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
799 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
800 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
801 embeddedice_store_reg(dbg_ctrl);
803 arm7_9_clear_halt(target);
805 /* if the target is in Thumb state, change to ARM state */
806 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
808 u32 r0_thumb, pc_thumb;
809 DEBUG("target entered debug from Thumb state, changing to ARM");
810 /* Entered debug from Thumb mode */
811 armv4_5->core_state = ARMV4_5_STATE_THUMB;
812 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
815 /* all register content is now invalid */
816 armv4_5_invalidate_core_regs(target);
818 /* SVC, ARM state, IRQ and FIQ disabled */
819 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
820 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
821 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
823 /* start fetching from 0x0 */
824 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
825 armv4_5->core_cache->reg_list[15].dirty = 1;
826 armv4_5->core_cache->reg_list[15].valid = 1;
828 armv4_5->core_mode = ARMV4_5_MODE_SVC;
829 armv4_5->core_state = ARMV4_5_STATE_ARM;
831 /* reset registers */
832 for (i = 0; i <= 14; i++)
834 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
835 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
836 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
839 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
844 int arm7_9_prepare_reset_halt(target_t *target)
846 armv4_5_common_t *armv4_5 = target->arch_info;
847 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
849 /* poll the target, and resume if it was currently halted */
851 if (target->state == TARGET_HALTED)
853 arm7_9_resume(target, 1, 0x0, 0, 1);
856 if (arm7_9->has_vector_catch)
858 /* program vector catch register to catch reset vector */
859 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
863 /* program watchpoint unit to match on reset vector address */
864 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
865 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
866 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
867 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
873 int arm7_9_halt(target_t *target)
875 armv4_5_common_t *armv4_5 = target->arch_info;
876 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
877 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
879 DEBUG("target->state: %s", target_state_strings[target->state]);
881 if (target->state == TARGET_HALTED)
883 WARNING("target was already halted");
884 return ERROR_TARGET_ALREADY_HALTED;
887 if (target->state == TARGET_UNKNOWN)
889 WARNING("target was in unknown state when halt was requested");
892 if (target->state == TARGET_RESET)
894 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
896 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
897 return ERROR_TARGET_FAILURE;
901 /* we came here in a reset_halt or reset_init sequence
902 * debug entry was already prepared in arm7_9_prepare_reset_halt()
904 target->debug_reason = DBG_REASON_DBGRQ;
910 if (arm7_9->use_dbgrq)
912 /* program EmbeddedICE Debug Control Register to assert DBGRQ
914 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
915 embeddedice_store_reg(dbg_ctrl);
919 /* program watchpoint unit to match on any address
921 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
922 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
923 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
924 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
927 target->debug_reason = DBG_REASON_DBGRQ;
932 int arm7_9_debug_entry(target_t *target)
937 u32 r0_thumb, pc_thumb;
940 /* get pointers to arch-specific information */
941 armv4_5_common_t *armv4_5 = target->arch_info;
942 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
943 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
944 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
946 #ifdef _DEBUG_ARM7_9_
950 if (arm7_9->pre_debug_entry)
951 arm7_9->pre_debug_entry(target);
953 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
954 * ensure that DBGRQ is cleared
956 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
957 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
958 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
959 embeddedice_store_reg(dbg_ctrl);
961 arm7_9_clear_halt(target);
963 if ((retval = jtag_execute_queue()) != ERROR_OK)
967 case ERROR_JTAG_QUEUE_FAILED:
968 ERROR("JTAG queue failed while writing EmbeddedICE control register");
976 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
980 if (target->state != TARGET_HALTED)
982 WARNING("target not halted");
983 return ERROR_TARGET_NOT_HALTED;
986 /* if the target is in Thumb state, change to ARM state */
987 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
989 DEBUG("target entered debug from Thumb state");
990 /* Entered debug from Thumb mode */
991 armv4_5->core_state = ARMV4_5_STATE_THUMB;
992 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
993 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
997 DEBUG("target entered debug from ARM state");
998 /* Entered debug from ARM mode */
999 armv4_5->core_state = ARMV4_5_STATE_ARM;
1002 for (i = 0; i < 16; i++)
1003 context_p[i] = &context[i];
1004 /* save core registers (r0 - r15 of current core mode) */
1005 arm7_9->read_core_regs(target, 0xffff, context_p);
1007 arm7_9->read_xpsr(target, &cpsr, 0);
1009 if ((retval = jtag_execute_queue()) != ERROR_OK)
1012 /* if the core has been executing in Thumb state, set the T bit */
1013 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1016 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
1017 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1018 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1020 armv4_5->core_mode = cpsr & 0x1f;
1022 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
1024 target->state = TARGET_UNKNOWN;
1025 ERROR("cpsr contains invalid mode value - communication failure");
1026 return ERROR_TARGET_FAILURE;
1029 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
1031 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1033 DEBUG("thumb state, applying fixups");
1034 context[0] = r0_thumb;
1035 context[15] = pc_thumb;
1036 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1038 /* adjust value stored by STM */
1039 context[15] -= 3 * 4;
1042 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
1043 || (target->debug_reason == DBG_REASON_SINGLESTEP)
1044 || (target->debug_reason == DBG_REASON_WATCHPOINT)
1045 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
1046 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
1047 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1048 else if (target->debug_reason == DBG_REASON_DBGRQ)
1049 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
1052 ERROR("unknown debug reason: %i", target->debug_reason);
1056 for (i=0; i<=15; i++)
1058 DEBUG("r%i: 0x%8.8x", i, context[i]);
1059 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1060 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1061 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1064 DEBUG("entered debug state at PC 0x%x", context[15]);
1066 /* exceptions other than USR & SYS have a saved program status register */
1067 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1070 arm7_9->read_xpsr(target, &spsr, 1);
1071 jtag_execute_queue();
1072 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1073 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1074 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1077 /* r0 and r15 (pc) have to be restored later */
1078 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1079 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1081 if ((retval = jtag->execute_queue()) != ERROR_OK)
1084 if (arm7_9->post_debug_entry)
1085 arm7_9->post_debug_entry(target);
1090 int arm7_9_full_context(target_t *target)
1094 armv4_5_common_t *armv4_5 = target->arch_info;
1095 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1099 if (target->state != TARGET_HALTED)
1101 WARNING("target not halted");
1102 return ERROR_TARGET_NOT_HALTED;
1105 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1106 * SYS shares registers with User, so we don't touch SYS
1108 for(i = 0; i < 6; i++)
1115 /* check if there are invalid registers in the current mode
1117 for (j = 0; j <= 16; j++)
1119 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1127 /* change processor mode (and mask T bit) */
1128 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1129 tmp_cpsr |= armv4_5_number_to_mode(i);
1131 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1133 for (j = 0; j < 15; j++)
1135 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1137 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1139 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1140 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1144 /* if only the PSR is invalid, mask is all zeroes */
1146 arm7_9->read_core_regs(target, mask, reg_p);
1148 /* check if the PSR has to be read */
1149 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1151 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1152 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1153 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1158 /* restore processor mode (mask T bit) */
1159 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1161 if ((retval = jtag_execute_queue()) != ERROR_OK)
1163 ERROR("JTAG failure");
1169 int arm7_9_restore_context(target_t *target)
1171 armv4_5_common_t *armv4_5 = target->arch_info;
1172 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1174 armv4_5_core_reg_t *reg_arch_info;
1175 enum armv4_5_mode current_mode = armv4_5->core_mode;
1182 if (target->state != TARGET_HALTED)
1184 WARNING("target not halted");
1185 return ERROR_TARGET_NOT_HALTED;
1188 if (arm7_9->pre_restore_context)
1189 arm7_9->pre_restore_context(target);
1191 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1192 * SYS shares registers with User, so we don't touch SYS
1194 for (i = 0; i < 6; i++)
1196 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1199 /* check if there are dirty registers in the current mode
1201 for (j = 0; j <= 16; j++)
1203 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1204 reg_arch_info = reg->arch_info;
1205 if (reg->dirty == 1)
1207 if (reg->valid == 1)
1210 DEBUG("examining dirty reg: %s", reg->name);
1211 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1212 && (reg_arch_info->mode != current_mode)
1213 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1214 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1217 DEBUG("require mode change");
1222 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1238 /* change processor mode (mask T bit) */
1239 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1240 tmp_cpsr |= armv4_5_number_to_mode(i);
1242 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1243 current_mode = armv4_5_number_to_mode(i);
1246 for (j = 0; j <= 14; j++)
1248 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1249 reg_arch_info = reg->arch_info;
1252 if (reg->dirty == 1)
1254 regs[j] = buf_get_u32(reg->value, 0, 32);
1259 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1265 arm7_9->write_core_regs(target, mask, regs);
1268 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1269 reg_arch_info = reg->arch_info;
1270 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1272 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1273 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1278 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1280 /* restore processor mode (mask T bit) */
1283 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1284 tmp_cpsr |= armv4_5_number_to_mode(i);
1286 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1287 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1289 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1291 /* CPSR has been changed, full restore necessary (mask T bit) */
1292 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1293 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1294 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1295 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1299 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1300 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1301 armv4_5->core_cache->reg_list[15].dirty = 0;
1303 if (arm7_9->post_restore_context)
1304 arm7_9->post_restore_context(target);
1309 int arm7_9_restart_core(struct target_s *target)
1311 armv4_5_common_t *armv4_5 = target->arch_info;
1312 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1313 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1315 /* set RESTART instruction */
1316 jtag_add_end_state(TAP_RTI);
1317 arm_jtag_set_instr(jtag_info, 0x4, NULL);
1319 jtag_add_runtest(1, TAP_RTI);
1320 if ((jtag_execute_queue()) != ERROR_OK)
1328 void arm7_9_enable_watchpoints(struct target_s *target)
1330 watchpoint_t *watchpoint = target->watchpoints;
1334 if (watchpoint->set == 0)
1335 arm7_9_set_watchpoint(target, watchpoint);
1336 watchpoint = watchpoint->next;
1340 void arm7_9_enable_breakpoints(struct target_s *target)
1342 breakpoint_t *breakpoint = target->breakpoints;
1344 /* set any pending breakpoints */
1347 if (breakpoint->set == 0)
1348 arm7_9_set_breakpoint(target, breakpoint);
1349 breakpoint = breakpoint->next;
1353 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1355 breakpoint_t *breakpoint = target->breakpoints;
1356 watchpoint_t *watchpoint = target->watchpoints;
1358 /* set any pending breakpoints */
1361 if (breakpoint->set != 0)
1362 arm7_9_unset_breakpoint(target, breakpoint);
1363 breakpoint = breakpoint->next;
1368 if (watchpoint->set != 0)
1369 arm7_9_unset_watchpoint(target, watchpoint);
1370 watchpoint = watchpoint->next;
1374 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1376 armv4_5_common_t *armv4_5 = target->arch_info;
1377 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1378 breakpoint_t *breakpoint = target->breakpoints;
1379 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1383 if (target->state != TARGET_HALTED)
1385 WARNING("target not halted");
1386 return ERROR_TARGET_NOT_HALTED;
1389 if (!debug_execution)
1391 target_free_all_working_areas(target);
1394 /* current = 1: continue on current pc, otherwise continue at <address> */
1396 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1398 /* the front-end may request us not to handle breakpoints */
1399 if (handle_breakpoints)
1401 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1403 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1404 arm7_9_unset_breakpoint(target, breakpoint);
1406 DEBUG("enable single-step");
1407 arm7_9->enable_single_step(target);
1409 target->debug_reason = DBG_REASON_SINGLESTEP;
1411 arm7_9_restore_context(target);
1413 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1414 arm7_9->branch_resume(target);
1415 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1417 arm7_9->branch_resume_thumb(target);
1421 ERROR("unhandled core state");
1425 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1426 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1427 arm7_9_execute_sys_speed(target);
1429 DEBUG("disable single-step");
1430 arm7_9->disable_single_step(target);
1432 arm7_9_debug_entry(target);
1433 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1435 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1436 arm7_9_set_breakpoint(target, breakpoint);
1440 /* enable any pending breakpoints and watchpoints */
1441 arm7_9_enable_breakpoints(target);
1442 arm7_9_enable_watchpoints(target);
1444 arm7_9_restore_context(target);
1446 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1448 arm7_9->branch_resume(target);
1450 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1452 arm7_9->branch_resume_thumb(target);
1456 ERROR("unhandled core state");
1460 /* deassert DBGACK and INTDIS */
1461 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1462 /* INTDIS only when we really resume, not during debug execution */
1463 if (!debug_execution)
1464 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1465 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1467 arm7_9_restart_core(target);
1469 target->debug_reason = DBG_REASON_NOTHALTED;
1471 if (!debug_execution)
1473 /* registers are now invalid */
1474 armv4_5_invalidate_core_regs(target);
1475 target->state = TARGET_RUNNING;
1476 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1480 target->state = TARGET_DEBUG_RUNNING;
1481 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1484 DEBUG("target resumed");
1489 void arm7_9_enable_eice_step(target_t *target)
1491 armv4_5_common_t *armv4_5 = target->arch_info;
1492 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1494 /* setup an inverse breakpoint on the current PC
1495 * - comparator 1 matches the current address
1496 * - rangeout from comparator 1 is connected to comparator 0 rangein
1497 * - comparator 0 matches any address, as long as rangein is low */
1498 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1499 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1500 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1501 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1502 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1503 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1504 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1505 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1506 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1509 void arm7_9_disable_eice_step(target_t *target)
1511 armv4_5_common_t *armv4_5 = target->arch_info;
1512 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1514 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1515 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1516 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1517 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1518 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1519 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1520 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1521 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1522 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1525 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1527 armv4_5_common_t *armv4_5 = target->arch_info;
1528 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1529 breakpoint_t *breakpoint = NULL;
1531 if (target->state != TARGET_HALTED)
1533 WARNING("target not halted");
1534 return ERROR_TARGET_NOT_HALTED;
1537 /* current = 1: continue on current pc, otherwise continue at <address> */
1539 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1541 /* the front-end may request us not to handle breakpoints */
1542 if (handle_breakpoints)
1543 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1544 arm7_9_unset_breakpoint(target, breakpoint);
1546 target->debug_reason = DBG_REASON_SINGLESTEP;
1548 arm7_9_restore_context(target);
1550 arm7_9->enable_single_step(target);
1552 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1554 arm7_9->branch_resume(target);
1556 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1558 arm7_9->branch_resume_thumb(target);
1562 ERROR("unhandled core state");
1566 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1568 arm7_9_execute_sys_speed(target);
1569 arm7_9->disable_single_step(target);
1571 /* registers are now invalid */
1572 armv4_5_invalidate_core_regs(target);
1574 arm7_9_debug_entry(target);
1576 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1579 arm7_9_set_breakpoint(target, breakpoint);
1581 DEBUG("target stepped");
1587 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1592 armv4_5_common_t *armv4_5 = target->arch_info;
1593 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1594 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1596 if ((num < 0) || (num > 16))
1597 return ERROR_INVALID_ARGUMENTS;
1599 if ((mode != ARMV4_5_MODE_ANY)
1600 && (mode != armv4_5->core_mode)
1601 && (reg_mode != ARMV4_5_MODE_ANY))
1605 /* change processor mode (mask T bit) */
1606 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1609 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1612 if ((num >= 0) && (num <= 15))
1614 /* read a normal core register */
1615 reg_p[num] = &value;
1617 arm7_9->read_core_regs(target, 1 << num, reg_p);
1621 /* read a program status register
1622 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1624 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1625 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1627 arm7_9->read_xpsr(target, &value, spsr);
1630 if ((retval = jtag_execute_queue()) != ERROR_OK)
1632 ERROR("JTAG failure");
1636 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1637 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1638 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1640 if ((mode != ARMV4_5_MODE_ANY)
1641 && (mode != armv4_5->core_mode)
1642 && (reg_mode != ARMV4_5_MODE_ANY)) {
1643 /* restore processor mode (mask T bit) */
1644 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1651 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1655 armv4_5_common_t *armv4_5 = target->arch_info;
1656 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1657 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1659 if ((num < 0) || (num > 16))
1660 return ERROR_INVALID_ARGUMENTS;
1662 if ((mode != ARMV4_5_MODE_ANY)
1663 && (mode != armv4_5->core_mode)
1664 && (reg_mode != ARMV4_5_MODE_ANY)) {
1667 /* change processor mode (mask T bit) */
1668 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1671 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1674 if ((num >= 0) && (num <= 15))
1676 /* write a normal core register */
1679 arm7_9->write_core_regs(target, 1 << num, reg);
1683 /* write a program status register
1684 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1686 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1687 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1689 /* if we're writing the CPSR, mask the T bit */
1693 arm7_9->write_xpsr(target, value, spsr);
1696 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1697 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1699 if ((mode != ARMV4_5_MODE_ANY)
1700 && (mode != armv4_5->core_mode)
1701 && (reg_mode != ARMV4_5_MODE_ANY)) {
1702 /* restore processor mode (mask T bit) */
1703 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1706 if ((retval = jtag_execute_queue()) != ERROR_OK)
1708 ERROR("JTAG failure");
1716 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1718 armv4_5_common_t *armv4_5 = target->arch_info;
1719 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1722 int num_accesses = 0;
1723 int thisrun_accesses;
1729 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1731 if (target->state != TARGET_HALTED)
1733 WARNING("target not halted");
1734 return ERROR_TARGET_NOT_HALTED;
1737 /* sanitize arguments */
1738 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1739 return ERROR_INVALID_ARGUMENTS;
1741 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1742 return ERROR_TARGET_UNALIGNED_ACCESS;
1744 /* load the base register with the address of the first word */
1746 arm7_9->write_core_regs(target, 0x1, reg);
1751 while (num_accesses < count)
1754 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1755 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1757 if (last_reg <= thisrun_accesses)
1758 last_reg = thisrun_accesses;
1760 arm7_9->load_word_regs(target, reg_list);
1762 /* fast memory reads are only safe when the target is running
1763 * from a sufficiently high clock (32 kHz is usually too slow)
1765 if (arm7_9->fast_memory_access)
1766 arm7_9_execute_fast_sys_speed(target);
1768 arm7_9_execute_sys_speed(target);
1770 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1772 /* advance buffer, count number of accesses */
1773 buffer += thisrun_accesses * 4;
1774 num_accesses += thisrun_accesses;
1778 while (num_accesses < count)
1781 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1782 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1784 for (i = 1; i <= thisrun_accesses; i++)
1788 arm7_9->load_hword_reg(target, i);
1789 /* fast memory reads are only safe when the target is running
1790 * from a sufficiently high clock (32 kHz is usually too slow)
1792 if (arm7_9->fast_memory_access)
1793 arm7_9_execute_fast_sys_speed(target);
1795 arm7_9_execute_sys_speed(target);
1798 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1800 /* advance buffer, count number of accesses */
1801 buffer += thisrun_accesses * 2;
1802 num_accesses += thisrun_accesses;
1806 while (num_accesses < count)
1809 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1810 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1812 for (i = 1; i <= thisrun_accesses; i++)
1816 arm7_9->load_byte_reg(target, i);
1817 /* fast memory reads are only safe when the target is running
1818 * from a sufficiently high clock (32 kHz is usually too slow)
1820 if (arm7_9->fast_memory_access)
1821 arm7_9_execute_fast_sys_speed(target);
1823 arm7_9_execute_sys_speed(target);
1826 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1828 /* advance buffer, count number of accesses */
1829 buffer += thisrun_accesses * 1;
1830 num_accesses += thisrun_accesses;
1834 ERROR("BUG: we shouldn't get here");
1839 for (i=0; i<=last_reg; i++)
1840 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1842 arm7_9->read_xpsr(target, &cpsr, 0);
1843 if ((retval = jtag_execute_queue()) != ERROR_OK)
1845 ERROR("JTAG error while reading cpsr");
1849 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1851 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1853 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1855 return ERROR_TARGET_DATA_ABORT;
1861 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1863 armv4_5_common_t *armv4_5 = target->arch_info;
1864 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1865 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1868 int num_accesses = 0;
1869 int thisrun_accesses;
1875 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1877 if (target->state != TARGET_HALTED)
1879 WARNING("target not halted");
1880 return ERROR_TARGET_NOT_HALTED;
1883 /* sanitize arguments */
1884 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1885 return ERROR_INVALID_ARGUMENTS;
1887 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1888 return ERROR_TARGET_UNALIGNED_ACCESS;
1890 /* load the base register with the address of the first word */
1892 arm7_9->write_core_regs(target, 0x1, reg);
1894 /* Clear DBGACK, to make sure memory fetches work as expected */
1895 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1896 embeddedice_store_reg(dbg_ctrl);
1901 while (num_accesses < count)
1904 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1905 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1907 for (i = 1; i <= thisrun_accesses; i++)
1911 reg[i] = target_buffer_get_u32(target, buffer);
1915 arm7_9->write_core_regs(target, reg_list, reg);
1917 arm7_9->store_word_regs(target, reg_list);
1919 /* fast memory writes are only safe when the target is running
1920 * from a sufficiently high clock (32 kHz is usually too slow)
1922 if (arm7_9->fast_memory_access)
1923 arm7_9_execute_fast_sys_speed(target);
1925 arm7_9_execute_sys_speed(target);
1927 num_accesses += thisrun_accesses;
1931 while (num_accesses < count)
1934 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1935 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1937 for (i = 1; i <= thisrun_accesses; i++)
1941 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1945 arm7_9->write_core_regs(target, reg_list, reg);
1947 for (i = 1; i <= thisrun_accesses; i++)
1949 arm7_9->store_hword_reg(target, i);
1951 /* fast memory writes are only safe when the target is running
1952 * from a sufficiently high clock (32 kHz is usually too slow)
1954 if (arm7_9->fast_memory_access)
1955 arm7_9_execute_fast_sys_speed(target);
1957 arm7_9_execute_sys_speed(target);
1960 num_accesses += thisrun_accesses;
1964 while (num_accesses < count)
1967 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1968 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1970 for (i = 1; i <= thisrun_accesses; i++)
1974 reg[i] = *buffer++ & 0xff;
1977 arm7_9->write_core_regs(target, reg_list, reg);
1979 for (i = 1; i <= thisrun_accesses; i++)
1981 arm7_9->store_byte_reg(target, i);
1982 /* fast memory writes are only safe when the target is running
1983 * from a sufficiently high clock (32 kHz is usually too slow)
1985 if (arm7_9->fast_memory_access)
1986 arm7_9_execute_fast_sys_speed(target);
1988 arm7_9_execute_sys_speed(target);
1991 num_accesses += thisrun_accesses;
1995 ERROR("BUG: we shouldn't get here");
2001 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
2002 embeddedice_store_reg(dbg_ctrl);
2004 for (i=0; i<=last_reg; i++)
2005 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
2007 arm7_9->read_xpsr(target, &cpsr, 0);
2008 if ((retval = jtag_execute_queue()) != ERROR_OK)
2010 ERROR("JTAG error while reading cpsr");
2014 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
2016 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
2018 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
2020 return ERROR_TARGET_DATA_ABORT;
2026 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
2028 armv4_5_common_t *armv4_5 = target->arch_info;
2029 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
2030 enum armv4_5_state core_state = armv4_5->core_state;
2031 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
2032 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
2033 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
2038 /* MRC TST BNE MRC STR B */
2039 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
2042 if (!arm7_9->dcc_downloads)
2043 return target->type->write_memory(target, address, 4, count, buffer);
2045 /* regrab previously allocated working_area, or allocate a new one */
2046 if (!arm7_9->dcc_working_area)
2048 u8 dcc_code_buf[6 * 4];
2050 /* make sure we have a working area */
2051 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
2053 INFO("no working area available, falling back to memory writes");
2054 return target->type->write_memory(target, address, 4, count, buffer);
2057 /* copy target instructions to target endianness */
2058 for (i = 0; i < 6; i++)
2060 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2063 /* write DCC code to working area */
2064 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2067 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2068 armv4_5->core_cache->reg_list[0].valid = 1;
2069 armv4_5->core_cache->reg_list[0].dirty = 1;
2070 armv4_5->core_state = ARMV4_5_STATE_ARM;
2072 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2074 for (i = 0; i < count; i++)
2076 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2080 target->type->halt(target);
2082 while (target->state != TARGET_HALTED)
2083 target->type->poll(target);
2085 /* restore target state */
2086 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2087 armv4_5->core_cache->reg_list[0].valid = 1;
2088 armv4_5->core_cache->reg_list[0].dirty = 1;
2089 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2090 armv4_5->core_cache->reg_list[1].valid = 1;
2091 armv4_5->core_cache->reg_list[1].dirty = 1;
2092 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2093 armv4_5->core_cache->reg_list[15].valid = 1;
2094 armv4_5->core_cache->reg_list[15].dirty = 1;
2095 armv4_5->core_state = core_state;
2100 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2102 command_t *arm7_9_cmd;
2104 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2106 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2107 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2109 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2111 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2112 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2113 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2114 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2115 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2116 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2117 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2118 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2119 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2120 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2122 armv4_5_register_commands(cmd_ctx);
2124 etm_register_commands(cmd_ctx);
2129 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2134 target_t *target = get_current_target(cmd_ctx);
2135 armv4_5_common_t *armv4_5;
2136 arm7_9_common_t *arm7_9;
2138 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2140 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2144 if (target->state != TARGET_HALTED)
2146 command_print(cmd_ctx, "can't write registers while running");
2152 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2156 value = strtoul(args[0], NULL, 0);
2157 spsr = strtol(args[1], NULL, 0);
2159 /* if we're writing the CPSR, mask the T bit */
2163 arm7_9->write_xpsr(target, value, spsr);
2164 if ((retval = jtag_execute_queue()) != ERROR_OK)
2166 ERROR("JTAG error while writing to xpsr");
2173 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2179 target_t *target = get_current_target(cmd_ctx);
2180 armv4_5_common_t *armv4_5;
2181 arm7_9_common_t *arm7_9;
2183 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2185 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2189 if (target->state != TARGET_HALTED)
2191 command_print(cmd_ctx, "can't write registers while running");
2197 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2201 value = strtoul(args[0], NULL, 0);
2202 rotate = strtol(args[1], NULL, 0);
2203 spsr = strtol(args[2], NULL, 0);
2205 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2206 if ((retval = jtag_execute_queue()) != ERROR_OK)
2208 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2215 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2220 target_t *target = get_current_target(cmd_ctx);
2221 armv4_5_common_t *armv4_5;
2222 arm7_9_common_t *arm7_9;
2224 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2226 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2230 if (target->state != TARGET_HALTED)
2232 command_print(cmd_ctx, "can't write registers while running");
2238 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2242 num = strtol(args[0], NULL, 0);
2243 mode = strtoul(args[1], NULL, 0);
2244 value = strtoul(args[2], NULL, 0);
2246 arm7_9_write_core_reg(target, num, mode, value);
2251 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2253 target_t *target = get_current_target(cmd_ctx);
2254 armv4_5_common_t *armv4_5;
2255 arm7_9_common_t *arm7_9;
2257 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2259 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2265 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2269 if (strcmp("enable", args[0]) == 0)
2271 if (arm7_9->sw_bkpts_use_wp)
2273 arm7_9_enable_sw_bkpts(target);
2277 arm7_9->sw_bkpts_enabled = 1;
2280 else if (strcmp("disable", args[0]) == 0)
2282 if (arm7_9->sw_bkpts_use_wp)
2284 arm7_9_disable_sw_bkpts(target);
2288 arm7_9->sw_bkpts_enabled = 0;
2293 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2296 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2301 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2303 target_t *target = get_current_target(cmd_ctx);
2304 armv4_5_common_t *armv4_5;
2305 arm7_9_common_t *arm7_9;
2307 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2309 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2313 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2315 arm7_9->force_hw_bkpts = 1;
2316 if (arm7_9->sw_bkpts_use_wp)
2318 arm7_9_disable_sw_bkpts(target);
2321 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2323 arm7_9->force_hw_bkpts = 0;
2327 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2330 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2335 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2337 target_t *target = get_current_target(cmd_ctx);
2338 armv4_5_common_t *armv4_5;
2339 arm7_9_common_t *arm7_9;
2341 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2343 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2349 if (strcmp("enable", args[0]) == 0)
2351 arm7_9->use_dbgrq = 1;
2353 else if (strcmp("disable", args[0]) == 0)
2355 arm7_9->use_dbgrq = 0;
2359 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2363 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2368 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2370 target_t *target = get_current_target(cmd_ctx);
2371 armv4_5_common_t *armv4_5;
2372 arm7_9_common_t *arm7_9;
2374 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2376 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2382 if (strcmp("enable", args[0]) == 0)
2384 arm7_9->fast_memory_access = 1;
2386 else if (strcmp("disable", args[0]) == 0)
2388 arm7_9->fast_memory_access = 0;
2392 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2396 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2401 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2403 target_t *target = get_current_target(cmd_ctx);
2404 armv4_5_common_t *armv4_5;
2405 arm7_9_common_t *arm7_9;
2407 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2409 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2415 if (strcmp("enable", args[0]) == 0)
2417 arm7_9->dcc_downloads = 1;
2419 else if (strcmp("disable", args[0]) == 0)
2421 arm7_9->dcc_downloads = 0;
2425 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2429 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2434 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2436 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2438 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2440 arm_jtag_setup_connection(&arm7_9->jtag_info);
2441 arm7_9->wp_available = 2;
2442 arm7_9->wp0_used = 0;
2443 arm7_9->wp1_used = 0;
2444 arm7_9->force_hw_bkpts = 0;
2445 arm7_9->use_dbgrq = 0;
2447 arm7_9->etm_ctx = NULL;
2448 arm7_9->has_single_step = 0;
2449 arm7_9->has_monitor_mode = 0;
2450 arm7_9->has_vector_catch = 0;
2452 arm7_9->reinit_embeddedice = 0;
2454 arm7_9->debug_entry_from_reset = 0;
2456 arm7_9->dcc_working_area = NULL;
2458 arm7_9->fast_memory_access = 0;
2459 arm7_9->dcc_downloads = 0;
2461 jtag_register_event_callback(arm7_9_jtag_callback, target);
2463 armv4_5->arch_info = arm7_9;
2464 armv4_5->read_core_reg = arm7_9_read_core_reg;
2465 armv4_5->write_core_reg = arm7_9_write_core_reg;
2466 armv4_5->full_context = arm7_9_full_context;
2468 armv4_5_init_arch_info(target, armv4_5);