1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
39 #include <sys/types.h>
44 int arm7_9_debug_entry(target_t *target);
45 int arm7_9_enable_sw_bkpts(struct target_s *target);
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int arm7_9_reinit_embeddedice(target_t *target)
60 armv4_5_common_t *armv4_5 = target->arch_info;
61 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
63 breakpoint_t *breakpoint = target->breakpoints;
65 arm7_9->wp_available = 2;
69 /* mark all hardware breakpoints as unset */
72 if (breakpoint->type == BKPT_HARD)
76 breakpoint = breakpoint->next;
79 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
81 arm7_9->sw_bkpts_enabled = 0;
82 arm7_9_enable_sw_bkpts(target);
85 arm7_9->reinit_embeddedice = 0;
90 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
92 target_t *target = priv;
93 armv4_5_common_t *armv4_5 = target->arch_info;
94 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
96 /* a test-logic reset occured
97 * the EmbeddedICE registers have been reset
98 * hardware breakpoints have been cleared
100 if (event == JTAG_TRST_ASSERTED)
102 arm7_9->reinit_embeddedice = 1;
108 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
110 armv4_5_common_t *armv4_5 = target->arch_info;
111 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
113 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
118 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
123 *armv4_5_p = armv4_5;
129 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
131 armv4_5_common_t *armv4_5 = target->arch_info;
132 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
134 if (target->state != TARGET_HALTED)
136 WARNING("target not halted");
137 return ERROR_TARGET_NOT_HALTED;
140 if (arm7_9->force_hw_bkpts)
141 breakpoint->type = BKPT_HARD;
145 WARNING("breakpoint already set");
149 if (breakpoint->type == BKPT_HARD)
151 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
152 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
153 if (!arm7_9->wp0_used)
155 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
161 jtag_execute_queue();
162 arm7_9->wp0_used = 1;
165 else if (!arm7_9->wp1_used)
167 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
173 jtag_execute_queue();
174 arm7_9->wp1_used = 1;
179 ERROR("BUG: no hardware comparator available");
183 else if (breakpoint->type == BKPT_SOFT)
185 if (breakpoint->length == 4)
187 /* keep the original instruction in target endianness */
188 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
189 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
190 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
194 /* keep the original instruction in target endianness */
195 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
196 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
197 target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
206 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
208 armv4_5_common_t *armv4_5 = target->arch_info;
209 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
211 if (target->state != TARGET_HALTED)
213 WARNING("target not halted");
214 return ERROR_TARGET_NOT_HALTED;
217 if (!breakpoint->set)
219 WARNING("breakpoint not set");
223 if (breakpoint->type == BKPT_HARD)
225 if (breakpoint->set == 1)
227 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
228 jtag_execute_queue();
229 arm7_9->wp0_used = 0;
231 else if (breakpoint->set == 2)
233 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
234 jtag_execute_queue();
235 arm7_9->wp1_used = 0;
241 /* restore original instruction (kept in target endianness) */
242 if (breakpoint->length == 4)
244 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
248 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
256 int arm7_9_add_breakpoint(struct target_s *target, u32 address, u32 length, enum breakpoint_type type)
258 armv4_5_common_t *armv4_5 = target->arch_info;
259 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
261 if (target->state != TARGET_HALTED)
263 WARNING("target not halted");
264 return ERROR_TARGET_NOT_HALTED;
267 if (arm7_9->force_hw_bkpts)
272 if ((type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
274 INFO("sw breakpoint requested, but software breakpoints not enabled");
275 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
278 if ((type == BKPT_HARD) && (arm7_9->wp_available < 1))
280 INFO("no watchpoint unit available for hardware breakpoint");
281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
284 if ((length != 2) && (length != 4))
286 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
290 if (type == BKPT_HARD)
291 arm7_9->wp_available--;
296 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
298 armv4_5_common_t *armv4_5 = target->arch_info;
299 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
301 if (target->state != TARGET_HALTED)
303 WARNING("target not halted");
304 return ERROR_TARGET_NOT_HALTED;
309 arm7_9_unset_breakpoint(target, breakpoint);
312 if (breakpoint->type == BKPT_HARD)
313 arm7_9->wp_available++;
318 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
320 armv4_5_common_t *armv4_5 = target->arch_info;
321 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
325 mask = watchpoint->length - 1;
327 if (target->state != TARGET_HALTED)
329 WARNING("target not halted");
330 return ERROR_TARGET_NOT_HALTED;
333 if (watchpoint->rw == WPT_ACCESS)
338 if (!arm7_9->wp0_used)
340 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
341 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
342 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
343 if( watchpoint->mask != 0xffffffffu )
344 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
345 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
346 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
348 jtag_execute_queue();
350 arm7_9->wp0_used = 2;
352 else if (!arm7_9->wp1_used)
354 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
355 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
357 if( watchpoint->mask != 0xffffffffu )
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
359 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
360 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
362 jtag_execute_queue();
364 arm7_9->wp1_used = 2;
368 ERROR("BUG: no hardware comparator available");
375 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
377 armv4_5_common_t *armv4_5 = target->arch_info;
378 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
380 if (target->state != TARGET_HALTED)
382 WARNING("target not halted");
383 return ERROR_TARGET_NOT_HALTED;
386 if (!watchpoint->set)
388 WARNING("breakpoint not set");
392 if (watchpoint->set == 1)
394 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
395 jtag_execute_queue();
396 arm7_9->wp0_used = 0;
398 else if (watchpoint->set == 2)
400 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
401 jtag_execute_queue();
402 arm7_9->wp1_used = 0;
409 int arm7_9_add_watchpoint(struct target_s *target, u32 address, u32 length, enum watchpoint_rw rw)
411 armv4_5_common_t *armv4_5 = target->arch_info;
412 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
414 if (target->state != TARGET_HALTED)
416 WARNING("target not halted");
417 return ERROR_TARGET_NOT_HALTED;
420 if (arm7_9->wp_available < 1)
422 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
425 if ((length != 1) && (length != 2) && (length != 4))
427 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
430 arm7_9->wp_available--;
435 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
437 armv4_5_common_t *armv4_5 = target->arch_info;
438 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440 if (target->state != TARGET_HALTED)
442 WARNING("target not halted");
443 return ERROR_TARGET_NOT_HALTED;
448 arm7_9_unset_watchpoint(target, watchpoint);
451 arm7_9->wp_available++;
456 int arm7_9_enable_sw_bkpts(struct target_s *target)
458 armv4_5_common_t *armv4_5 = target->arch_info;
459 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
462 if (arm7_9->sw_bkpts_enabled)
465 if (arm7_9->wp_available < 1)
467 WARNING("can't enable sw breakpoints with no watchpoint unit available");
468 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
470 arm7_9->wp_available--;
472 if (!arm7_9->wp0_used)
474 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
475 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
476 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
477 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
478 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
479 arm7_9->sw_bkpts_enabled = 1;
480 arm7_9->wp0_used = 3;
482 else if (!arm7_9->wp1_used)
484 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
485 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
486 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
487 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
488 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
489 arm7_9->sw_bkpts_enabled = 2;
490 arm7_9->wp1_used = 3;
494 ERROR("BUG: both watchpoints used, but wp_available >= 1");
498 if ((retval = jtag_execute_queue()) != ERROR_OK)
500 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
507 int arm7_9_disable_sw_bkpts(struct target_s *target)
509 armv4_5_common_t *armv4_5 = target->arch_info;
510 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
512 if (!arm7_9->sw_bkpts_enabled)
515 if (arm7_9->sw_bkpts_enabled == 1)
517 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
518 arm7_9->sw_bkpts_enabled = 0;
519 arm7_9->wp0_used = 0;
520 arm7_9->wp_available++;
522 else if (arm7_9->sw_bkpts_enabled == 2)
524 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
525 arm7_9->sw_bkpts_enabled = 0;
526 arm7_9->wp1_used = 0;
527 arm7_9->wp_available++;
533 int arm7_9_execute_sys_speed(struct target_s *target)
538 armv4_5_common_t *armv4_5 = target->arch_info;
539 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
540 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
541 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
543 /* set RESTART instruction */
544 jtag_add_end_state(TAP_RTI);
545 arm_jtag_set_instr(jtag_info, 0x4);
547 for (timeout=0; timeout<50; timeout++)
549 /* read debug status register */
550 embeddedice_read_reg(dbg_stat);
551 if ((retval = jtag_execute_queue()) != ERROR_OK)
553 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
554 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
560 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
561 return ERROR_TARGET_TIMEOUT;
567 int arm7_9_execute_fast_sys_speed(struct target_s *target)
569 u8 check_value[4], check_mask[4];
571 armv4_5_common_t *armv4_5 = target->arch_info;
572 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
573 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
574 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
576 /* set RESTART instruction */
577 jtag_add_end_state(TAP_RTI);
578 arm_jtag_set_instr(jtag_info, 0x4);
580 /* check for DBGACK and SYSCOMP set (others don't care) */
581 buf_set_u32(check_value, 0, 32, 0x9);
582 buf_set_u32(check_mask, 0, 32, 0x9);
584 /* read debug status register */
585 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
590 enum target_state arm7_9_poll(target_t *target)
593 armv4_5_common_t *armv4_5 = target->arch_info;
594 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
595 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
597 if (arm7_9->reinit_embeddedice)
599 arm7_9_reinit_embeddedice(target);
602 /* read debug status register */
603 embeddedice_read_reg(dbg_stat);
604 if ((retval = jtag_execute_queue()) != ERROR_OK)
608 case ERROR_JTAG_QUEUE_FAILED:
609 ERROR("JTAG queue failed while reading EmbeddedICE status register");
617 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
619 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
620 if ((target->state == TARGET_UNKNOWN))
622 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
623 target->state = TARGET_RUNNING;
625 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
627 target->state = TARGET_HALTED;
628 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
631 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
633 if (target->state == TARGET_DEBUG_RUNNING)
635 target->state = TARGET_HALTED;
636 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
639 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
644 if (target->state != TARGET_DEBUG_RUNNING)
645 target->state = TARGET_RUNNING;
648 return target->state;
651 int arm7_9_assert_reset(target_t *target)
655 DEBUG("target->state: %s", target_state_strings[target->state]);
657 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
659 /* assert SRST and TRST */
660 /* system would get ouf sync if we didn't reset test-logic, too */
661 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
663 if (retval == ERROR_JTAG_RESET_CANT_SRST)
665 WARNING("can't assert srst");
670 ERROR("unknown error");
674 jtag_add_sleep(5000);
675 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
677 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
679 WARNING("srst resets test logic, too");
680 retval = jtag_add_reset(1, 1);
686 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
688 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
690 WARNING("srst resets test logic, too");
691 retval = jtag_add_reset(1, 1);
694 if (retval == ERROR_JTAG_RESET_CANT_SRST)
696 WARNING("can't assert srst");
699 else if (retval != ERROR_OK)
701 ERROR("unknown error");
707 target->state = TARGET_RESET;
708 jtag_add_sleep(50000);
710 armv4_5_invalidate_core_regs(target);
716 int arm7_9_deassert_reset(target_t *target)
718 DEBUG("target->state: %s", target_state_strings[target->state]);
720 /* deassert reset lines */
721 jtag_add_reset(0, 0);
727 int arm7_9_soft_reset_halt(struct target_s *target)
729 armv4_5_common_t *armv4_5 = target->arch_info;
730 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
731 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
734 if (target->state == TARGET_RUNNING)
736 target->type->halt(target);
739 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
741 embeddedice_read_reg(dbg_stat);
742 jtag_execute_queue();
744 target->state = TARGET_HALTED;
746 /* all register content is now invalid */
747 armv4_5_invalidate_core_regs(target);
749 /* SVC, ARM state, IRQ and FIQ disabled */
750 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
751 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
752 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
754 /* start fetching from 0x0 */
755 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
756 armv4_5->core_cache->reg_list[15].dirty = 1;
757 armv4_5->core_cache->reg_list[15].valid = 1;
759 armv4_5->core_mode = ARMV4_5_MODE_SVC;
760 armv4_5->core_state = ARMV4_5_STATE_ARM;
762 /* reset registers */
763 for (i = 0; i <= 14; i++)
765 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
766 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
767 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
770 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
775 int arm7_9_halt(target_t *target)
777 armv4_5_common_t *armv4_5 = target->arch_info;
778 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
779 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
781 DEBUG("target->state: %s", target_state_strings[target->state]);
783 if (target->state == TARGET_HALTED)
785 WARNING("target was already halted");
786 return ERROR_TARGET_ALREADY_HALTED;
789 if (target->state == TARGET_UNKNOWN)
791 WARNING("target was in unknown state when halt was requested");
794 if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
796 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
797 return ERROR_TARGET_FAILURE;
800 if (arm7_9->use_dbgrq)
802 /* program EmbeddedICE Debug Control Register to assert DBGRQ
804 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
805 embeddedice_store_reg(dbg_ctrl);
809 /* program watchpoint unit to match on any address
811 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
812 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
813 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
814 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
817 target->debug_reason = DBG_REASON_DBGRQ;
822 int arm7_9_clear_halt(target_t *target)
824 armv4_5_common_t *armv4_5 = target->arch_info;
825 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
826 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
828 if (arm7_9->use_dbgrq)
830 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
832 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
833 embeddedice_store_reg(dbg_ctrl);
837 /* restore registers if watchpoint unit 0 was in use
839 if (arm7_9->wp0_used)
841 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
842 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
843 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
845 /* control value always has to be restored, as it was either disabled,
846 * or enabled with possibly different bits
848 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
854 int arm7_9_debug_entry(target_t *target)
859 u32 r0_thumb, pc_thumb;
862 /* get pointers to arch-specific information */
863 armv4_5_common_t *armv4_5 = target->arch_info;
864 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
865 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
866 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
868 #ifdef _DEBUG_ARM7_9_
872 if (arm7_9->pre_debug_entry)
873 arm7_9->pre_debug_entry(target);
875 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
876 * ensure that DBGRQ is cleared
878 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
879 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
880 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
881 embeddedice_store_reg(dbg_ctrl);
883 arm7_9_clear_halt(target);
885 if ((retval = jtag_execute_queue()) != ERROR_OK)
889 case ERROR_JTAG_QUEUE_FAILED:
890 ERROR("JTAG queue failed while writing EmbeddedICE control register");
898 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
902 if (target->state != TARGET_HALTED)
904 WARNING("target not halted");
905 return ERROR_TARGET_NOT_HALTED;
908 /* if the target is in Thumb state, change to ARM state */
909 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
911 DEBUG("target entered debug from Thumb state");
912 /* Entered debug from Thumb mode */
913 armv4_5->core_state = ARMV4_5_STATE_THUMB;
914 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
915 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
919 DEBUG("target entered debug from ARM state");
920 /* Entered debug from ARM mode */
921 armv4_5->core_state = ARMV4_5_STATE_ARM;
924 for (i = 0; i < 16; i++)
925 context_p[i] = &context[i];
926 /* save core registers (r0 - r15 of current core mode) */
927 arm7_9->read_core_regs(target, 0xffff, context_p);
929 arm7_9->read_xpsr(target, &cpsr, 0);
931 if ((retval = jtag_execute_queue()) != ERROR_OK)
934 /* if the core has been executing in Thumb state, set the T bit */
935 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
938 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
939 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
940 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
942 armv4_5->core_mode = cpsr & 0x1f;
944 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
946 target->state = TARGET_UNKNOWN;
947 ERROR("cpsr contains invalid mode value - communication failure");
948 return ERROR_TARGET_FAILURE;
951 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
953 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
955 DEBUG("thumb state, applying fixups");
956 context[0] = r0_thumb;
957 context[15] = pc_thumb;
958 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
960 /* adjust value stored by STM */
961 context[15] -= 3 * 4;
964 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
965 || (target->debug_reason == DBG_REASON_SINGLESTEP)
966 || (target->debug_reason == DBG_REASON_WATCHPOINT)
967 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
968 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
969 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
970 else if (target->debug_reason == DBG_REASON_DBGRQ)
971 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
974 ERROR("unknown debug reason: %i", target->debug_reason);
978 for (i=0; i<=15; i++)
980 DEBUG("r%i: 0x%8.8x", i, context[i]);
981 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
982 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
983 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
986 DEBUG("entered debug state at PC 0x%x", context[15]);
988 /* exceptions other than USR & SYS have a saved program status register */
989 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
992 arm7_9->read_xpsr(target, &spsr, 1);
993 jtag_execute_queue();
994 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
995 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
996 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
999 /* r0 and r15 (pc) have to be restored later */
1000 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1001 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1003 if ((retval = jtag->execute_queue()) != ERROR_OK)
1006 if (arm7_9->post_debug_entry)
1007 arm7_9->post_debug_entry(target);
1012 int arm7_9_full_context(target_t *target)
1016 armv4_5_common_t *armv4_5 = target->arch_info;
1017 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1021 if (target->state != TARGET_HALTED)
1023 WARNING("target not halted");
1024 return ERROR_TARGET_NOT_HALTED;
1027 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1028 * SYS shares registers with User, so we don't touch SYS
1030 for(i = 0; i < 6; i++)
1037 /* check if there are invalid registers in the current mode
1039 for (j = 0; j <= 16; j++)
1041 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1049 /* change processor mode (and mask T bit) */
1050 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1051 tmp_cpsr |= armv4_5_number_to_mode(i);
1053 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1055 for (j = 0; j < 15; j++)
1057 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1059 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1061 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1062 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1066 /* if only the PSR is invalid, mask is all zeroes */
1068 arm7_9->read_core_regs(target, mask, reg_p);
1070 /* check if the PSR has to be read */
1071 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1073 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1074 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1075 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1080 /* restore processor mode (mask T bit) */
1081 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1083 if ((retval = jtag_execute_queue()) != ERROR_OK)
1085 ERROR("JTAG failure");
1091 int arm7_9_restore_context(target_t *target)
1093 armv4_5_common_t *armv4_5 = target->arch_info;
1094 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1096 armv4_5_core_reg_t *reg_arch_info;
1097 enum armv4_5_mode current_mode = armv4_5->core_mode;
1104 if (target->state != TARGET_HALTED)
1106 WARNING("target not halted");
1107 return ERROR_TARGET_NOT_HALTED;
1110 if (arm7_9->pre_restore_context)
1111 arm7_9->pre_restore_context(target);
1113 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1114 * SYS shares registers with User, so we don't touch SYS
1116 for (i = 0; i < 6; i++)
1118 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1121 /* check if there are dirty registers in the current mode
1123 for (j = 0; j <= 16; j++)
1125 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1126 reg_arch_info = reg->arch_info;
1127 if (reg->dirty == 1)
1129 if (reg->valid == 1)
1132 DEBUG("examining dirty reg: %s", reg->name);
1133 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1134 && (reg_arch_info->mode != current_mode)
1135 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1136 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1139 DEBUG("require mode change");
1144 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1160 /* change processor mode (mask T bit) */
1161 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1162 tmp_cpsr |= armv4_5_number_to_mode(i);
1164 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1165 current_mode = armv4_5_number_to_mode(i);
1168 for (j = 0; j <= 14; j++)
1170 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1171 reg_arch_info = reg->arch_info;
1174 if (reg->dirty == 1)
1176 regs[j] = buf_get_u32(reg->value, 0, 32);
1181 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1187 arm7_9->write_core_regs(target, mask, regs);
1190 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1191 reg_arch_info = reg->arch_info;
1192 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1194 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1195 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1200 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1202 /* restore processor mode (mask T bit) */
1205 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1206 tmp_cpsr |= armv4_5_number_to_mode(i);
1208 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1209 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1211 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1213 /* CPSR has been changed, full restore necessary (mask T bit) */
1214 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1215 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1216 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1217 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1221 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1222 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1223 armv4_5->core_cache->reg_list[15].dirty = 0;
1225 if (arm7_9->post_restore_context)
1226 arm7_9->post_restore_context(target);
1231 int arm7_9_restart_core(struct target_s *target)
1233 armv4_5_common_t *armv4_5 = target->arch_info;
1234 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1235 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1237 /* set RESTART instruction */
1238 jtag_add_end_state(TAP_RTI);
1239 arm_jtag_set_instr(jtag_info, 0x4);
1241 jtag_add_runtest(1, TAP_RTI);
1242 if ((jtag_execute_queue()) != ERROR_OK)
1250 void arm7_9_enable_watchpoints(struct target_s *target)
1252 watchpoint_t *watchpoint = target->watchpoints;
1256 if (watchpoint->set == 0)
1257 arm7_9_set_watchpoint(target, watchpoint);
1258 watchpoint = watchpoint->next;
1262 void arm7_9_enable_breakpoints(struct target_s *target)
1264 breakpoint_t *breakpoint = target->breakpoints;
1266 /* set any pending breakpoints */
1269 if (breakpoint->set == 0)
1270 arm7_9_set_breakpoint(target, breakpoint);
1271 breakpoint = breakpoint->next;
1275 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1277 breakpoint_t *breakpoint = target->breakpoints;
1278 watchpoint_t *watchpoint = target->watchpoints;
1280 /* set any pending breakpoints */
1283 if (breakpoint->set != 0)
1284 arm7_9_unset_breakpoint(target, breakpoint);
1285 breakpoint = breakpoint->next;
1290 if (watchpoint->set != 0)
1291 arm7_9_unset_watchpoint(target, watchpoint);
1292 watchpoint = watchpoint->next;
1296 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1298 armv4_5_common_t *armv4_5 = target->arch_info;
1299 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1300 breakpoint_t *breakpoint = target->breakpoints;
1301 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1305 if (target->state != TARGET_HALTED)
1307 WARNING("target not halted");
1308 return ERROR_TARGET_NOT_HALTED;
1311 if (!debug_execution)
1313 target_free_all_working_areas(target);
1316 /* current = 1: continue on current pc, otherwise continue at <address> */
1318 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1320 /* the front-end may request us not to handle breakpoints */
1321 if (handle_breakpoints)
1323 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1325 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1326 arm7_9_unset_breakpoint(target, breakpoint);
1328 DEBUG("enable single-step");
1329 arm7_9->enable_single_step(target);
1331 target->debug_reason = DBG_REASON_SINGLESTEP;
1333 arm7_9_restore_context(target);
1335 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1336 arm7_9->branch_resume(target);
1337 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1339 arm7_9->branch_resume_thumb(target);
1343 ERROR("unhandled core state");
1347 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1348 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1349 arm7_9_execute_sys_speed(target);
1351 DEBUG("disable single-step");
1352 arm7_9->disable_single_step(target);
1354 arm7_9_debug_entry(target);
1355 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1357 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1358 arm7_9_set_breakpoint(target, breakpoint);
1362 /* enable any pending breakpoints and watchpoints */
1363 arm7_9_enable_breakpoints(target);
1364 arm7_9_enable_watchpoints(target);
1366 arm7_9_restore_context(target);
1368 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1370 arm7_9->branch_resume(target);
1372 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1374 arm7_9->branch_resume_thumb(target);
1378 ERROR("unhandled core state");
1382 /* deassert DBGACK and INTDIS */
1383 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1384 /* INTDIS only when we really resume, not during debug execution */
1385 if (!debug_execution)
1386 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1387 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1389 arm7_9_restart_core(target);
1391 target->debug_reason = DBG_REASON_NOTHALTED;
1393 if (!debug_execution)
1395 /* registers are now invalid */
1396 armv4_5_invalidate_core_regs(target);
1397 target->state = TARGET_RUNNING;
1398 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1402 target->state = TARGET_DEBUG_RUNNING;
1403 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1406 DEBUG("target resumed");
1411 void arm7_9_enable_eice_step(target_t *target)
1413 armv4_5_common_t *armv4_5 = target->arch_info;
1414 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1416 /* setup an inverse breakpoint on the current PC
1417 * - comparator 1 matches the current address
1418 * - rangeout from comparator 1 is connected to comparator 0 rangein
1419 * - comparator 0 matches any address, as long as rangein is low */
1420 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1421 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1422 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1423 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1424 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1425 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1426 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1427 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1428 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1431 void arm7_9_disable_eice_step(target_t *target)
1433 armv4_5_common_t *armv4_5 = target->arch_info;
1434 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1436 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1437 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1438 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1439 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1440 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1441 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1442 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1443 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1444 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1447 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1449 armv4_5_common_t *armv4_5 = target->arch_info;
1450 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1451 breakpoint_t *breakpoint = NULL;
1453 if (target->state != TARGET_HALTED)
1455 WARNING("target not halted");
1456 return ERROR_TARGET_NOT_HALTED;
1459 /* current = 1: continue on current pc, otherwise continue at <address> */
1461 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1463 /* the front-end may request us not to handle breakpoints */
1464 if (handle_breakpoints)
1465 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1466 arm7_9_unset_breakpoint(target, breakpoint);
1468 target->debug_reason = DBG_REASON_SINGLESTEP;
1470 arm7_9_restore_context(target);
1472 arm7_9->enable_single_step(target);
1474 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1476 arm7_9->branch_resume(target);
1478 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1480 arm7_9->branch_resume_thumb(target);
1484 ERROR("unhandled core state");
1488 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1490 arm7_9_execute_sys_speed(target);
1491 arm7_9->disable_single_step(target);
1493 /* registers are now invalid */
1494 armv4_5_invalidate_core_regs(target);
1496 arm7_9_debug_entry(target);
1498 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1501 arm7_9_set_breakpoint(target, breakpoint);
1503 DEBUG("target stepped");
1509 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1514 armv4_5_common_t *armv4_5 = target->arch_info;
1515 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1516 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1518 if ((num < 0) || (num > 16))
1519 return ERROR_INVALID_ARGUMENTS;
1521 if ((mode != ARMV4_5_MODE_ANY)
1522 && (mode != armv4_5->core_mode)
1523 && (reg_mode != ARMV4_5_MODE_ANY))
1527 /* change processor mode (mask T bit) */
1528 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1531 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1534 if ((num >= 0) && (num <= 15))
1536 /* read a normal core register */
1537 reg_p[num] = &value;
1539 arm7_9->read_core_regs(target, 1 << num, reg_p);
1543 /* read a program status register
1544 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1546 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1547 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1549 arm7_9->read_xpsr(target, &value, spsr);
1552 if ((retval = jtag_execute_queue()) != ERROR_OK)
1554 ERROR("JTAG failure");
1558 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1559 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1560 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1562 if ((mode != ARMV4_5_MODE_ANY)
1563 && (mode != armv4_5->core_mode)
1564 && (reg_mode != ARMV4_5_MODE_ANY)) {
1565 /* restore processor mode (mask T bit) */
1566 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1573 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1577 armv4_5_common_t *armv4_5 = target->arch_info;
1578 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1579 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1581 if ((num < 0) || (num > 16))
1582 return ERROR_INVALID_ARGUMENTS;
1584 if ((mode != ARMV4_5_MODE_ANY)
1585 && (mode != armv4_5->core_mode)
1586 && (reg_mode != ARMV4_5_MODE_ANY)) {
1589 /* change processor mode (mask T bit) */
1590 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1593 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1596 if ((num >= 0) && (num <= 15))
1598 /* write a normal core register */
1601 arm7_9->write_core_regs(target, 1 << num, reg);
1605 /* write a program status register
1606 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1608 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1609 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1611 /* if we're writing the CPSR, mask the T bit */
1615 arm7_9->write_xpsr(target, value, spsr);
1618 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1619 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1621 if ((mode != ARMV4_5_MODE_ANY)
1622 && (mode != armv4_5->core_mode)
1623 && (reg_mode != ARMV4_5_MODE_ANY)) {
1624 /* restore processor mode (mask T bit) */
1625 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1628 if ((retval = jtag_execute_queue()) != ERROR_OK)
1630 ERROR("JTAG failure");
1638 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1640 armv4_5_common_t *armv4_5 = target->arch_info;
1641 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1644 int num_accesses = 0;
1645 int thisrun_accesses;
1651 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1653 if (target->state != TARGET_HALTED)
1655 WARNING("target not halted");
1656 return ERROR_TARGET_NOT_HALTED;
1659 /* sanitize arguments */
1660 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1661 return ERROR_INVALID_ARGUMENTS;
1663 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1664 return ERROR_TARGET_UNALIGNED_ACCESS;
1666 /* load the base register with the address of the first word */
1668 arm7_9->write_core_regs(target, 0x1, reg);
1673 while (num_accesses < count)
1676 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1677 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1679 if (last_reg <= thisrun_accesses)
1680 last_reg = thisrun_accesses;
1682 arm7_9->load_word_regs(target, reg_list);
1684 /* fast memory reads are only safe when the target is running
1685 * from a sufficiently high clock (32 kHz is usually too slow)
1687 if (arm7_9->fast_memory_access)
1688 arm7_9_execute_fast_sys_speed(target);
1690 arm7_9_execute_sys_speed(target);
1692 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1694 /* advance buffer, count number of accesses */
1695 buffer += thisrun_accesses * 4;
1696 num_accesses += thisrun_accesses;
1700 while (num_accesses < count)
1703 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1704 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1706 for (i = 1; i <= thisrun_accesses; i++)
1710 arm7_9->load_hword_reg(target, i);
1711 /* fast memory reads are only safe when the target is running
1712 * from a sufficiently high clock (32 kHz is usually too slow)
1714 if (arm7_9->fast_memory_access)
1715 arm7_9_execute_fast_sys_speed(target);
1717 arm7_9_execute_sys_speed(target);
1720 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1722 /* advance buffer, count number of accesses */
1723 buffer += thisrun_accesses * 2;
1724 num_accesses += thisrun_accesses;
1728 while (num_accesses < count)
1731 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1732 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1734 for (i = 1; i <= thisrun_accesses; i++)
1738 arm7_9->load_byte_reg(target, i);
1739 /* fast memory reads are only safe when the target is running
1740 * from a sufficiently high clock (32 kHz is usually too slow)
1742 if (arm7_9->fast_memory_access)
1743 arm7_9_execute_fast_sys_speed(target);
1745 arm7_9_execute_sys_speed(target);
1748 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1750 /* advance buffer, count number of accesses */
1751 buffer += thisrun_accesses * 1;
1752 num_accesses += thisrun_accesses;
1756 ERROR("BUG: we shouldn't get here");
1761 for (i=0; i<=last_reg; i++)
1762 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1764 arm7_9->read_xpsr(target, &cpsr, 0);
1765 if ((retval = jtag_execute_queue()) != ERROR_OK)
1767 ERROR("JTAG error while reading cpsr");
1771 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1773 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1775 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1777 return ERROR_TARGET_DATA_ABORT;
1783 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1785 armv4_5_common_t *armv4_5 = target->arch_info;
1786 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1787 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1790 int num_accesses = 0;
1791 int thisrun_accesses;
1797 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1799 if (target->state != TARGET_HALTED)
1801 WARNING("target not halted");
1802 return ERROR_TARGET_NOT_HALTED;
1805 /* sanitize arguments */
1806 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1807 return ERROR_INVALID_ARGUMENTS;
1809 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1810 return ERROR_TARGET_UNALIGNED_ACCESS;
1812 /* load the base register with the address of the first word */
1814 arm7_9->write_core_regs(target, 0x1, reg);
1816 /* Clear DBGACK, to make sure memory fetches work as expected */
1817 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1818 embeddedice_store_reg(dbg_ctrl);
1823 while (num_accesses < count)
1826 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1827 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1829 for (i = 1; i <= thisrun_accesses; i++)
1833 reg[i] = target_buffer_get_u32(target, buffer);
1837 arm7_9->write_core_regs(target, reg_list, reg);
1839 arm7_9->store_word_regs(target, reg_list);
1841 /* fast memory writes are only safe when the target is running
1842 * from a sufficiently high clock (32 kHz is usually too slow)
1844 if (arm7_9->fast_memory_access)
1845 arm7_9_execute_fast_sys_speed(target);
1847 arm7_9_execute_sys_speed(target);
1849 num_accesses += thisrun_accesses;
1853 while (num_accesses < count)
1856 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1857 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1859 for (i = 1; i <= thisrun_accesses; i++)
1863 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1867 arm7_9->write_core_regs(target, reg_list, reg);
1869 for (i = 1; i <= thisrun_accesses; i++)
1871 arm7_9->store_hword_reg(target, i);
1873 /* fast memory writes are only safe when the target is running
1874 * from a sufficiently high clock (32 kHz is usually too slow)
1876 if (arm7_9->fast_memory_access)
1877 arm7_9_execute_fast_sys_speed(target);
1879 arm7_9_execute_sys_speed(target);
1882 num_accesses += thisrun_accesses;
1886 while (num_accesses < count)
1889 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1890 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1892 for (i = 1; i <= thisrun_accesses; i++)
1896 reg[i] = *buffer++ & 0xff;
1899 arm7_9->write_core_regs(target, reg_list, reg);
1901 for (i = 1; i <= thisrun_accesses; i++)
1903 arm7_9->store_byte_reg(target, i);
1904 /* fast memory writes are only safe when the target is running
1905 * from a sufficiently high clock (32 kHz is usually too slow)
1907 if (arm7_9->fast_memory_access)
1908 arm7_9_execute_fast_sys_speed(target);
1910 arm7_9_execute_sys_speed(target);
1913 num_accesses += thisrun_accesses;
1917 ERROR("BUG: we shouldn't get here");
1923 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1924 embeddedice_store_reg(dbg_ctrl);
1926 for (i=0; i<=last_reg; i++)
1927 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1929 arm7_9->read_xpsr(target, &cpsr, 0);
1930 if ((retval = jtag_execute_queue()) != ERROR_OK)
1932 ERROR("JTAG error while reading cpsr");
1936 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1938 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1940 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1942 return ERROR_TARGET_DATA_ABORT;
1948 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1950 armv4_5_common_t *armv4_5 = target->arch_info;
1951 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1952 enum armv4_5_state core_state = armv4_5->core_state;
1953 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1954 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1955 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1960 /* MRC TST BNE MRC STR B */
1961 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1964 if (!arm7_9->dcc_downloads)
1965 return target->type->write_memory(target, address, 4, count, buffer);
1967 /* regrab previously allocated working_area, or allocate a new one */
1968 if (!arm7_9->dcc_working_area)
1970 u8 dcc_code_buf[6 * 4];
1972 /* make sure we have a working area */
1973 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
1975 INFO("no working area available, falling back to memory writes");
1976 return target->type->write_memory(target, address, 4, count, buffer);
1979 /* copy target instructions to target endianness */
1980 for (i = 0; i < 6; i++)
1982 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
1985 /* write DCC code to working area */
1986 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
1989 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
1990 armv4_5->core_cache->reg_list[0].valid = 1;
1991 armv4_5->core_cache->reg_list[0].dirty = 1;
1992 armv4_5->core_state = ARMV4_5_STATE_ARM;
1994 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
1996 for (i = 0; i < count; i++)
1998 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2002 target->type->halt(target);
2004 while (target->state != TARGET_HALTED)
2005 target->type->poll(target);
2007 /* restore target state */
2008 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2009 armv4_5->core_cache->reg_list[0].valid = 1;
2010 armv4_5->core_cache->reg_list[0].dirty = 1;
2011 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2012 armv4_5->core_cache->reg_list[1].valid = 1;
2013 armv4_5->core_cache->reg_list[1].dirty = 1;
2014 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2015 armv4_5->core_cache->reg_list[15].valid = 1;
2016 armv4_5->core_cache->reg_list[15].dirty = 1;
2017 armv4_5->core_state = core_state;
2022 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2024 command_t *arm7_9_cmd;
2026 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2028 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2029 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2031 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2033 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2034 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2035 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2036 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2037 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2038 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2039 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2040 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2041 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2042 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2044 armv4_5_register_commands(cmd_ctx);
2049 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2054 target_t *target = get_current_target(cmd_ctx);
2055 armv4_5_common_t *armv4_5;
2056 arm7_9_common_t *arm7_9;
2058 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2060 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2064 if (target->state != TARGET_HALTED)
2066 command_print(cmd_ctx, "can't write registers while running");
2072 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2076 value = strtoul(args[0], NULL, 0);
2077 spsr = strtol(args[1], NULL, 0);
2079 /* if we're writing the CPSR, mask the T bit */
2083 arm7_9->write_xpsr(target, value, spsr);
2084 if ((retval = jtag_execute_queue()) != ERROR_OK)
2086 ERROR("JTAG error while writing to xpsr");
2093 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2099 target_t *target = get_current_target(cmd_ctx);
2100 armv4_5_common_t *armv4_5;
2101 arm7_9_common_t *arm7_9;
2103 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2105 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2109 if (target->state != TARGET_HALTED)
2111 command_print(cmd_ctx, "can't write registers while running");
2117 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2121 value = strtoul(args[0], NULL, 0);
2122 rotate = strtol(args[1], NULL, 0);
2123 spsr = strtol(args[2], NULL, 0);
2125 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2126 if ((retval = jtag_execute_queue()) != ERROR_OK)
2128 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2135 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2140 target_t *target = get_current_target(cmd_ctx);
2141 armv4_5_common_t *armv4_5;
2142 arm7_9_common_t *arm7_9;
2144 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2146 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2150 if (target->state != TARGET_HALTED)
2152 command_print(cmd_ctx, "can't write registers while running");
2158 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2162 num = strtol(args[0], NULL, 0);
2163 mode = strtoul(args[1], NULL, 0);
2164 value = strtoul(args[2], NULL, 0);
2166 arm7_9_write_core_reg(target, num, mode, value);
2171 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2173 target_t *target = get_current_target(cmd_ctx);
2174 armv4_5_common_t *armv4_5;
2175 arm7_9_common_t *arm7_9;
2177 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2179 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2185 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2189 if (strcmp("enable", args[0]) == 0)
2191 if (arm7_9->sw_bkpts_use_wp)
2193 arm7_9_enable_sw_bkpts(target);
2197 arm7_9->sw_bkpts_enabled = 1;
2200 else if (strcmp("disable", args[0]) == 0)
2202 if (arm7_9->sw_bkpts_use_wp)
2204 arm7_9_disable_sw_bkpts(target);
2208 arm7_9->sw_bkpts_enabled = 0;
2213 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2216 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2221 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2223 target_t *target = get_current_target(cmd_ctx);
2224 armv4_5_common_t *armv4_5;
2225 arm7_9_common_t *arm7_9;
2227 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2229 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2233 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2235 arm7_9->force_hw_bkpts = 1;
2236 if (arm7_9->sw_bkpts_use_wp)
2238 arm7_9_disable_sw_bkpts(target);
2241 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2243 arm7_9->force_hw_bkpts = 0;
2247 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2250 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2255 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2257 target_t *target = get_current_target(cmd_ctx);
2258 armv4_5_common_t *armv4_5;
2259 arm7_9_common_t *arm7_9;
2261 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2263 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2269 if (strcmp("enable", args[0]) == 0)
2271 arm7_9->use_dbgrq = 1;
2273 else if (strcmp("disable", args[0]) == 0)
2275 arm7_9->use_dbgrq = 0;
2279 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2283 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2288 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2290 target_t *target = get_current_target(cmd_ctx);
2291 armv4_5_common_t *armv4_5;
2292 arm7_9_common_t *arm7_9;
2294 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2296 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2302 if (strcmp("enable", args[0]) == 0)
2304 arm7_9->fast_memory_access = 1;
2306 else if (strcmp("disable", args[0]) == 0)
2308 arm7_9->fast_memory_access = 0;
2312 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2316 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2321 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2323 target_t *target = get_current_target(cmd_ctx);
2324 armv4_5_common_t *armv4_5;
2325 arm7_9_common_t *arm7_9;
2327 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2329 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2335 if (strcmp("enable", args[0]) == 0)
2337 arm7_9->dcc_downloads = 1;
2339 else if (strcmp("disable", args[0]) == 0)
2341 arm7_9->dcc_downloads = 0;
2345 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2349 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2354 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2356 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2358 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2360 arm_jtag_setup_connection(&arm7_9->jtag_info);
2361 arm7_9->wp_available = 2;
2362 arm7_9->wp0_used = 0;
2363 arm7_9->wp1_used = 0;
2364 arm7_9->force_hw_bkpts = 0;
2365 arm7_9->use_dbgrq = 0;
2366 arm7_9->has_etm = 0;
2368 arm7_9->reinit_embeddedice = 0;
2370 arm7_9->dcc_working_area = NULL;
2372 arm7_9->fast_memory_access = 0;
2373 arm7_9->dcc_downloads = 0;
2375 jtag_register_event_callback(arm7_9_jtag_callback, target);
2377 armv4_5->arch_info = arm7_9;
2378 armv4_5->read_core_reg = arm7_9_read_core_reg;
2379 armv4_5->write_core_reg = arm7_9_write_core_reg;
2380 armv4_5->full_context = arm7_9_full_context;
2382 armv4_5_init_arch_info(target, armv4_5);