1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
26 #include "embeddedice.h"
32 #include "arm7_9_common.h"
33 #include "breakpoints.h"
39 #include <sys/types.h>
44 int arm7_9_debug_entry(target_t *target);
45 int arm7_9_enable_sw_bkpts(struct target_s *target);
47 /* command handler forward declarations */
48 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_arm7_9_read_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
56 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
58 int arm7_9_reinit_embeddedice(target_t *target)
60 armv4_5_common_t *armv4_5 = target->arch_info;
61 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
63 breakpoint_t *breakpoint = target->breakpoints;
65 arm7_9->wp_available = 2;
69 /* mark all hardware breakpoints as unset */
72 if (breakpoint->type == BKPT_HARD)
76 breakpoint = breakpoint->next;
79 if (arm7_9->sw_bkpts_enabled && arm7_9->sw_bkpts_use_wp)
81 arm7_9->sw_bkpts_enabled = 0;
82 arm7_9_enable_sw_bkpts(target);
85 arm7_9->reinit_embeddedice = 0;
90 int arm7_9_jtag_callback(enum jtag_event event, void *priv)
92 target_t *target = priv;
93 armv4_5_common_t *armv4_5 = target->arch_info;
94 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
96 /* a test-logic reset occured
97 * the EmbeddedICE registers have been reset
98 * hardware breakpoints have been cleared
100 if (event == JTAG_TRST_ASSERTED)
102 arm7_9->reinit_embeddedice = 1;
108 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
110 armv4_5_common_t *armv4_5 = target->arch_info;
111 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
113 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
118 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
123 *armv4_5_p = armv4_5;
129 int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
131 armv4_5_common_t *armv4_5 = target->arch_info;
132 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
134 if (target->state != TARGET_HALTED)
136 WARNING("target not halted");
137 return ERROR_TARGET_NOT_HALTED;
140 if (arm7_9->force_hw_bkpts)
141 breakpoint->type = BKPT_HARD;
145 WARNING("breakpoint already set");
149 if (breakpoint->type == BKPT_HARD)
151 /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
152 u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
153 if (!arm7_9->wp0_used)
155 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
156 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
157 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
158 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
159 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
161 jtag_execute_queue();
162 arm7_9->wp0_used = 1;
165 else if (!arm7_9->wp1_used)
167 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
168 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
169 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
170 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
171 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
173 jtag_execute_queue();
174 arm7_9->wp1_used = 1;
179 ERROR("BUG: no hardware comparator available");
183 else if (breakpoint->type == BKPT_SOFT)
185 if (breakpoint->length == 4)
187 /* keep the original instruction in target endianness */
188 target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
189 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
190 target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
194 /* keep the original instruction in target endianness */
195 target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
196 /* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
197 target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
206 int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
208 armv4_5_common_t *armv4_5 = target->arch_info;
209 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
211 if (target->state != TARGET_HALTED)
213 WARNING("target not halted");
214 return ERROR_TARGET_NOT_HALTED;
217 if (!breakpoint->set)
219 WARNING("breakpoint not set");
223 if (breakpoint->type == BKPT_HARD)
225 if (breakpoint->set == 1)
227 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
228 jtag_execute_queue();
229 arm7_9->wp0_used = 0;
231 else if (breakpoint->set == 2)
233 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
234 jtag_execute_queue();
235 arm7_9->wp1_used = 0;
241 /* restore original instruction (kept in target endianness) */
242 if (breakpoint->length == 4)
244 target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
248 target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
256 int arm7_9_add_breakpoint(struct target_s *target, u32 address, u32 length, enum breakpoint_type type)
258 armv4_5_common_t *armv4_5 = target->arch_info;
259 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
261 if (target->state != TARGET_HALTED)
263 WARNING("target not halted");
264 return ERROR_TARGET_NOT_HALTED;
267 if (arm7_9->force_hw_bkpts)
272 if ((type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
274 INFO("sw breakpoint requested, but software breakpoints not enabled");
275 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
278 if ((type == BKPT_HARD) && (arm7_9->wp_available < 1))
280 INFO("no watchpoint unit available for hardware breakpoint");
281 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
284 if ((length != 2) && (length != 4))
286 INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
287 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
290 if (type == BKPT_HARD)
291 arm7_9->wp_available--;
296 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
298 armv4_5_common_t *armv4_5 = target->arch_info;
299 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
301 if (target->state != TARGET_HALTED)
303 WARNING("target not halted");
304 return ERROR_TARGET_NOT_HALTED;
309 arm7_9_unset_breakpoint(target, breakpoint);
312 if (breakpoint->type == BKPT_HARD)
313 arm7_9->wp_available++;
318 int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
320 armv4_5_common_t *armv4_5 = target->arch_info;
321 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
325 mask = watchpoint->length - 1;
327 if (target->state != TARGET_HALTED)
329 WARNING("target not halted");
330 return ERROR_TARGET_NOT_HALTED;
333 if (watchpoint->rw == WPT_ACCESS)
338 if (!arm7_9->wp0_used)
340 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
341 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
342 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
343 if( watchpoint->mask != 0xffffffffu )
344 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
345 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
346 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
348 jtag_execute_queue();
350 arm7_9->wp0_used = 2;
352 else if (!arm7_9->wp1_used)
354 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
355 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
356 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
357 if( watchpoint->mask != 0xffffffffu )
358 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
359 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
360 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
362 jtag_execute_queue();
364 arm7_9->wp1_used = 2;
368 ERROR("BUG: no hardware comparator available");
375 int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
377 armv4_5_common_t *armv4_5 = target->arch_info;
378 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
380 if (target->state != TARGET_HALTED)
382 WARNING("target not halted");
383 return ERROR_TARGET_NOT_HALTED;
386 if (!watchpoint->set)
388 WARNING("breakpoint not set");
392 if (watchpoint->set == 1)
394 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
395 jtag_execute_queue();
396 arm7_9->wp0_used = 0;
398 else if (watchpoint->set == 2)
400 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
401 jtag_execute_queue();
402 arm7_9->wp1_used = 0;
409 int arm7_9_add_watchpoint(struct target_s *target, u32 address, u32 length, enum watchpoint_rw rw)
411 armv4_5_common_t *armv4_5 = target->arch_info;
412 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
414 if (target->state != TARGET_HALTED)
416 WARNING("target not halted");
417 return ERROR_TARGET_NOT_HALTED;
420 if (arm7_9->wp_available < 1)
422 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
425 if ((length != 1) && (length != 2) && (length != 4))
427 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
430 arm7_9->wp_available--;
435 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
437 armv4_5_common_t *armv4_5 = target->arch_info;
438 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440 if (target->state != TARGET_HALTED)
442 WARNING("target not halted");
443 return ERROR_TARGET_NOT_HALTED;
448 arm7_9_unset_watchpoint(target, watchpoint);
451 arm7_9->wp_available++;
456 int arm7_9_enable_sw_bkpts(struct target_s *target)
458 armv4_5_common_t *armv4_5 = target->arch_info;
459 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
462 if (arm7_9->sw_bkpts_enabled)
465 if (arm7_9->wp_available < 1)
467 WARNING("can't enable sw breakpoints with no watchpoint unit available");
468 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
470 arm7_9->wp_available--;
472 if (!arm7_9->wp0_used)
474 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
475 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
476 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
477 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
478 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
479 arm7_9->sw_bkpts_enabled = 1;
480 arm7_9->wp0_used = 3;
482 else if (!arm7_9->wp1_used)
484 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
485 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
486 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
487 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
488 embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
489 arm7_9->sw_bkpts_enabled = 2;
490 arm7_9->wp1_used = 3;
494 ERROR("BUG: both watchpoints used, but wp_available >= 1");
498 if ((retval = jtag_execute_queue()) != ERROR_OK)
500 ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
507 int arm7_9_disable_sw_bkpts(struct target_s *target)
509 armv4_5_common_t *armv4_5 = target->arch_info;
510 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
512 if (!arm7_9->sw_bkpts_enabled)
515 if (arm7_9->sw_bkpts_enabled == 1)
517 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
518 arm7_9->sw_bkpts_enabled = 0;
519 arm7_9->wp0_used = 0;
520 arm7_9->wp_available++;
522 else if (arm7_9->sw_bkpts_enabled == 2)
524 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
525 arm7_9->sw_bkpts_enabled = 0;
526 arm7_9->wp1_used = 0;
527 arm7_9->wp_available++;
533 int arm7_9_execute_sys_speed(struct target_s *target)
538 armv4_5_common_t *armv4_5 = target->arch_info;
539 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
540 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
541 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
543 /* set RESTART instruction */
544 jtag_add_end_state(TAP_RTI);
545 arm_jtag_set_instr(jtag_info, 0x4);
547 for (timeout=0; timeout<50; timeout++)
549 /* read debug status register */
550 embeddedice_read_reg(dbg_stat);
551 if ((retval = jtag_execute_queue()) != ERROR_OK)
553 if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
554 && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
560 ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
561 return ERROR_TARGET_TIMEOUT;
567 int arm7_9_execute_fast_sys_speed(struct target_s *target)
569 u8 check_value[4], check_mask[4];
571 armv4_5_common_t *armv4_5 = target->arch_info;
572 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
573 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
574 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
576 /* set RESTART instruction */
577 jtag_add_end_state(TAP_RTI);
578 arm_jtag_set_instr(jtag_info, 0x4);
580 /* check for DBGACK and SYSCOMP set (others don't care) */
581 buf_set_u32(check_value, 0, 32, 0x9);
582 buf_set_u32(check_mask, 0, 32, 0x9);
584 /* read debug status register */
585 embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
590 enum target_state arm7_9_poll(target_t *target)
593 armv4_5_common_t *armv4_5 = target->arch_info;
594 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
595 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
597 if (arm7_9->reinit_embeddedice)
599 arm7_9_reinit_embeddedice(target);
602 /* read debug status register */
603 embeddedice_read_reg(dbg_stat);
604 if ((retval = jtag_execute_queue()) != ERROR_OK)
608 case ERROR_JTAG_QUEUE_FAILED:
609 ERROR("JTAG queue failed while reading EmbeddedICE status register");
617 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
619 DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
620 if ((target->state == TARGET_UNKNOWN))
622 WARNING("DBGACK set while target was in unknown state. Reset or initialize target before resuming");
623 target->state = TARGET_RUNNING;
625 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
627 target->state = TARGET_HALTED;
628 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
631 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
633 if (target->state == TARGET_DEBUG_RUNNING)
635 target->state = TARGET_HALTED;
636 if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
639 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
644 if (target->state != TARGET_DEBUG_RUNNING)
645 target->state = TARGET_RUNNING;
648 return target->state;
651 int arm7_9_assert_reset(target_t *target)
655 DEBUG("target->state: %s", target_state_strings[target->state]);
657 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
659 /* if the target wasn't running, there might be working areas allocated */
660 target_free_all_working_areas(target);
662 /* assert SRST and TRST */
663 /* system would get ouf sync if we didn't reset test-logic, too */
664 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
666 if (retval == ERROR_JTAG_RESET_CANT_SRST)
668 WARNING("can't assert srst");
673 ERROR("unknown error");
677 jtag_add_sleep(5000);
678 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
680 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
682 WARNING("srst resets test logic, too");
683 retval = jtag_add_reset(1, 1);
689 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
691 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
693 WARNING("srst resets test logic, too");
694 retval = jtag_add_reset(1, 1);
697 if (retval == ERROR_JTAG_RESET_CANT_SRST)
699 WARNING("can't assert srst");
702 else if (retval != ERROR_OK)
704 ERROR("unknown error");
710 target->state = TARGET_RESET;
711 jtag_add_sleep(50000);
713 armv4_5_invalidate_core_regs(target);
719 int arm7_9_deassert_reset(target_t *target)
721 DEBUG("target->state: %s", target_state_strings[target->state]);
723 /* deassert reset lines */
724 jtag_add_reset(0, 0);
730 int arm7_9_clear_halt(target_t *target)
732 armv4_5_common_t *armv4_5 = target->arch_info;
733 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
734 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
736 if (arm7_9->use_dbgrq)
738 /* program EmbeddedICE Debug Control Register to deassert DBGRQ
740 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
741 embeddedice_store_reg(dbg_ctrl);
745 /* restore registers if watchpoint unit 0 was in use
747 if (arm7_9->wp0_used)
749 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
750 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
751 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
753 /* control value always has to be restored, as it was either disabled,
754 * or enabled with possibly different bits
756 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
762 int arm7_9_soft_reset_halt(struct target_s *target)
764 armv4_5_common_t *armv4_5 = target->arch_info;
765 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
766 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
767 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
770 if (target->state == TARGET_RUNNING)
772 target->type->halt(target);
775 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
777 embeddedice_read_reg(dbg_stat);
778 jtag_execute_queue();
780 target->state = TARGET_HALTED;
782 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
783 * ensure that DBGRQ is cleared
785 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
786 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
787 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
788 embeddedice_store_reg(dbg_ctrl);
790 arm7_9_clear_halt(target);
792 /* if the target is in Thumb state, change to ARM state */
793 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
795 u32 r0_thumb, pc_thumb;
796 DEBUG("target entered debug from Thumb state, changing to ARM");
797 /* Entered debug from Thumb mode */
798 armv4_5->core_state = ARMV4_5_STATE_THUMB;
799 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
802 /* all register content is now invalid */
803 armv4_5_invalidate_core_regs(target);
805 /* SVC, ARM state, IRQ and FIQ disabled */
806 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
807 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
808 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
810 /* start fetching from 0x0 */
811 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
812 armv4_5->core_cache->reg_list[15].dirty = 1;
813 armv4_5->core_cache->reg_list[15].valid = 1;
815 armv4_5->core_mode = ARMV4_5_MODE_SVC;
816 armv4_5->core_state = ARMV4_5_STATE_ARM;
818 /* reset registers */
819 for (i = 0; i <= 14; i++)
821 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
822 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
823 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
826 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
831 int arm7_9_halt(target_t *target)
833 armv4_5_common_t *armv4_5 = target->arch_info;
834 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
835 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
837 DEBUG("target->state: %s", target_state_strings[target->state]);
839 if (target->state == TARGET_HALTED)
841 WARNING("target was already halted");
842 return ERROR_TARGET_ALREADY_HALTED;
845 if (target->state == TARGET_UNKNOWN)
847 WARNING("target was in unknown state when halt was requested");
850 if ((target->state == TARGET_RESET) && (jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_srst))
852 ERROR("can't request a halt while in reset if nSRST pulls nTRST");
853 return ERROR_TARGET_FAILURE;
856 if (arm7_9->use_dbgrq)
858 /* program EmbeddedICE Debug Control Register to assert DBGRQ
860 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
861 embeddedice_store_reg(dbg_ctrl);
865 /* program watchpoint unit to match on any address
867 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
868 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
869 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
870 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
873 target->debug_reason = DBG_REASON_DBGRQ;
878 int arm7_9_debug_entry(target_t *target)
883 u32 r0_thumb, pc_thumb;
886 /* get pointers to arch-specific information */
887 armv4_5_common_t *armv4_5 = target->arch_info;
888 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
889 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
890 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
892 #ifdef _DEBUG_ARM7_9_
896 if (arm7_9->pre_debug_entry)
897 arm7_9->pre_debug_entry(target);
899 /* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
900 * ensure that DBGRQ is cleared
902 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
903 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
904 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
905 embeddedice_store_reg(dbg_ctrl);
907 arm7_9_clear_halt(target);
909 if ((retval = jtag_execute_queue()) != ERROR_OK)
913 case ERROR_JTAG_QUEUE_FAILED:
914 ERROR("JTAG queue failed while writing EmbeddedICE control register");
922 if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
926 if (target->state != TARGET_HALTED)
928 WARNING("target not halted");
929 return ERROR_TARGET_NOT_HALTED;
932 /* if the target is in Thumb state, change to ARM state */
933 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
935 DEBUG("target entered debug from Thumb state");
936 /* Entered debug from Thumb mode */
937 armv4_5->core_state = ARMV4_5_STATE_THUMB;
938 arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
939 DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
943 DEBUG("target entered debug from ARM state");
944 /* Entered debug from ARM mode */
945 armv4_5->core_state = ARMV4_5_STATE_ARM;
948 for (i = 0; i < 16; i++)
949 context_p[i] = &context[i];
950 /* save core registers (r0 - r15 of current core mode) */
951 arm7_9->read_core_regs(target, 0xffff, context_p);
953 arm7_9->read_xpsr(target, &cpsr, 0);
955 if ((retval = jtag_execute_queue()) != ERROR_OK)
958 /* if the core has been executing in Thumb state, set the T bit */
959 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
962 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
963 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
964 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
966 armv4_5->core_mode = cpsr & 0x1f;
968 if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
970 target->state = TARGET_UNKNOWN;
971 ERROR("cpsr contains invalid mode value - communication failure");
972 return ERROR_TARGET_FAILURE;
975 DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
977 if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
979 DEBUG("thumb state, applying fixups");
980 context[0] = r0_thumb;
981 context[15] = pc_thumb;
982 } else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
984 /* adjust value stored by STM */
985 context[15] -= 3 * 4;
988 if ((target->debug_reason == DBG_REASON_BREAKPOINT)
989 || (target->debug_reason == DBG_REASON_SINGLESTEP)
990 || (target->debug_reason == DBG_REASON_WATCHPOINT)
991 || (target->debug_reason == DBG_REASON_WPTANDBKPT)
992 || ((target->debug_reason == DBG_REASON_DBGRQ) && (arm7_9->use_dbgrq == 0)))
993 context[15] -= 3 * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
994 else if (target->debug_reason == DBG_REASON_DBGRQ)
995 context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
998 ERROR("unknown debug reason: %i", target->debug_reason);
1002 for (i=0; i<=15; i++)
1004 DEBUG("r%i: 0x%8.8x", i, context[i]);
1005 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
1006 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
1007 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
1010 DEBUG("entered debug state at PC 0x%x", context[15]);
1012 /* exceptions other than USR & SYS have a saved program status register */
1013 if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
1016 arm7_9->read_xpsr(target, &spsr, 1);
1017 jtag_execute_queue();
1018 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
1019 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
1020 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
1023 /* r0 and r15 (pc) have to be restored later */
1024 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1025 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
1027 if ((retval = jtag->execute_queue()) != ERROR_OK)
1030 if (arm7_9->post_debug_entry)
1031 arm7_9->post_debug_entry(target);
1036 int arm7_9_full_context(target_t *target)
1040 armv4_5_common_t *armv4_5 = target->arch_info;
1041 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1045 if (target->state != TARGET_HALTED)
1047 WARNING("target not halted");
1048 return ERROR_TARGET_NOT_HALTED;
1051 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1052 * SYS shares registers with User, so we don't touch SYS
1054 for(i = 0; i < 6; i++)
1061 /* check if there are invalid registers in the current mode
1063 for (j = 0; j <= 16; j++)
1065 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1073 /* change processor mode (and mask T bit) */
1074 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1075 tmp_cpsr |= armv4_5_number_to_mode(i);
1077 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1079 for (j = 0; j < 15; j++)
1081 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
1083 reg_p[j] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value;
1085 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
1086 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
1090 /* if only the PSR is invalid, mask is all zeroes */
1092 arm7_9->read_core_regs(target, mask, reg_p);
1094 /* check if the PSR has to be read */
1095 if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
1097 arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1);
1098 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
1099 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
1104 /* restore processor mode (mask T bit) */
1105 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1107 if ((retval = jtag_execute_queue()) != ERROR_OK)
1109 ERROR("JTAG failure");
1115 int arm7_9_restore_context(target_t *target)
1117 armv4_5_common_t *armv4_5 = target->arch_info;
1118 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1120 armv4_5_core_reg_t *reg_arch_info;
1121 enum armv4_5_mode current_mode = armv4_5->core_mode;
1128 if (target->state != TARGET_HALTED)
1130 WARNING("target not halted");
1131 return ERROR_TARGET_NOT_HALTED;
1134 if (arm7_9->pre_restore_context)
1135 arm7_9->pre_restore_context(target);
1137 /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
1138 * SYS shares registers with User, so we don't touch SYS
1140 for (i = 0; i < 6; i++)
1142 DEBUG("examining %s mode", armv4_5_mode_strings[i]);
1145 /* check if there are dirty registers in the current mode
1147 for (j = 0; j <= 16; j++)
1149 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1150 reg_arch_info = reg->arch_info;
1151 if (reg->dirty == 1)
1153 if (reg->valid == 1)
1156 DEBUG("examining dirty reg: %s", reg->name);
1157 if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
1158 && (reg_arch_info->mode != current_mode)
1159 && !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
1160 && !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
1163 DEBUG("require mode change");
1168 ERROR("BUG: dirty register '%s', but no valid data", reg->name);
1184 /* change processor mode (mask T bit) */
1185 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1186 tmp_cpsr |= armv4_5_number_to_mode(i);
1188 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1189 current_mode = armv4_5_number_to_mode(i);
1192 for (j = 0; j <= 14; j++)
1194 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j);
1195 reg_arch_info = reg->arch_info;
1198 if (reg->dirty == 1)
1200 regs[j] = buf_get_u32(reg->value, 0, 32);
1205 DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
1211 arm7_9->write_core_regs(target, mask, regs);
1214 reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16);
1215 reg_arch_info = reg->arch_info;
1216 if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
1218 DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
1219 arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
1224 if ((armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 0) && (armv4_5->core_mode != current_mode))
1226 /* restore processor mode (mask T bit) */
1229 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1230 tmp_cpsr |= armv4_5_number_to_mode(i);
1232 DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
1233 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1235 else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
1237 /* CPSR has been changed, full restore necessary (mask T bit) */
1238 DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
1239 arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
1240 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
1241 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
1245 DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1246 arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1247 armv4_5->core_cache->reg_list[15].dirty = 0;
1249 if (arm7_9->post_restore_context)
1250 arm7_9->post_restore_context(target);
1255 int arm7_9_restart_core(struct target_s *target)
1257 armv4_5_common_t *armv4_5 = target->arch_info;
1258 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1259 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
1261 /* set RESTART instruction */
1262 jtag_add_end_state(TAP_RTI);
1263 arm_jtag_set_instr(jtag_info, 0x4);
1265 jtag_add_runtest(1, TAP_RTI);
1266 if ((jtag_execute_queue()) != ERROR_OK)
1274 void arm7_9_enable_watchpoints(struct target_s *target)
1276 watchpoint_t *watchpoint = target->watchpoints;
1280 if (watchpoint->set == 0)
1281 arm7_9_set_watchpoint(target, watchpoint);
1282 watchpoint = watchpoint->next;
1286 void arm7_9_enable_breakpoints(struct target_s *target)
1288 breakpoint_t *breakpoint = target->breakpoints;
1290 /* set any pending breakpoints */
1293 if (breakpoint->set == 0)
1294 arm7_9_set_breakpoint(target, breakpoint);
1295 breakpoint = breakpoint->next;
1299 void arm7_9_disable_bkpts_and_wpts(struct target_s *target)
1301 breakpoint_t *breakpoint = target->breakpoints;
1302 watchpoint_t *watchpoint = target->watchpoints;
1304 /* set any pending breakpoints */
1307 if (breakpoint->set != 0)
1308 arm7_9_unset_breakpoint(target, breakpoint);
1309 breakpoint = breakpoint->next;
1314 if (watchpoint->set != 0)
1315 arm7_9_unset_watchpoint(target, watchpoint);
1316 watchpoint = watchpoint->next;
1320 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
1322 armv4_5_common_t *armv4_5 = target->arch_info;
1323 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1324 breakpoint_t *breakpoint = target->breakpoints;
1325 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1329 if (target->state != TARGET_HALTED)
1331 WARNING("target not halted");
1332 return ERROR_TARGET_NOT_HALTED;
1335 if (!debug_execution)
1337 target_free_all_working_areas(target);
1340 /* current = 1: continue on current pc, otherwise continue at <address> */
1342 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1344 /* the front-end may request us not to handle breakpoints */
1345 if (handle_breakpoints)
1347 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1349 DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
1350 arm7_9_unset_breakpoint(target, breakpoint);
1352 DEBUG("enable single-step");
1353 arm7_9->enable_single_step(target);
1355 target->debug_reason = DBG_REASON_SINGLESTEP;
1357 arm7_9_restore_context(target);
1359 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1360 arm7_9->branch_resume(target);
1361 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1363 arm7_9->branch_resume_thumb(target);
1367 ERROR("unhandled core state");
1371 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1372 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1373 arm7_9_execute_sys_speed(target);
1375 DEBUG("disable single-step");
1376 arm7_9->disable_single_step(target);
1378 arm7_9_debug_entry(target);
1379 DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1381 DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
1382 arm7_9_set_breakpoint(target, breakpoint);
1386 /* enable any pending breakpoints and watchpoints */
1387 arm7_9_enable_breakpoints(target);
1388 arm7_9_enable_watchpoints(target);
1390 arm7_9_restore_context(target);
1392 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1394 arm7_9->branch_resume(target);
1396 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1398 arm7_9->branch_resume_thumb(target);
1402 ERROR("unhandled core state");
1406 /* deassert DBGACK and INTDIS */
1407 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1408 /* INTDIS only when we really resume, not during debug execution */
1409 if (!debug_execution)
1410 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
1411 embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
1413 arm7_9_restart_core(target);
1415 target->debug_reason = DBG_REASON_NOTHALTED;
1417 if (!debug_execution)
1419 /* registers are now invalid */
1420 armv4_5_invalidate_core_regs(target);
1421 target->state = TARGET_RUNNING;
1422 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1426 target->state = TARGET_DEBUG_RUNNING;
1427 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1430 DEBUG("target resumed");
1435 void arm7_9_enable_eice_step(target_t *target)
1437 armv4_5_common_t *armv4_5 = target->arch_info;
1438 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1440 /* setup an inverse breakpoint on the current PC
1441 * - comparator 1 matches the current address
1442 * - rangeout from comparator 1 is connected to comparator 0 rangein
1443 * - comparator 0 matches any address, as long as rangein is low */
1444 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
1445 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
1446 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
1447 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0x77);
1448 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
1449 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
1450 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
1451 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
1452 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xf7);
1455 void arm7_9_disable_eice_step(target_t *target)
1457 armv4_5_common_t *armv4_5 = target->arch_info;
1458 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1460 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
1461 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
1462 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE]);
1463 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
1464 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE]);
1465 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK]);
1466 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK]);
1467 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK]);
1468 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
1471 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
1473 armv4_5_common_t *armv4_5 = target->arch_info;
1474 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1475 breakpoint_t *breakpoint = NULL;
1477 if (target->state != TARGET_HALTED)
1479 WARNING("target not halted");
1480 return ERROR_TARGET_NOT_HALTED;
1483 /* current = 1: continue on current pc, otherwise continue at <address> */
1485 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, address);
1487 /* the front-end may request us not to handle breakpoints */
1488 if (handle_breakpoints)
1489 if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
1490 arm7_9_unset_breakpoint(target, breakpoint);
1492 target->debug_reason = DBG_REASON_SINGLESTEP;
1494 arm7_9_restore_context(target);
1496 arm7_9->enable_single_step(target);
1498 if (armv4_5->core_state == ARMV4_5_STATE_ARM)
1500 arm7_9->branch_resume(target);
1502 else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
1504 arm7_9->branch_resume_thumb(target);
1508 ERROR("unhandled core state");
1512 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1514 arm7_9_execute_sys_speed(target);
1515 arm7_9->disable_single_step(target);
1517 /* registers are now invalid */
1518 armv4_5_invalidate_core_regs(target);
1520 arm7_9_debug_entry(target);
1522 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1525 arm7_9_set_breakpoint(target, breakpoint);
1527 DEBUG("target stepped");
1533 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
1538 armv4_5_common_t *armv4_5 = target->arch_info;
1539 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1540 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1542 if ((num < 0) || (num > 16))
1543 return ERROR_INVALID_ARGUMENTS;
1545 if ((mode != ARMV4_5_MODE_ANY)
1546 && (mode != armv4_5->core_mode)
1547 && (reg_mode != ARMV4_5_MODE_ANY))
1551 /* change processor mode (mask T bit) */
1552 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1555 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1558 if ((num >= 0) && (num <= 15))
1560 /* read a normal core register */
1561 reg_p[num] = &value;
1563 arm7_9->read_core_regs(target, 1 << num, reg_p);
1567 /* read a program status register
1568 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
1570 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1571 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1573 arm7_9->read_xpsr(target, &value, spsr);
1576 if ((retval = jtag_execute_queue()) != ERROR_OK)
1578 ERROR("JTAG failure");
1582 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1583 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1584 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
1586 if ((mode != ARMV4_5_MODE_ANY)
1587 && (mode != armv4_5->core_mode)
1588 && (reg_mode != ARMV4_5_MODE_ANY)) {
1589 /* restore processor mode (mask T bit) */
1590 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1597 int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, u32 value)
1601 armv4_5_common_t *armv4_5 = target->arch_info;
1602 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1603 enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
1605 if ((num < 0) || (num > 16))
1606 return ERROR_INVALID_ARGUMENTS;
1608 if ((mode != ARMV4_5_MODE_ANY)
1609 && (mode != armv4_5->core_mode)
1610 && (reg_mode != ARMV4_5_MODE_ANY)) {
1613 /* change processor mode (mask T bit) */
1614 tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
1617 arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
1620 if ((num >= 0) && (num <= 15))
1622 /* write a normal core register */
1625 arm7_9->write_core_regs(target, 1 << num, reg);
1629 /* write a program status register
1630 * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
1632 armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
1633 int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
1635 /* if we're writing the CPSR, mask the T bit */
1639 arm7_9->write_xpsr(target, value, spsr);
1642 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
1643 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
1645 if ((mode != ARMV4_5_MODE_ANY)
1646 && (mode != armv4_5->core_mode)
1647 && (reg_mode != ARMV4_5_MODE_ANY)) {
1648 /* restore processor mode (mask T bit) */
1649 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1652 if ((retval = jtag_execute_queue()) != ERROR_OK)
1654 ERROR("JTAG failure");
1662 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1664 armv4_5_common_t *armv4_5 = target->arch_info;
1665 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1668 int num_accesses = 0;
1669 int thisrun_accesses;
1675 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1677 if (target->state != TARGET_HALTED)
1679 WARNING("target not halted");
1680 return ERROR_TARGET_NOT_HALTED;
1683 /* sanitize arguments */
1684 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1685 return ERROR_INVALID_ARGUMENTS;
1687 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1688 return ERROR_TARGET_UNALIGNED_ACCESS;
1690 /* load the base register with the address of the first word */
1692 arm7_9->write_core_regs(target, 0x1, reg);
1697 while (num_accesses < count)
1700 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1701 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1703 if (last_reg <= thisrun_accesses)
1704 last_reg = thisrun_accesses;
1706 arm7_9->load_word_regs(target, reg_list);
1708 /* fast memory reads are only safe when the target is running
1709 * from a sufficiently high clock (32 kHz is usually too slow)
1711 if (arm7_9->fast_memory_access)
1712 arm7_9_execute_fast_sys_speed(target);
1714 arm7_9_execute_sys_speed(target);
1716 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4);
1718 /* advance buffer, count number of accesses */
1719 buffer += thisrun_accesses * 4;
1720 num_accesses += thisrun_accesses;
1724 while (num_accesses < count)
1727 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1728 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1730 for (i = 1; i <= thisrun_accesses; i++)
1734 arm7_9->load_hword_reg(target, i);
1735 /* fast memory reads are only safe when the target is running
1736 * from a sufficiently high clock (32 kHz is usually too slow)
1738 if (arm7_9->fast_memory_access)
1739 arm7_9_execute_fast_sys_speed(target);
1741 arm7_9_execute_sys_speed(target);
1744 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2);
1746 /* advance buffer, count number of accesses */
1747 buffer += thisrun_accesses * 2;
1748 num_accesses += thisrun_accesses;
1752 while (num_accesses < count)
1755 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1756 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1758 for (i = 1; i <= thisrun_accesses; i++)
1762 arm7_9->load_byte_reg(target, i);
1763 /* fast memory reads are only safe when the target is running
1764 * from a sufficiently high clock (32 kHz is usually too slow)
1766 if (arm7_9->fast_memory_access)
1767 arm7_9_execute_fast_sys_speed(target);
1769 arm7_9_execute_sys_speed(target);
1772 arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
1774 /* advance buffer, count number of accesses */
1775 buffer += thisrun_accesses * 1;
1776 num_accesses += thisrun_accesses;
1780 ERROR("BUG: we shouldn't get here");
1785 for (i=0; i<=last_reg; i++)
1786 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1788 arm7_9->read_xpsr(target, &cpsr, 0);
1789 if ((retval = jtag_execute_queue()) != ERROR_OK)
1791 ERROR("JTAG error while reading cpsr");
1795 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1797 WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1799 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1801 return ERROR_TARGET_DATA_ABORT;
1807 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
1809 armv4_5_common_t *armv4_5 = target->arch_info;
1810 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1811 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
1814 int num_accesses = 0;
1815 int thisrun_accesses;
1821 DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
1823 if (target->state != TARGET_HALTED)
1825 WARNING("target not halted");
1826 return ERROR_TARGET_NOT_HALTED;
1829 /* sanitize arguments */
1830 if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1831 return ERROR_INVALID_ARGUMENTS;
1833 if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1834 return ERROR_TARGET_UNALIGNED_ACCESS;
1836 /* load the base register with the address of the first word */
1838 arm7_9->write_core_regs(target, 0x1, reg);
1840 /* Clear DBGACK, to make sure memory fetches work as expected */
1841 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
1842 embeddedice_store_reg(dbg_ctrl);
1847 while (num_accesses < count)
1850 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1851 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1853 for (i = 1; i <= thisrun_accesses; i++)
1857 reg[i] = target_buffer_get_u32(target, buffer);
1861 arm7_9->write_core_regs(target, reg_list, reg);
1863 arm7_9->store_word_regs(target, reg_list);
1865 /* fast memory writes are only safe when the target is running
1866 * from a sufficiently high clock (32 kHz is usually too slow)
1868 if (arm7_9->fast_memory_access)
1869 arm7_9_execute_fast_sys_speed(target);
1871 arm7_9_execute_sys_speed(target);
1873 num_accesses += thisrun_accesses;
1877 while (num_accesses < count)
1880 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1881 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1883 for (i = 1; i <= thisrun_accesses; i++)
1887 reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
1891 arm7_9->write_core_regs(target, reg_list, reg);
1893 for (i = 1; i <= thisrun_accesses; i++)
1895 arm7_9->store_hword_reg(target, i);
1897 /* fast memory writes are only safe when the target is running
1898 * from a sufficiently high clock (32 kHz is usually too slow)
1900 if (arm7_9->fast_memory_access)
1901 arm7_9_execute_fast_sys_speed(target);
1903 arm7_9_execute_sys_speed(target);
1906 num_accesses += thisrun_accesses;
1910 while (num_accesses < count)
1913 thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
1914 reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
1916 for (i = 1; i <= thisrun_accesses; i++)
1920 reg[i] = *buffer++ & 0xff;
1923 arm7_9->write_core_regs(target, reg_list, reg);
1925 for (i = 1; i <= thisrun_accesses; i++)
1927 arm7_9->store_byte_reg(target, i);
1928 /* fast memory writes are only safe when the target is running
1929 * from a sufficiently high clock (32 kHz is usually too slow)
1931 if (arm7_9->fast_memory_access)
1932 arm7_9_execute_fast_sys_speed(target);
1934 arm7_9_execute_sys_speed(target);
1937 num_accesses += thisrun_accesses;
1941 ERROR("BUG: we shouldn't get here");
1947 buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
1948 embeddedice_store_reg(dbg_ctrl);
1950 for (i=0; i<=last_reg; i++)
1951 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
1953 arm7_9->read_xpsr(target, &cpsr, 0);
1954 if ((retval = jtag_execute_queue()) != ERROR_OK)
1956 ERROR("JTAG error while reading cpsr");
1960 if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
1962 WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
1964 arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
1966 return ERROR_TARGET_DATA_ABORT;
1972 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
1974 armv4_5_common_t *armv4_5 = target->arch_info;
1975 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
1976 enum armv4_5_state core_state = armv4_5->core_state;
1977 u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
1978 u32 r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
1979 u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
1984 /* MRC TST BNE MRC STR B */
1985 0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
1988 if (!arm7_9->dcc_downloads)
1989 return target->type->write_memory(target, address, 4, count, buffer);
1991 /* regrab previously allocated working_area, or allocate a new one */
1992 if (!arm7_9->dcc_working_area)
1994 u8 dcc_code_buf[6 * 4];
1996 /* make sure we have a working area */
1997 if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
1999 INFO("no working area available, falling back to memory writes");
2000 return target->type->write_memory(target, address, 4, count, buffer);
2003 /* copy target instructions to target endianness */
2004 for (i = 0; i < 6; i++)
2006 target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
2009 /* write DCC code to working area */
2010 target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
2013 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address);
2014 armv4_5->core_cache->reg_list[0].valid = 1;
2015 armv4_5->core_cache->reg_list[0].dirty = 1;
2016 armv4_5->core_state = ARMV4_5_STATE_ARM;
2018 arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
2020 for (i = 0; i < count; i++)
2022 embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], target_buffer_get_u32(target, buffer));
2026 target->type->halt(target);
2028 while (target->state != TARGET_HALTED)
2029 target->type->poll(target);
2031 /* restore target state */
2032 buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, r0);
2033 armv4_5->core_cache->reg_list[0].valid = 1;
2034 armv4_5->core_cache->reg_list[0].dirty = 1;
2035 buf_set_u32(armv4_5->core_cache->reg_list[1].value, 0, 32, r1);
2036 armv4_5->core_cache->reg_list[1].valid = 1;
2037 armv4_5->core_cache->reg_list[1].dirty = 1;
2038 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, pc);
2039 armv4_5->core_cache->reg_list[15].valid = 1;
2040 armv4_5->core_cache->reg_list[15].dirty = 1;
2041 armv4_5->core_state = core_state;
2046 int arm7_9_register_commands(struct command_context_s *cmd_ctx)
2048 command_t *arm7_9_cmd;
2050 arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
2052 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
2053 register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
2055 register_command(cmd_ctx, arm7_9_cmd, "write_core_reg", handle_arm7_9_write_core_reg_command, COMMAND_EXEC, "write core register <num> <mode> <value>");
2057 register_command(cmd_ctx, arm7_9_cmd, "sw_bkpts", handle_arm7_9_sw_bkpts_command, COMMAND_EXEC, "support for software breakpoints <enable|disable>");
2058 register_command(cmd_ctx, arm7_9_cmd, "force_hw_bkpts", handle_arm7_9_force_hw_bkpts_command, COMMAND_EXEC, "use hardware breakpoints for all breakpoints (disables sw breakpoint support) <enable|disable>");
2059 register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command,
2060 COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>");
2061 register_command(cmd_ctx, arm7_9_cmd, "fast_writes", handle_arm7_9_fast_memory_access_command,
2062 COMMAND_ANY, "(deprecated, see: arm7_9 fast_memory_access)");
2063 register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command,
2064 COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>");
2065 register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command,
2066 COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>");
2068 armv4_5_register_commands(cmd_ctx);
2073 int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2078 target_t *target = get_current_target(cmd_ctx);
2079 armv4_5_common_t *armv4_5;
2080 arm7_9_common_t *arm7_9;
2082 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2084 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2088 if (target->state != TARGET_HALTED)
2090 command_print(cmd_ctx, "can't write registers while running");
2096 command_print(cmd_ctx, "usage: write_xpsr <value> <not cpsr|spsr>");
2100 value = strtoul(args[0], NULL, 0);
2101 spsr = strtol(args[1], NULL, 0);
2103 /* if we're writing the CPSR, mask the T bit */
2107 arm7_9->write_xpsr(target, value, spsr);
2108 if ((retval = jtag_execute_queue()) != ERROR_OK)
2110 ERROR("JTAG error while writing to xpsr");
2117 int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2123 target_t *target = get_current_target(cmd_ctx);
2124 armv4_5_common_t *armv4_5;
2125 arm7_9_common_t *arm7_9;
2127 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2129 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2133 if (target->state != TARGET_HALTED)
2135 command_print(cmd_ctx, "can't write registers while running");
2141 command_print(cmd_ctx, "usage: write_xpsr_im8 <im8> <rotate> <not cpsr|spsr>");
2145 value = strtoul(args[0], NULL, 0);
2146 rotate = strtol(args[1], NULL, 0);
2147 spsr = strtol(args[2], NULL, 0);
2149 arm7_9->write_xpsr_im8(target, value, rotate, spsr);
2150 if ((retval = jtag_execute_queue()) != ERROR_OK)
2152 ERROR("JTAG error while writing 8-bit immediate to xpsr");
2159 int handle_arm7_9_write_core_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2164 target_t *target = get_current_target(cmd_ctx);
2165 armv4_5_common_t *armv4_5;
2166 arm7_9_common_t *arm7_9;
2168 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2170 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2174 if (target->state != TARGET_HALTED)
2176 command_print(cmd_ctx, "can't write registers while running");
2182 command_print(cmd_ctx, "usage: write_core_reg <num> <mode> <value>");
2186 num = strtol(args[0], NULL, 0);
2187 mode = strtoul(args[1], NULL, 0);
2188 value = strtoul(args[2], NULL, 0);
2190 arm7_9_write_core_reg(target, num, mode, value);
2195 int handle_arm7_9_sw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2197 target_t *target = get_current_target(cmd_ctx);
2198 armv4_5_common_t *armv4_5;
2199 arm7_9_common_t *arm7_9;
2201 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2203 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2209 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2213 if (strcmp("enable", args[0]) == 0)
2215 if (arm7_9->sw_bkpts_use_wp)
2217 arm7_9_enable_sw_bkpts(target);
2221 arm7_9->sw_bkpts_enabled = 1;
2224 else if (strcmp("disable", args[0]) == 0)
2226 if (arm7_9->sw_bkpts_use_wp)
2228 arm7_9_disable_sw_bkpts(target);
2232 arm7_9->sw_bkpts_enabled = 0;
2237 command_print(cmd_ctx, "usage: arm7_9 sw_bkpts <enable|disable>");
2240 command_print(cmd_ctx, "software breakpoints %s", (arm7_9->sw_bkpts_enabled) ? "enabled" : "disabled");
2245 int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2247 target_t *target = get_current_target(cmd_ctx);
2248 armv4_5_common_t *armv4_5;
2249 arm7_9_common_t *arm7_9;
2251 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2253 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2257 if ((argc >= 1) && (strcmp("enable", args[0]) == 0))
2259 arm7_9->force_hw_bkpts = 1;
2260 if (arm7_9->sw_bkpts_use_wp)
2262 arm7_9_disable_sw_bkpts(target);
2265 else if ((argc >= 1) && (strcmp("disable", args[0]) == 0))
2267 arm7_9->force_hw_bkpts = 0;
2271 command_print(cmd_ctx, "usage: arm7_9 force_hw_bkpts <enable|disable>");
2274 command_print(cmd_ctx, "force hardware breakpoints %s", (arm7_9->force_hw_bkpts) ? "enabled" : "disabled");
2279 int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2281 target_t *target = get_current_target(cmd_ctx);
2282 armv4_5_common_t *armv4_5;
2283 arm7_9_common_t *arm7_9;
2285 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2287 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2293 if (strcmp("enable", args[0]) == 0)
2295 arm7_9->use_dbgrq = 1;
2297 else if (strcmp("disable", args[0]) == 0)
2299 arm7_9->use_dbgrq = 0;
2303 command_print(cmd_ctx, "usage: arm7_9 dbgrq <enable|disable>");
2307 command_print(cmd_ctx, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
2312 int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2314 target_t *target = get_current_target(cmd_ctx);
2315 armv4_5_common_t *armv4_5;
2316 arm7_9_common_t *arm7_9;
2318 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2320 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2326 if (strcmp("enable", args[0]) == 0)
2328 arm7_9->fast_memory_access = 1;
2330 else if (strcmp("disable", args[0]) == 0)
2332 arm7_9->fast_memory_access = 0;
2336 command_print(cmd_ctx, "usage: arm7_9 fast_memory_access <enable|disable>");
2340 command_print(cmd_ctx, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
2345 int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
2347 target_t *target = get_current_target(cmd_ctx);
2348 armv4_5_common_t *armv4_5;
2349 arm7_9_common_t *arm7_9;
2351 if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
2353 command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
2359 if (strcmp("enable", args[0]) == 0)
2361 arm7_9->dcc_downloads = 1;
2363 else if (strcmp("disable", args[0]) == 0)
2365 arm7_9->dcc_downloads = 0;
2369 command_print(cmd_ctx, "usage: arm7_9 dcc_downloads <enable|disable>");
2373 command_print(cmd_ctx, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
2378 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
2380 armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
2382 arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
2384 arm_jtag_setup_connection(&arm7_9->jtag_info);
2385 arm7_9->wp_available = 2;
2386 arm7_9->wp0_used = 0;
2387 arm7_9->wp1_used = 0;
2388 arm7_9->force_hw_bkpts = 0;
2389 arm7_9->use_dbgrq = 0;
2390 arm7_9->has_etm = 0;
2392 arm7_9->reinit_embeddedice = 0;
2394 arm7_9->dcc_working_area = NULL;
2396 arm7_9->fast_memory_access = 0;
2397 arm7_9->dcc_downloads = 0;
2399 jtag_register_event_callback(arm7_9_jtag_callback, target);
2401 armv4_5->arch_info = arm7_9;
2402 armv4_5->read_core_reg = arm7_9_read_core_reg;
2403 armv4_5->write_core_reg = arm7_9_write_core_reg;
2404 armv4_5->full_context = arm7_9_full_context;
2406 armv4_5_init_arch_info(target, armv4_5);