]> git.sur5r.net Git - openocd/blob - src/target/arm7_9_common.h
fixed gaffe: disable interrupts reset init script
[openocd] / src / target / arm7_9_common.h
1 /***************************************************************************
2  *   Copyright (C) 2005 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   Copyright (C) 2007,2008 Ã˜yvind Harboe                                 *
6  *   oyvind.harboe@zylin.com                                               *
7  *                                                                         *
8  *   Copyright (C) 2008 by Spencer Oliver                                  *
9  *   spen@spen-soft.co.uk                                                  *
10  *                                                                         *
11  *   This program is free software; you can redistribute it and/or modify  *
12  *   it under the terms of the GNU General Public License as published by  *
13  *   the Free Software Foundation; either version 2 of the License, or     *
14  *   (at your option) any later version.                                   *
15  *                                                                         *
16  *   This program is distributed in the hope that it will be useful,       *
17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
19  *   GNU General Public License for more details.                          *
20  *                                                                         *
21  *   You should have received a copy of the GNU General Public License     *
22  *   along with this program; if not, write to the                         *
23  *   Free Software Foundation, Inc.,                                       *
24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
25  ***************************************************************************/
26 #ifndef ARM7_9_COMMON_H
27 #define ARM7_9_COMMON_H
28
29 #include "armv4_5.h"
30 #include "arm_jtag.h"
31 #include "breakpoints.h"
32 #include "target.h"
33
34 #include "etm.h"
35
36 #define ARM7_9_COMMON_MAGIC 0x0a790a79
37
38 typedef struct arm7_9_common_s
39 {
40         int common_magic;
41         
42         arm_jtag_t jtag_info;
43         reg_cache_t *eice_cache;
44         
45         u32 arm_bkpt;
46         u16 thumb_bkpt;
47         int sw_breakpoints_added;
48         int breakpoint_count;
49         int wp_available;
50         int wp_available_max;
51         int wp0_used;
52         int wp1_used;
53         int wp1_used_default;
54         int force_hw_bkpts;
55         int dbgreq_adjust_pc;
56         int use_dbgrq;
57         int need_bypass_before_restart;
58         
59         etm_context_t *etm_ctx;
60         
61         int has_single_step;
62         int has_monitor_mode;
63         int has_vector_catch;
64         
65         int debug_entry_from_reset;
66         
67         struct working_area_s *dcc_working_area;
68         
69         int fast_memory_access;
70         int dcc_downloads;
71
72         int (*examine_debug_reason)(target_t *target);
73         
74         void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
75         
76         void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
77         void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
78         void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
79         
80         void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
81         void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
82         void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
83         
84         void (*load_word_regs)(target_t *target, u32 mask);
85         void (*load_hword_reg)(target_t *target, int num);
86         void (*load_byte_reg)(target_t *target, int num);
87
88         void (*store_word_regs)(target_t *target, u32 mask);
89         void (*store_hword_reg)(target_t *target, int num);
90         void (*store_byte_reg)(target_t *target, int num);
91         
92         void (*write_pc)(target_t *target, u32 pc);
93         void (*branch_resume)(target_t *target);
94         void (*branch_resume_thumb)(target_t *target);
95         
96         void (*enable_single_step)(target_t *target);
97         void (*disable_single_step)(target_t *target);
98         
99         void (*set_special_dbgrq)(target_t *target);
100
101         void (*pre_debug_entry)(target_t *target);
102         void (*post_debug_entry)(target_t *target);
103         
104         void (*pre_restore_context)(target_t *target);
105         void (*post_restore_context)(target_t *target);
106         
107         armv4_5_common_t armv4_5_common;
108         void *arch_info;
109
110 } arm7_9_common_t;
111
112 int arm7_9_register_commands(struct command_context_s *cmd_ctx);
113
114 int arm7_9_poll(target_t *target);
115
116 int arm7_9_target_request_data(target_t *target, u32 size, u8 *buffer);
117
118 int arm7_9_setup(target_t *target);
119 int arm7_9_assert_reset(target_t *target);
120 int arm7_9_deassert_reset(target_t *target);
121 int arm7_9_reset_request_halt(target_t *target);
122 int arm7_9_early_halt(target_t *target);
123 int arm7_9_soft_reset_halt(struct target_s *target);
124 int arm7_9_prepare_reset_halt(struct target_s *target);
125
126 int arm7_9_halt(target_t *target);
127 int arm7_9_debug_entry(target_t *target);
128 int arm7_9_full_context(target_t *target);
129 int arm7_9_restore_context(target_t *target);
130 int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
131 int arm7_9_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
132 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
133 int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
134 int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
135 int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
136 int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum);
137 int arm7_9_blank_check_memory(struct target_s *target, u32 address, u32 count, u32* blank);
138
139 int arm7_9_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_prams, reg_param_t *reg_param, u32 entry_point, void *arch_info);
140
141 int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
142 int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
143 int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
144 int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
145
146 void arm7_9_enable_eice_step(target_t *target);
147 void arm7_9_disable_eice_step(target_t *target);
148
149 int arm7_9_execute_sys_speed(struct target_s *target);
150
151 int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9);
152 int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p);
153
154
155 #endif /* ARM7_9_COMMON_H */