git.sur5r.net Git - openocd/blob - src/target/arm920t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm920t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 0
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44
  45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm920t_quit();
  52 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size);
  53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  55 int arm920t_soft_reset_halt(struct target_s *target);
  56
  57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
  58
  59 target_type_t arm920t_target =
  60 {
  61         .name = "arm920t",
  62
  63         .poll = arm7_9_poll,
  64         .arch_state = arm920t_arch_state,
  65
  66         .target_request_data = arm7_9_target_request_data,
  67
  68         .halt = arm7_9_halt,
  69         .resume = arm7_9_resume,
  70         .step = arm7_9_step,
  71
  72         .assert_reset = arm7_9_assert_reset,
  73         .deassert_reset = arm7_9_deassert_reset,
  74         .soft_reset_halt = arm920t_soft_reset_halt,
  75         .prepare_reset_halt = arm7_9_prepare_reset_halt,
  76
  77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  78
  79         .read_memory = arm920t_read_memory,
  80         .write_memory = arm920t_write_memory,
  81         .bulk_write_memory = arm7_9_bulk_write_memory,
  82
  83         .run_algorithm = armv4_5_run_algorithm,
  84
  85         .add_breakpoint = arm7_9_add_breakpoint,
  86         .remove_breakpoint = arm7_9_remove_breakpoint,
  87         .add_watchpoint = arm7_9_add_watchpoint,
  88         .remove_watchpoint = arm7_9_remove_watchpoint,
  89
  90         .register_commands = arm920t_register_commands,
  91         .target_command = arm920t_target_command,
  92         .init_target = arm920t_init_target,
  93         .quit = arm920t_quit
  94 };
  95
  96 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
  97 {
  98         armv4_5_common_t *armv4_5 = target->arch_info;
  99         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 100         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 101         scan_field_t fields[4];
 102         u8 access_type_buf = 1;
 103         u8 reg_addr_buf = reg_addr & 0x3f;
 104         u8 nr_w_buf = 0;
 105
 106         jtag_add_end_state(TAP_RTI);
 107         arm_jtag_scann(jtag_info, 0xf);
 108         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 109
 110         fields[0].device = jtag_info->chain_pos;
 111         fields[0].num_bits = 1;
 112         fields[0].out_value = &access_type_buf;
 113         fields[0].out_mask = NULL;
 114         fields[0].in_value = NULL;
 115         fields[0].in_check_value = NULL;
 116         fields[0].in_check_mask = NULL;
 117         fields[0].in_handler = NULL;
 118         fields[0].in_handler_priv = NULL;
 119
 120         fields[1].device = jtag_info->chain_pos;
 121         fields[1].num_bits = 32;
 122         fields[1].out_value = NULL;
 123         fields[1].out_mask = NULL;
 124         fields[1].in_value = NULL;
 125         fields[1].in_check_value = NULL;
 126         fields[1].in_check_mask = NULL;
 127         fields[1].in_handler = NULL;
 128         fields[1].in_handler_priv = NULL;
 129
 130         fields[2].device = jtag_info->chain_pos;
 131         fields[2].num_bits = 6;
 132         fields[2].out_value = &reg_addr_buf;
 133         fields[2].out_mask = NULL;
 134         fields[2].in_value = NULL;
 135         fields[2].in_check_value = NULL;
 136         fields[2].in_check_mask = NULL;
 137         fields[2].in_handler = NULL;
 138         fields[2].in_handler_priv = NULL;
 139
 140         fields[3].device = jtag_info->chain_pos;
 141         fields[3].num_bits = 1;
 142         fields[3].out_value = &nr_w_buf;
 143         fields[3].out_mask = NULL;
 144         fields[3].in_value = NULL;
 145         fields[3].in_check_value = NULL;
 146         fields[3].in_check_mask = NULL;
 147         fields[3].in_handler = NULL;
 148         fields[3].in_handler_priv = NULL;
 149
 150         jtag_add_dr_scan(4, fields, -1, NULL);
 151
 152         fields[1].in_handler_priv = value;
 153         fields[1].in_handler = arm_jtag_buf_to_u32;
 154
 155         jtag_add_dr_scan(4, fields, -1, NULL);
 156
 157 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 158         jtag_execute_queue();
 159         DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
 160 #endif
 161
 162         return ERROR_OK;
 163 }
 164
 165 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 166 {
 167         armv4_5_common_t *armv4_5 = target->arch_info;
 168         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 169         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 170         scan_field_t fields[4];
 171         u8 access_type_buf = 1;
 172         u8 reg_addr_buf = reg_addr & 0x3f;
 173         u8 nr_w_buf = 1;
 174         u8 value_buf[4];
 175
 176         buf_set_u32(value_buf, 0, 32, value);
 177
 178         jtag_add_end_state(TAP_RTI);
 179         arm_jtag_scann(jtag_info, 0xf);
 180         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 181
 182         fields[0].device = jtag_info->chain_pos;
 183         fields[0].num_bits = 1;
 184         fields[0].out_value = &access_type_buf;
 185         fields[0].out_mask = NULL;
 186         fields[0].in_value = NULL;
 187         fields[0].in_check_value = NULL;
 188         fields[0].in_check_mask = NULL;
 189         fields[0].in_handler = NULL;
 190         fields[0].in_handler_priv = NULL;
 191
 192         fields[1].device = jtag_info->chain_pos;
 193         fields[1].num_bits = 32;
 194         fields[1].out_value = value_buf;
 195         fields[1].out_mask = NULL;
 196         fields[1].in_value = NULL;
 197         fields[1].in_check_value = NULL;
 198         fields[1].in_check_mask = NULL;
 199         fields[1].in_handler = NULL;
 200         fields[1].in_handler_priv = NULL;
 201
 202         fields[2].device = jtag_info->chain_pos;
 203         fields[2].num_bits = 6;
 204         fields[2].out_value = &reg_addr_buf;
 205         fields[2].out_mask = NULL;
 206         fields[2].in_value = NULL;
 207         fields[2].in_check_value = NULL;
 208         fields[2].in_check_mask = NULL;
 209         fields[2].in_handler = NULL;
 210         fields[2].in_handler_priv = NULL;
 211
 212         fields[3].device = jtag_info->chain_pos;
 213         fields[3].num_bits = 1;
 214         fields[3].out_value = &nr_w_buf;
 215         fields[3].out_mask = NULL;
 216         fields[3].in_value = NULL;
 217         fields[3].in_check_value = NULL;
 218         fields[3].in_check_mask = NULL;
 219         fields[3].in_handler = NULL;
 220         fields[3].in_handler_priv = NULL;
 221
 222         jtag_add_dr_scan(4, fields, -1, NULL);
 223
 224 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 225         DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
 226 #endif
 227
 228         return ERROR_OK;
 229 }
 230
 231 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 232 {
 233         armv4_5_common_t *armv4_5 = target->arch_info;
 234         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 235         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 236         scan_field_t fields[4];
 237         u8 access_type_buf = 0;         /* interpreted access */
 238         u8 reg_addr_buf = 0x0;
 239         u8 nr_w_buf = 0;
 240         u8 cp15_opcode_buf[4];
 241
 242         jtag_add_end_state(TAP_RTI);
 243         arm_jtag_scann(jtag_info, 0xf);
 244         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 245
 246         buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 247
 248         fields[0].device = jtag_info->chain_pos;
 249         fields[0].num_bits = 1;
 250         fields[0].out_value = &access_type_buf;
 251         fields[0].out_mask = NULL;
 252         fields[0].in_value = NULL;
 253         fields[0].in_check_value = NULL;
 254         fields[0].in_check_mask = NULL;
 255         fields[0].in_handler = NULL;
 256         fields[0].in_handler_priv = NULL;
 257
 258         fields[1].device = jtag_info->chain_pos;
 259         fields[1].num_bits = 32;
 260         fields[1].out_value = cp15_opcode_buf;
 261         fields[1].out_mask = NULL;
 262         fields[1].in_value = NULL;
 263         fields[1].in_check_value = NULL;
 264         fields[1].in_check_mask = NULL;
 265         fields[1].in_handler = NULL;
 266         fields[1].in_handler_priv = NULL;
 267
 268         fields[2].device = jtag_info->chain_pos;
 269         fields[2].num_bits = 6;
 270         fields[2].out_value = &reg_addr_buf;
 271         fields[2].out_mask = NULL;
 272         fields[2].in_value = NULL;
 273         fields[2].in_check_value = NULL;
 274         fields[2].in_check_mask = NULL;
 275         fields[2].in_handler = NULL;
 276         fields[2].in_handler_priv = NULL;
 277
 278         fields[3].device = jtag_info->chain_pos;
 279         fields[3].num_bits = 1;
 280         fields[3].out_value = &nr_w_buf;
 281         fields[3].out_mask = NULL;
 282         fields[3].in_value = NULL;
 283         fields[3].in_check_value = NULL;
 284         fields[3].in_check_mask = NULL;
 285         fields[3].in_handler = NULL;
 286         fields[3].in_handler_priv = NULL;
 287
 288         jtag_add_dr_scan(4, fields, -1, NULL);
 289
 290         arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
 291         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 292         arm7_9_execute_sys_speed(target);
 293
 294         if (jtag_execute_queue() != ERROR_OK)
 295         {
 296                 ERROR("failed executing JTAG queue, exiting");
 297                 exit(-1);
 298         }
 299
 300         return ERROR_OK;
 301 }
 302
 303 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
 304 {
 305         armv4_5_common_t *armv4_5 = target->arch_info;
 306         u32* regs_p[1];
 307         u32 regs[2];
 308         u32 cp15c15 = 0x0;
 309
 310         /* load address into R1 */
 311         regs[1] = address;
 312         arm9tdmi_write_core_regs(target, 0x2, regs);
 313
 314         /* read-modify-write CP15 test state register
 315         * to enable interpreted access mode */
 316         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 317         jtag_execute_queue();
 318         cp15c15 |= 1;   /* set interpret mode */
 319         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 320
 321         /* execute CP15 instruction and ARM load (reading from coprocessor) */
 322         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
 323
 324         /* disable interpreted access mode */
 325         cp15c15 &= ~1U; /* clear interpret mode */
 326         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 327
 328         /* retrieve value from R0 */
 329         regs_p[0] = value;
 330         arm9tdmi_read_core_regs(target, 0x1, regs_p);
 331         jtag_execute_queue();
 332
 333 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 334         DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
 335 #endif
 336
 337         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 338         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 339
 340         return ERROR_OK;
 341 }
 342
 343 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
 344 {
 345         u32 cp15c15 = 0x0;
 346         armv4_5_common_t *armv4_5 = target->arch_info;
 347         u32 regs[2];
 348
 349         /* load value, address into R0, R1 */
 350         regs[0] = value;
 351         regs[1] = address;
 352         arm9tdmi_write_core_regs(target, 0x3, regs);
 353
 354         /* read-modify-write CP15 test state register
 355         * to enable interpreted access mode */
 356         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 357         jtag_execute_queue();
 358         cp15c15 |= 1;   /* set interpret mode */
 359         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 360
 361         /* execute CP15 instruction and ARM store (writing to coprocessor) */
 362         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
 363
 364         /* disable interpreted access mode */
 365         cp15c15 &= ~1U; /* set interpret mode */
 366         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 367
 368 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 369         DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
 370 #endif
 371
 372         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 373         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 374
 375         return ERROR_OK;
 376 }
 377
 378 u32 arm920t_get_ttb(target_t *target)
 379 {
 380         int retval;
 381         u32 ttb = 0x0;
 382
 383         if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 384                 return retval;
 385
 386         return ttb;
 387 }
 388
 389 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 390 {
 391         u32 cp15_control;
 392
 393         /* read cp15 control register */
 394         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 395         jtag_execute_queue();
 396
 397         if (mmu)
 398                 cp15_control &= ~0x1U;
 399
 400         if (d_u_cache)
 401                 cp15_control &= ~0x4U;
 402
 403         if (i_cache)
 404                 cp15_control &= ~0x1000U;
 405
 406         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 407 }
 408
 409 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 410 {
 411         u32 cp15_control;
 412
 413         /* read cp15 control register */
 414         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 415         jtag_execute_queue();
 416
 417         if (mmu)
 418                 cp15_control |= 0x1U;
 419
 420         if (d_u_cache)
 421                 cp15_control |= 0x4U;
 422
 423         if (i_cache)
 424                 cp15_control |= 0x1000U;
 425
 426         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 427 }
 428
 429 void arm920t_post_debug_entry(target_t *target)
 430 {
 431         u32 cp15c15;
 432         armv4_5_common_t *armv4_5 = target->arch_info;
 433         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 434         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 435         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 436
 437         /* examine cp15 control reg */
 438         arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
 439         jtag_execute_queue();
 440         DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
 441
 442         if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 443         {
 444                 u32 cache_type_reg;
 445                 /* identify caches */
 446                 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
 447                 jtag_execute_queue();
 448                 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
 449         }
 450
 451         arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
 452         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 453         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 454
 455         /* save i/d fault status and address register */
 456         arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
 457         arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
 458         arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 459         arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 460
 461         DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
 462                 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 463
 464         if (arm920t->preserve_cache)
 465         {
 466                 /* read-modify-write CP15 test state register
 467                  * to disable I/D-cache linefills */
 468                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 469                 jtag_execute_queue();
 470                 cp15c15 |= 0x600;
 471                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 472         }
 473 }
 474
 475 void arm920t_pre_restore_context(target_t *target)
 476 {
 477         u32 cp15c15;
 478         armv4_5_common_t *armv4_5 = target->arch_info;
 479         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 480         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 481         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 482
 483         /* restore i/d fault status and address register */
 484         arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
 485         arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
 486         arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
 487         arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
 488
 489         /* read-modify-write CP15 test state register
 490         * to reenable I/D-cache linefills */
 491         if (arm920t->preserve_cache)
 492         {
 493                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 494                 jtag_execute_queue();
 495                 cp15c15 &= ~0x600U;
 496                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 497         }
 498 }
 499
 500 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
 501 {
 502         armv4_5_common_t *armv4_5 = target->arch_info;
 503         arm7_9_common_t *arm7_9;
 504         arm9tdmi_common_t *arm9tdmi;
 505         arm920t_common_t *arm920t;
 506
 507         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 508         {
 509                 return -1;
 510         }
 511
 512         arm7_9 = armv4_5->arch_info;
 513         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 514         {
 515                 return -1;
 516         }
 517
 518         arm9tdmi = arm7_9->arch_info;
 519         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 520         {
 521                 return -1;
 522         }
 523
 524         arm920t = arm9tdmi->arch_info;
 525         if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
 526         {
 527                 return -1;
 528         }
 529
 530         *armv4_5_p = armv4_5;
 531         *arm7_9_p = arm7_9;
 532         *arm9tdmi_p = arm9tdmi;
 533         *arm920t_p = arm920t;
 534
 535         return ERROR_OK;
 536 }
 537
 538 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
 539 {
 540         armv4_5_common_t *armv4_5 = target->arch_info;
 541         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 542         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 543         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 544
 545         char *state[] =
 546         {
 547                 "disabled", "enabled"
 548         };
 549
 550         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 551         {
 552                 ERROR("BUG: called for a non-ARMv4/5 target");
 553                 exit(-1);
 554         }
 555
 556         snprintf(buf, buf_size,
 557                         "target halted in %s state due to %s, current mode: %s\n"
 558                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 559                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 560                          armv4_5_state_strings[armv4_5->core_state],
 561                          target_debug_reason_strings[target->debug_reason],
 562                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 563                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 564                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 565                          state[arm920t->armv4_5_mmu.mmu_enabled],
 566                          state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 567                          state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 568
 569         return ERROR_OK;
 570 }
 571
 572 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 573 {
 574         int retval;
 575
 576         retval = arm7_9_read_memory(target, address, size, count, buffer);
 577
 578         return retval;
 579 }
 580
 581 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 582 {
 583         int retval;
 584         armv4_5_common_t *armv4_5 = target->arch_info;
 585         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 586         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 587         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 588
 589         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 590                 return retval;
 591
 592         if (((size == 4) || (size == 2)) && (count == 1))
 593         {
 594                 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 595                 {
 596                         DEBUG("D-Cache enabled, writing through to main memory");
 597                         u32 pa, cb, ap;
 598                         int type, domain;
 599
 600                         pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
 601                         if (type == -1)
 602                                 return ERROR_OK;
 603                         /* cacheable & bufferable means write-back region */
 604                         if (cb == 3)
 605                                 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
 606                 }
 607
 608                 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 609                 {
 610                         DEBUG("I-Cache enabled, invalidating affected I-Cache line");
 611                         arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
 612                 }
 613         }
 614
 615         return retval;
 616 }
 617
 618 int arm920t_soft_reset_halt(struct target_s *target)
 619 {
 620         armv4_5_common_t *armv4_5 = target->arch_info;
 621         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 622         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 623         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 624         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 625
 626         if (target->state == TARGET_RUNNING)
 627         {
 628                 target->type->halt(target);
 629         }
 630
 631         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 632         {
 633                 embeddedice_read_reg(dbg_stat);
 634                 jtag_execute_queue();
 635         }
 636
 637         target->state = TARGET_HALTED;
 638
 639         /* SVC, ARM state, IRQ and FIQ disabled */
 640         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 641         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 642         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 643
 644         /* start fetching from 0x0 */
 645         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 646         armv4_5->core_cache->reg_list[15].dirty = 1;
 647         armv4_5->core_cache->reg_list[15].valid = 1;
 648
 649         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 650         armv4_5->core_state = ARMV4_5_STATE_ARM;
 651
 652         arm920t_disable_mmu_caches(target, 1, 1, 1);
 653         arm920t->armv4_5_mmu.mmu_enabled = 0;
 654         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 655         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 656
 657         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 658
 659         return ERROR_OK;
 660 }
 661
 662 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 663 {
 664         arm9tdmi_init_target(cmd_ctx, target);
 665
 666         return ERROR_OK;
 667
 668 }
 669
 670 int arm920t_quit()
 671 {
 672
 673         return ERROR_OK;
 674 }
 675
 676 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
 677 {
 678         arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
 679         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 680
 681         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 682          */
 683         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 684
 685         arm9tdmi->arch_info = arm920t;
 686         arm920t->common_magic = ARM920T_COMMON_MAGIC;
 687
 688         arm7_9->post_debug_entry = arm920t_post_debug_entry;
 689         arm7_9->pre_restore_context = arm920t_pre_restore_context;
 690
 691         arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 692         arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
 693         arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 694         arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 695         arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 696         arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 697         arm920t->armv4_5_mmu.has_tiny_pages = 1;
 698         arm920t->armv4_5_mmu.mmu_enabled = 0;
 699
 700         /* disabling linefills leads to lockups, so keep them enabled for now
 701          * this doesn't affect correctness, but might affect timing issues, if
 702          * important data is evicted from the cache during the debug session
 703          * */
 704         arm920t->preserve_cache = 0;
 705
 706         /* override hw single-step capability from ARM9TDMI */
 707         arm7_9->has_single_step = 1;
 708
 709         return ERROR_OK;
 710 }
 711
 712 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 713 {
 714         int chain_pos;
 715         char *variant = NULL;
 716         arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
 717
 718         if (argc < 4)
 719         {
 720                 ERROR("'target arm920t' requires at least one additional argument");
 721                 exit(-1);
 722         }
 723
 724         chain_pos = strtoul(args[3], NULL, 0);
 725
 726         if (argc >= 5)
 727                 variant = args[4];
 728
 729         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 730
 731         arm920t_init_arch_info(target, arm920t, chain_pos, variant);
 732
 733         return ERROR_OK;
 734 }
 735
 736 int arm920t_register_commands(struct command_context_s *cmd_ctx)
 737 {
 738         int retval;
 739         command_t *arm920t_cmd;
 740
 741
 742         retval = arm9tdmi_register_commands(cmd_ctx);
 743
 744         arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
 745
 746         register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
 747         register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
 748         register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 749         register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 750
 751         register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 752         register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 753         register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 754
 755         register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 756         register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 757         register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 758
 759         register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
 760         register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
 761
 762         return ERROR_OK;
 763 }
 764
 765 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 766 {
 767         target_t *target = get_current_target(cmd_ctx);
 768         armv4_5_common_t *armv4_5;
 769         arm7_9_common_t *arm7_9;
 770         arm9tdmi_common_t *arm9tdmi;
 771         arm920t_common_t *arm920t;
 772         arm_jtag_t *jtag_info;
 773         u32 cp15c15;
 774         u32 cp15_ctrl, cp15_ctrl_saved;
 775         u32 regs[16];
 776         u32 *regs_p[16];
 777         u32 C15_C_D_Ind, C15_C_I_Ind;
 778         int i;
 779         FILE *output;
 780         arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
 781         int segment, index;
 782
 783         if (argc != 1)
 784         {
 785                 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
 786                 return ERROR_OK;
 787         }
 788
 789         if ((output = fopen(args[0], "w")) == NULL)
 790         {
 791                 DEBUG("error opening cache content file");
 792                 return ERROR_OK;
 793         }
 794
 795         for (i = 0; i < 16; i++)
 796                 regs_p[i] = &regs[i];
 797
 798         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 799         {
 800                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 801                 return ERROR_OK;
 802         }
 803
 804         jtag_info = &arm7_9->jtag_info;
 805
 806         /* disable MMU and Caches */
 807         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
 808         jtag_execute_queue();
 809         cp15_ctrl_saved = cp15_ctrl;
 810         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 811         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 812
 813         /* read CP15 test state register */
 814         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
 815         jtag_execute_queue();
 816
 817         /* read DCache content */
 818         fprintf(output, "DCache:\n");
 819
 820         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 821         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 822         {
 823                 fprintf(output, "\nsegment: %i\n----------", segment);
 824
 825                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 826                 regs[0] = 0x0 | (segment << 5);
 827                 arm9tdmi_write_core_regs(target, 0x1, regs);
 828
 829                 /* set interpret mode */
 830                 cp15c15 |= 0x1;
 831                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 832
 833                 /* D CAM Read, loads current victim into C15.C.D.Ind */
 834                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 835
 836                 /* read current victim */
 837                 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
 838
 839                 /* clear interpret mode */
 840                 cp15c15 &= ~0x1;
 841                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 842
 843                 for (index = 0; index < 64; index++)
 844                 {
 845                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 846                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 847                         arm9tdmi_write_core_regs(target, 0x1, regs);
 848
 849                         /* set interpret mode */
 850                         cp15c15 |= 0x1;
 851                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 852
 853                         /* Write DCache victim */
 854                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 855
 856                         /* Read D RAM */
 857                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 858
 859                         /* Read D CAM */
 860                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
 861
 862                         /* clear interpret mode */
 863                         cp15c15 &= ~0x1;
 864                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 865
 866                         /* read D RAM and CAM content */
 867                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 868                         jtag_execute_queue();
 869
 870                         d_cache[segment][index].cam = regs[9];
 871
 872                         /* mask LFSR[6] */
 873                         regs[9] &= 0xfffffffe;
 874                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 875
 876                         for (i = 1; i < 9; i++)
 877                         {
 878                                  d_cache[segment][index].data[i] = regs[i];
 879                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
 880                         }
 881
 882                 }
 883
 884                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 885                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 886                 arm9tdmi_write_core_regs(target, 0x1, regs);
 887
 888                 /* set interpret mode */
 889                 cp15c15 |= 0x1;
 890                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 891
 892                 /* Write DCache victim */
 893                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 894
 895                 /* clear interpret mode */
 896                 cp15c15 &= ~0x1;
 897                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 898         }
 899
 900         /* read ICache content */
 901         fprintf(output, "ICache:\n");
 902
 903         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 904         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 905         {
 906                 fprintf(output, "segment: %i\n----------", segment);
 907
 908                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 909                 regs[0] = 0x0 | (segment << 5);
 910                 arm9tdmi_write_core_regs(target, 0x1, regs);
 911
 912                 /* set interpret mode */
 913                 cp15c15 |= 0x1;
 914                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 915
 916                 /* I CAM Read, loads current victim into C15.C.I.Ind */
 917                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 918
 919                 /* read current victim */
 920                 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
 921
 922                 /* clear interpret mode */
 923                 cp15c15 &= ~0x1;
 924                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 925
 926                 for (index = 0; index < 64; index++)
 927                 {
 928                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 929                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 930                         arm9tdmi_write_core_regs(target, 0x1, regs);
 931
 932                         /* set interpret mode */
 933                         cp15c15 |= 0x1;
 934                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 935
 936                         /* Write ICache victim */
 937                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 938
 939                         /* Read I RAM */
 940                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 941
 942                         /* Read I CAM */
 943                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
 944
 945                         /* clear interpret mode */
 946                         cp15c15 &= ~0x1;
 947                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 948
 949                         /* read I RAM and CAM content */
 950                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 951                         jtag_execute_queue();
 952
 953                         i_cache[segment][index].cam = regs[9];
 954
 955                         /* mask LFSR[6] */
 956                         regs[9] &= 0xfffffffe;
 957                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 958
 959                         for (i = 1; i < 9; i++)
 960                         {
 961                                  i_cache[segment][index].data[i] = regs[i];
 962                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
 963                         }
 964
 965                 }
 966
 967
 968                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 969                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 970                 arm9tdmi_write_core_regs(target, 0x1, regs);
 971
 972                 /* set interpret mode */
 973                 cp15c15 |= 0x1;
 974                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 975
 976                 /* Write ICache victim */
 977                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 978
 979                 /* clear interpret mode */
 980                 cp15c15 &= ~0x1;
 981                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 982         }
 983
 984         /* restore CP15 MMU and Cache settings */
 985         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
 986
 987         command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
 988
 989         fclose(output);
 990
 991         /* mark registers dirty */
 992         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 993         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 994         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
 995         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
 996         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
 997         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
 998         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
 999         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
1000         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
1001         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
1002
1003         return ERROR_OK;
1004 }
1005
1006 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1007 {
1008         target_t *target = get_current_target(cmd_ctx);
1009         armv4_5_common_t *armv4_5;
1010         arm7_9_common_t *arm7_9;
1011         arm9tdmi_common_t *arm9tdmi;
1012         arm920t_common_t *arm920t;
1013         arm_jtag_t *jtag_info;
1014         u32 cp15c15;
1015         u32 cp15_ctrl, cp15_ctrl_saved;
1016         u32 regs[16];
1017         u32 *regs_p[16];
1018         int i;
1019         FILE *output;
1020         u32 Dlockdown, Ilockdown;
1021         arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1022         int victim;
1023
1024         if (argc != 1)
1025         {
1026                 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1027                 return ERROR_OK;
1028         }
1029
1030         if ((output = fopen(args[0], "w")) == NULL)
1031         {
1032                 DEBUG("error opening mmu content file");
1033                 return ERROR_OK;
1034         }
1035
1036         for (i = 0; i < 16; i++)
1037                 regs_p[i] = &regs[i];
1038
1039         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1040         {
1041                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1042                 return ERROR_OK;
1043         }
1044
1045         jtag_info = &arm7_9->jtag_info;
1046
1047         /* disable MMU and Caches */
1048         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1049         jtag_execute_queue();
1050         cp15_ctrl_saved = cp15_ctrl;
1051         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1052         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1053
1054         /* read CP15 test state register */
1055         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1056         jtag_execute_queue();
1057
1058         /* prepare reading D TLB content
1059          * */
1060
1061         /* set interpret mode */
1062         cp15c15 |= 0x1;
1063         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1064
1065         /* Read D TLB lockdown */
1066         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1067
1068         /* clear interpret mode */
1069         cp15c15 &= ~0x1;
1070         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1071
1072         /* read D TLB lockdown stored to r1 */
1073         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1074         jtag_execute_queue();
1075         Dlockdown = regs[1];
1076
1077         for (victim = 0; victim < 64; victim += 8)
1078         {
1079                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1080                  * base remains unchanged, victim goes through entries 0 to 63 */
1081                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1082                 arm9tdmi_write_core_regs(target, 0x2, regs);
1083
1084                 /* set interpret mode */
1085                 cp15c15 |= 0x1;
1086                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1087
1088                 /* Write D TLB lockdown */
1089                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1090
1091                 /* Read D TLB CAM */
1092                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1093
1094                 /* clear interpret mode */
1095                 cp15c15 &= ~0x1;
1096                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1097
1098                 /* read D TLB CAM content stored to r2-r9 */
1099                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1100                 jtag_execute_queue();
1101
1102                 for (i = 0; i < 8; i++)
1103                         d_tlb[victim + i].cam = regs[i + 2];
1104         }
1105
1106         for (victim = 0; victim < 64; victim++)
1107         {
1108                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1109                  * base remains unchanged, victim goes through entries 0 to 63 */
1110                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1111                 arm9tdmi_write_core_regs(target, 0x2, regs);
1112
1113                 /* set interpret mode */
1114                 cp15c15 |= 0x1;
1115                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1116
1117                 /* Write D TLB lockdown */
1118                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1119
1120                 /* Read D TLB RAM1 */
1121                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1122
1123                 /* Read D TLB RAM2 */
1124                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1125
1126                 /* clear interpret mode */
1127                 cp15c15 &= ~0x1;
1128                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1129
1130                 /* read D TLB RAM content stored to r2 and r3 */
1131                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1132                 jtag_execute_queue();
1133
1134                 d_tlb[victim].ram1 = regs[2];
1135                 d_tlb[victim].ram2 = regs[3];
1136         }
1137
1138         /* restore D TLB lockdown */
1139         regs[1] = Dlockdown;
1140         arm9tdmi_write_core_regs(target, 0x2, regs);
1141
1142         /* Write D TLB lockdown */
1143         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1144
1145         /* prepare reading I TLB content
1146          * */
1147
1148         /* set interpret mode */
1149         cp15c15 |= 0x1;
1150         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1151
1152         /* Read I TLB lockdown */
1153         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1154
1155         /* clear interpret mode */
1156         cp15c15 &= ~0x1;
1157         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1158
1159         /* read I TLB lockdown stored to r1 */
1160         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1161         jtag_execute_queue();
1162         Ilockdown = regs[1];
1163
1164         for (victim = 0; victim < 64; victim += 8)
1165         {
1166                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1167                  * base remains unchanged, victim goes through entries 0 to 63 */
1168                 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1169                 arm9tdmi_write_core_regs(target, 0x2, regs);
1170
1171                 /* set interpret mode */
1172                 cp15c15 |= 0x1;
1173                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1174
1175                 /* Write I TLB lockdown */
1176                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1177
1178                 /* Read I TLB CAM */
1179                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1180
1181                 /* clear interpret mode */
1182                 cp15c15 &= ~0x1;
1183                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1184
1185                 /* read I TLB CAM content stored to r2-r9 */
1186                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1187                 jtag_execute_queue();
1188
1189                 for (i = 0; i < 8; i++)
1190                         i_tlb[i + victim].cam = regs[i + 2];
1191         }
1192
1193         for (victim = 0; victim < 64; victim++)
1194         {
1195                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1196                  * base remains unchanged, victim goes through entries 0 to 63 */
1197                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1198                 arm9tdmi_write_core_regs(target, 0x2, regs);
1199
1200                 /* set interpret mode */
1201                 cp15c15 |= 0x1;
1202                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1203
1204                 /* Write I TLB lockdown */
1205                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1206
1207                 /* Read I TLB RAM1 */
1208                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1209
1210                 /* Read I TLB RAM2 */
1211                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1212
1213                 /* clear interpret mode */
1214                 cp15c15 &= ~0x1;
1215                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1216
1217                 /* read I TLB RAM content stored to r2 and r3 */
1218                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1219                 jtag_execute_queue();
1220
1221                 i_tlb[victim].ram1 = regs[2];
1222                 i_tlb[victim].ram2 = regs[3];
1223         }
1224
1225         /* restore I TLB lockdown */
1226         regs[1] = Ilockdown;
1227         arm9tdmi_write_core_regs(target, 0x2, regs);
1228
1229         /* Write I TLB lockdown */
1230         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1231
1232         /* restore CP15 MMU and Cache settings */
1233         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1234
1235         /* output data to file */
1236         fprintf(output, "D TLB content:\n");
1237         for (i = 0; i < 64; i++)
1238         {
1239                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1240         }
1241
1242         fprintf(output, "\n\nI TLB content:\n");
1243         for (i = 0; i < 64; i++)
1244         {
1245                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1246         }
1247
1248         command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1249
1250         fclose(output);
1251
1252         /* mark registers dirty */
1253         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1254         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
1255         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
1256         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
1257         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
1258         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
1259         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
1260         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
1261         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
1262         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
1263
1264         return ERROR_OK;
1265 }
1266 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1267 {
1268         int retval;
1269         target_t *target = get_current_target(cmd_ctx);
1270         armv4_5_common_t *armv4_5;
1271         arm7_9_common_t *arm7_9;
1272         arm9tdmi_common_t *arm9tdmi;
1273         arm920t_common_t *arm920t;
1274         arm_jtag_t *jtag_info;
1275
1276         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1277         {
1278                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1279                 return ERROR_OK;
1280         }
1281
1282         jtag_info = &arm7_9->jtag_info;
1283
1284         if (target->state != TARGET_HALTED)
1285         {
1286                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1287                 return ERROR_OK;
1288         }
1289
1290         /* one or more argument, access a single register (write if second argument is given */
1291         if (argc >= 1)
1292         {
1293                 int address = strtoul(args[0], NULL, 0);
1294
1295                 if (argc == 1)
1296                 {
1297                         u32 value;
1298                         if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1299                         {
1300                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1301                                 return ERROR_OK;
1302                         }
1303                         jtag_execute_queue();
1304
1305                         command_print(cmd_ctx, "%i: %8.8x", address, value);
1306                 }
1307                 else if (argc == 2)
1308                 {
1309                         u32 value = strtoul(args[1], NULL, 0);
1310                         if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1311                         {
1312                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1313                                 return ERROR_OK;
1314                         }
1315                         command_print(cmd_ctx, "%i: %8.8x", address, value);
1316                 }
1317         }
1318
1319         return ERROR_OK;
1320 }
1321
1322 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1323 {
1324         int retval;
1325         target_t *target = get_current_target(cmd_ctx);
1326         armv4_5_common_t *armv4_5;
1327         arm7_9_common_t *arm7_9;
1328         arm9tdmi_common_t *arm9tdmi;
1329         arm920t_common_t *arm920t;
1330         arm_jtag_t *jtag_info;
1331
1332         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1333         {
1334                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1335                 return ERROR_OK;
1336         }
1337
1338         jtag_info = &arm7_9->jtag_info;
1339
1340         if (target->state != TARGET_HALTED)
1341         {
1342                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1343                 return ERROR_OK;
1344         }
1345
1346         /* one or more argument, access a single register (write if second argument is given */
1347         if (argc >= 1)
1348         {
1349                 u32 opcode = strtoul(args[0], NULL, 0);
1350
1351                 if (argc == 1)
1352                 {
1353                         u32 value;
1354                         if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1355                         {
1356                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1357                                 return ERROR_OK;
1358                         }
1359
1360                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1361                 }
1362                 else if (argc == 2)
1363                 {
1364                         u32 value = strtoul(args[1], NULL, 0);
1365                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1366                         {
1367                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1368                                 return ERROR_OK;
1369                         }
1370                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1371                 }
1372                 else if (argc == 3)
1373                 {
1374                         u32 value = strtoul(args[1], NULL, 0);
1375                         u32 address = strtoul(args[2], NULL, 0);
1376                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1377                         {
1378                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1379                                 return ERROR_OK;
1380                         }
1381                         command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1382                 }
1383         }
1384         else
1385         {
1386                 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1387         }
1388
1389         return ERROR_OK;
1390 }
1391
1392 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1393 {
1394         target_t *target = get_current_target(cmd_ctx);
1395         armv4_5_common_t *armv4_5;
1396         arm7_9_common_t *arm7_9;
1397         arm9tdmi_common_t *arm9tdmi;
1398         arm920t_common_t *arm920t;
1399
1400         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1401         {
1402                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1403                 return ERROR_OK;
1404         }
1405
1406         return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1407 }
1408
1409 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1410 {
1411         target_t *target = get_current_target(cmd_ctx);
1412         armv4_5_common_t *armv4_5;
1413         arm7_9_common_t *arm7_9;
1414         arm9tdmi_common_t *arm9tdmi;
1415         arm920t_common_t *arm920t;
1416         arm_jtag_t *jtag_info;
1417
1418         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1419         {
1420                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1421                 return ERROR_OK;
1422         }
1423
1424         jtag_info = &arm7_9->jtag_info;
1425
1426         if (target->state != TARGET_HALTED)
1427         {
1428                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1429                 return ERROR_OK;
1430         }
1431
1432         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1433 }
1434
1435 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1436 {
1437         target_t *target = get_current_target(cmd_ctx);
1438         armv4_5_common_t *armv4_5;
1439         arm7_9_common_t *arm7_9;
1440         arm9tdmi_common_t *arm9tdmi;
1441         arm920t_common_t *arm920t;
1442         arm_jtag_t *jtag_info;
1443
1444         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1445         {
1446                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1447                 return ERROR_OK;
1448         }
1449
1450         jtag_info = &arm7_9->jtag_info;
1451
1452         if (target->state != TARGET_HALTED)
1453         {
1454                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1455                 return ERROR_OK;
1456         }
1457
1458         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1459 }
1460
1461 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1462 {
1463         target_t *target = get_current_target(cmd_ctx);
1464         armv4_5_common_t *armv4_5;
1465         arm7_9_common_t *arm7_9;
1466         arm9tdmi_common_t *arm9tdmi;
1467         arm920t_common_t *arm920t;
1468         arm_jtag_t *jtag_info;
1469
1470         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1471         {
1472                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1473                 return ERROR_OK;
1474         }
1475
1476         jtag_info = &arm7_9->jtag_info;
1477
1478         if (target->state != TARGET_HALTED)
1479         {
1480                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1481                 return ERROR_OK;
1482         }
1483
1484         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1485 }