git.sur5r.net Git - openocd/blob - src/target/arm920t.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm920t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 0
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44
  45 /* forward declarations */
  46 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  47 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  48 int arm920t_quit();
  49 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size);
  50 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  51 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  52 int arm920t_soft_reset_halt(struct target_s *target);
  53
  54 target_type_t arm920t_target =
  55 {
  56         .name = "arm920t",
  57
  58         .poll = arm7_9_poll,
  59         .arch_state = arm920t_arch_state,
  60
  61         .halt = arm7_9_halt,
  62         .resume = arm7_9_resume,
  63         .step = arm7_9_step,
  64
  65         .assert_reset = arm7_9_assert_reset,
  66         .deassert_reset = arm7_9_deassert_reset,
  67         .soft_reset_halt = arm920t_soft_reset_halt,
  68
  69         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  70
  71         .read_memory = arm920t_read_memory,
  72         .write_memory = arm920t_write_memory,
  73         .bulk_write_memory = arm7_9_bulk_write_memory,
  74
  75         .run_algorithm = armv4_5_run_algorithm,
  76
  77         .add_breakpoint = arm7_9_add_breakpoint,
  78         .remove_breakpoint = arm7_9_remove_breakpoint,
  79         .add_watchpoint = arm7_9_add_watchpoint,
  80         .remove_watchpoint = arm7_9_remove_watchpoint,
  81
  82         .register_commands = arm920t_register_commands,
  83         .target_command = arm920t_target_command,
  84         .init_target = arm920t_init_target,
  85         .quit = arm920t_quit
  86 };
  87
  88 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
  89 {
  90         armv4_5_common_t *armv4_5 = target->arch_info;
  91         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  92         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  93         scan_field_t fields[4];
  94         u8 access_type_buf = 1;
  95         u8 reg_addr_buf = reg_addr & 0x3f;
  96         u8 nr_w_buf = 0;
  97
  98         jtag_add_end_state(TAP_RTI);
  99         arm_jtag_scann(jtag_info, 0xf);
 100         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 101
 102         fields[0].device = jtag_info->chain_pos;
 103         fields[0].num_bits = 1;
 104         fields[0].out_value = &access_type_buf;
 105         fields[0].out_mask = NULL;
 106         fields[0].in_value = NULL;
 107         fields[0].in_check_value = NULL;
 108         fields[0].in_check_mask = NULL;
 109         fields[0].in_handler = NULL;
 110         fields[0].in_handler_priv = NULL;
 111
 112         fields[1].device = jtag_info->chain_pos;
 113         fields[1].num_bits = 32;
 114         fields[1].out_value = NULL;
 115         fields[1].out_mask = NULL;
 116         fields[1].in_value = NULL;
 117         fields[1].in_check_value = NULL;
 118         fields[1].in_check_mask = NULL;
 119         fields[1].in_handler = NULL;
 120         fields[1].in_handler_priv = NULL;
 121
 122         fields[2].device = jtag_info->chain_pos;
 123         fields[2].num_bits = 6;
 124         fields[2].out_value = &reg_addr_buf;
 125         fields[2].out_mask = NULL;
 126         fields[2].in_value = NULL;
 127         fields[2].in_check_value = NULL;
 128         fields[2].in_check_mask = NULL;
 129         fields[2].in_handler = NULL;
 130         fields[2].in_handler_priv = NULL;
 131
 132         fields[3].device = jtag_info->chain_pos;
 133         fields[3].num_bits = 1;
 134         fields[3].out_value = &nr_w_buf;
 135         fields[3].out_mask = NULL;
 136         fields[3].in_value = NULL;
 137         fields[3].in_check_value = NULL;
 138         fields[3].in_check_mask = NULL;
 139         fields[3].in_handler = NULL;
 140         fields[3].in_handler_priv = NULL;
 141
 142         jtag_add_dr_scan(4, fields, -1);
 143
 144         fields[1].in_value = (u8*)value;
 145
 146         jtag_add_dr_scan(4, fields, -1);
 147
 148         return ERROR_OK;
 149 }
 150
 151 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 152 {
 153         armv4_5_common_t *armv4_5 = target->arch_info;
 154         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 155         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 156         scan_field_t fields[4];
 157         u8 access_type_buf = 1;
 158         u8 reg_addr_buf = reg_addr & 0x3f;
 159         u8 nr_w_buf = 1;
 160
 161         jtag_add_end_state(TAP_RTI);
 162         arm_jtag_scann(jtag_info, 0xf);
 163         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 164
 165         fields[0].device = jtag_info->chain_pos;
 166         fields[0].num_bits = 1;
 167         fields[0].out_value = &access_type_buf;
 168         fields[0].out_mask = NULL;
 169         fields[0].in_value = NULL;
 170         fields[0].in_check_value = NULL;
 171         fields[0].in_check_mask = NULL;
 172         fields[0].in_handler = NULL;
 173         fields[0].in_handler_priv = NULL;
 174
 175         fields[1].device = jtag_info->chain_pos;
 176         fields[1].num_bits = 32;
 177         fields[1].out_value = (u8*)&value;
 178         fields[1].out_mask = NULL;
 179         fields[1].in_value = NULL;
 180         fields[1].in_check_value = NULL;
 181         fields[1].in_check_mask = NULL;
 182         fields[1].in_handler = NULL;
 183         fields[1].in_handler_priv = NULL;
 184
 185         fields[2].device = jtag_info->chain_pos;
 186         fields[2].num_bits = 6;
 187         fields[2].out_value = &reg_addr_buf;
 188         fields[2].out_mask = NULL;
 189         fields[2].in_value = NULL;
 190         fields[2].in_check_value = NULL;
 191         fields[2].in_check_mask = NULL;
 192         fields[2].in_handler = NULL;
 193         fields[2].in_handler_priv = NULL;
 194
 195         fields[3].device = jtag_info->chain_pos;
 196         fields[3].num_bits = 1;
 197         fields[3].out_value = &nr_w_buf;
 198         fields[3].out_mask = NULL;
 199         fields[3].in_value = NULL;
 200         fields[3].in_check_value = NULL;
 201         fields[3].in_check_mask = NULL;
 202         fields[3].in_handler = NULL;
 203         fields[3].in_handler_priv = NULL;
 204
 205         jtag_add_dr_scan(4, fields, -1);
 206
 207         return ERROR_OK;
 208 }
 209
 210 int arm920t_read_cp15_interpreted(target_t *target, u32 opcode, u32 *value)
 211 {
 212         u32 cp15c15 = 0x0;
 213         scan_field_t fields[4];
 214         u8 access_type_buf = 0;         /* interpreted access */
 215         u8 reg_addr_buf = 0x0;
 216         u8 nr_w_buf = 0;
 217         armv4_5_common_t *armv4_5 = target->arch_info;
 218         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 219         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 220         u32* context_p[1];
 221
 222         /* read-modify-write CP15 test state register
 223         * to enable interpreted access mode */
 224         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 225         jtag_execute_queue();
 226         cp15c15 |= 1;   /* set interpret mode */
 227         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 228
 229         jtag_add_end_state(TAP_RTI);
 230         arm_jtag_scann(jtag_info, 0xf);
 231         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 232
 233         fields[0].device = jtag_info->chain_pos;
 234         fields[0].num_bits = 1;
 235         fields[0].out_value = &access_type_buf;
 236         fields[0].out_mask = NULL;
 237         fields[0].in_value = NULL;
 238         fields[0].in_check_value = NULL;
 239         fields[0].in_check_mask = NULL;
 240         fields[0].in_handler = NULL;
 241         fields[0].in_handler_priv = NULL;
 242
 243         fields[1].device = jtag_info->chain_pos;
 244         fields[1].num_bits = 32;
 245         fields[1].out_value = (u8*)&opcode;
 246         fields[1].out_mask = NULL;
 247         fields[1].in_value = NULL;
 248         fields[1].in_check_value = NULL;
 249         fields[1].in_check_mask = NULL;
 250         fields[1].in_handler = NULL;
 251         fields[1].in_handler_priv = NULL;
 252
 253         fields[2].device = jtag_info->chain_pos;
 254         fields[2].num_bits = 6;
 255         fields[2].out_value = &reg_addr_buf;
 256         fields[2].out_mask = NULL;
 257         fields[2].in_value = NULL;
 258         fields[2].in_check_value = NULL;
 259         fields[2].in_check_mask = NULL;
 260         fields[2].in_handler = NULL;
 261         fields[2].in_handler_priv = NULL;
 262
 263         fields[3].device = jtag_info->chain_pos;
 264         fields[3].num_bits = 1;
 265         fields[3].out_value = &nr_w_buf;
 266         fields[3].out_mask = NULL;
 267         fields[3].in_value = NULL;
 268         fields[3].in_check_value = NULL;
 269         fields[3].in_check_mask = NULL;
 270         fields[3].in_handler = NULL;
 271         fields[3].in_handler_priv = NULL;
 272
 273         jtag_add_dr_scan(4, fields, -1);
 274
 275         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDR(0, 15), 0, NULL, 0);
 276         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 277         arm7_9_execute_sys_speed(target);
 278         jtag_execute_queue();
 279
 280         /* read-modify-write CP15 test state register
 281         * to disable interpreted access mode */
 282         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 283         jtag_execute_queue();
 284         cp15c15 &= ~1U; /* clear interpret mode */
 285         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 286
 287         context_p[0] = value;
 288         arm9tdmi_read_core_regs(target, 0x1, context_p);
 289         jtag_execute_queue();
 290
 291         DEBUG("opcode: %8.8x, value: %8.8x", opcode, *value);
 292
 293         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 294         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = 1;
 295
 296         return ERROR_OK;
 297 }
 298
 299 int arm920t_write_cp15_interpreted(target_t *target, u32 opcode, u32 value, u32 address)
 300 {
 301         u32 cp15c15 = 0x0;
 302         scan_field_t fields[4];
 303         u8 access_type_buf = 0;         /* interpreted access */
 304         u8 reg_addr_buf = 0x0;
 305         u8 nr_w_buf = 0;
 306         armv4_5_common_t *armv4_5 = target->arch_info;
 307         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 308         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 309         u32 regs[2];
 310
 311         regs[0] = value;
 312         regs[1] = address;
 313
 314         arm9tdmi_write_core_regs(target, 0x3, regs);
 315
 316         /* read-modify-write CP15 test state register
 317         * to enable interpreted access mode */
 318         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 319         jtag_execute_queue();
 320         cp15c15 |= 1;   /* set interpret mode */
 321         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 322
 323         jtag_add_end_state(TAP_RTI);
 324         arm_jtag_scann(jtag_info, 0xf);
 325         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 326
 327         fields[0].device = jtag_info->chain_pos;
 328         fields[0].num_bits = 1;
 329         fields[0].out_value = &access_type_buf;
 330         fields[0].out_mask = NULL;
 331         fields[0].in_value = NULL;
 332         fields[0].in_check_value = NULL;
 333         fields[0].in_check_mask = NULL;
 334         fields[0].in_handler = NULL;
 335         fields[0].in_handler_priv = NULL;
 336
 337         fields[1].device = jtag_info->chain_pos;
 338         fields[1].num_bits = 32;
 339         fields[1].out_value = (u8*)&opcode;
 340         fields[1].out_mask = NULL;
 341         fields[1].in_value = NULL;
 342         fields[1].in_check_value = NULL;
 343         fields[1].in_check_mask = NULL;
 344         fields[1].in_handler = NULL;
 345         fields[1].in_handler_priv = NULL;
 346
 347         fields[2].device = jtag_info->chain_pos;
 348         fields[2].num_bits = 6;
 349         fields[2].out_value = &reg_addr_buf;
 350         fields[2].out_mask = NULL;
 351         fields[2].in_value = NULL;
 352         fields[2].in_check_value = NULL;
 353         fields[2].in_check_mask = NULL;
 354         fields[2].in_handler = NULL;
 355         fields[2].in_handler_priv = NULL;
 356
 357         fields[3].device = jtag_info->chain_pos;
 358         fields[3].num_bits = 1;
 359         fields[3].out_value = &nr_w_buf;
 360         fields[3].out_mask = NULL;
 361         fields[3].in_value = NULL;
 362         fields[3].in_check_value = NULL;
 363         fields[3].in_check_mask = NULL;
 364         fields[3].in_handler = NULL;
 365         fields[3].in_handler_priv = NULL;
 366
 367         jtag_add_dr_scan(4, fields, -1);
 368
 369         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 1), 0, NULL, 0);
 370         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 371         arm7_9_execute_sys_speed(target);
 372         jtag_execute_queue();
 373
 374         /* read-modify-write CP15 test state register
 375         * to disable interpreted access mode */
 376         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 377         jtag_execute_queue();
 378         cp15c15 &= ~1U; /* set interpret mode */
 379         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 380
 381         DEBUG("opcode: %8.8x, value: %8.8x, address: %8.8x", opcode, value, address);
 382
 383         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 384         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 385
 386         return ERROR_OK;
 387 }
 388
 389 u32 arm920t_get_ttb(target_t *target)
 390 {
 391         int retval;
 392         u32 ttb = 0x0;
 393
 394         if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, &ttb)) != ERROR_OK)
 395                 return retval;
 396
 397         return ttb;
 398 }
 399
 400 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 401 {
 402         u32 cp15_control;
 403
 404         /* read cp15 control register */
 405         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 406         jtag_execute_queue();
 407
 408         if (mmu)
 409                 cp15_control &= ~0x1U;
 410
 411         if (d_u_cache)
 412                 cp15_control &= ~0x4U;
 413
 414         if (i_cache)
 415                 cp15_control &= ~0x1000U;
 416
 417         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 418 }
 419
 420 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 421 {
 422         u32 cp15_control;
 423
 424         /* read cp15 control register */
 425         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 426         jtag_execute_queue();
 427
 428         if (mmu)
 429                 cp15_control |= 0x1U;
 430
 431         if (d_u_cache)
 432                 cp15_control |= 0x4U;
 433
 434         if (i_cache)
 435                 cp15_control |= 0x1000U;
 436
 437         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 438 }
 439
 440 void arm920t_post_debug_entry(target_t *target)
 441 {
 442         u32 cp15c15;
 443         armv4_5_common_t *armv4_5 = target->arch_info;
 444         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 445         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 446         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 447
 448         /* examine cp15 control reg */
 449         arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
 450         jtag_execute_queue();
 451         DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
 452
 453         if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 454         {
 455                 u32 cache_type_reg;
 456                 /* identify caches */
 457                 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
 458                 jtag_execute_queue();
 459                 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
 460         }
 461
 462         arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
 463         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 464         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 465
 466         /* save i/d fault status and address register */
 467         arm920t_read_cp15_interpreted(target, 0xee150f10, &arm920t->d_fsr);
 468         arm920t_read_cp15_interpreted(target, 0xee150f30, &arm920t->i_fsr);
 469         arm920t_read_cp15_interpreted(target, 0xee160f10, &arm920t->d_far);
 470         arm920t_read_cp15_interpreted(target, 0xee160f30, &arm920t->i_far);
 471
 472         /* read-modify-write CP15 test state register
 473         * to disable I/D-cache linefills */
 474         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 475         jtag_execute_queue();
 476         cp15c15 |= 0x600;
 477         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 478
 479 }
 480
 481 void arm920t_pre_restore_context(target_t *target)
 482 {
 483         u32 cp15c15;
 484         armv4_5_common_t *armv4_5 = target->arch_info;
 485         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 486         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 487         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 488
 489         /* restore i/d fault status and address register */
 490         arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
 491         arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
 492         arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
 493         arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
 494
 495         /* read-modify-write CP15 test state register
 496         * to reenable I/D-cache linefills */
 497         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 498         jtag_execute_queue();
 499         cp15c15 &= ~0x600U;
 500         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 501
 502 }
 503
 504 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
 505 {
 506         armv4_5_common_t *armv4_5 = target->arch_info;
 507         arm7_9_common_t *arm7_9;
 508         arm9tdmi_common_t *arm9tdmi;
 509         arm920t_common_t *arm920t;
 510
 511         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 512         {
 513                 return -1;
 514         }
 515
 516         arm7_9 = armv4_5->arch_info;
 517         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 518         {
 519                 return -1;
 520         }
 521
 522         arm9tdmi = arm7_9->arch_info;
 523         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 524         {
 525                 return -1;
 526         }
 527
 528         arm920t = arm9tdmi->arch_info;
 529         if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
 530         {
 531                 return -1;
 532         }
 533
 534         *armv4_5_p = armv4_5;
 535         *arm7_9_p = arm7_9;
 536         *arm9tdmi_p = arm9tdmi;
 537         *arm920t_p = arm920t;
 538
 539         return ERROR_OK;
 540 }
 541
 542 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
 543 {
 544         armv4_5_common_t *armv4_5 = target->arch_info;
 545         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 546         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 547         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 548
 549         char *state[] =
 550         {
 551                 "disabled", "enabled"
 552         };
 553
 554         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 555         {
 556                 ERROR("BUG: called for a non-ARMv4/5 target");
 557                 exit(-1);
 558         }
 559
 560         snprintf(buf, buf_size,
 561                         "target halted in %s state due to %s, current mode: %s\n"
 562                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 563                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 564                          armv4_5_state_strings[armv4_5->core_state],
 565                          target_debug_reason_strings[target->debug_reason],
 566                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 567                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 568                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 569                          state[arm920t->armv4_5_mmu.mmu_enabled],
 570                          state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 571                          state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 572
 573         return ERROR_OK;
 574 }
 575
 576 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 577 {
 578         int retval;
 579
 580         retval = arm7_9_read_memory(target, address, size, count, buffer);
 581
 582         return retval;
 583 }
 584
 585 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 586 {
 587         int retval;
 588         armv4_5_common_t *armv4_5 = target->arch_info;
 589         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 590         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 591         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 592
 593         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 594                 return retval;
 595
 596         if (((size == 4) || (size == 2)) && (count == 1))
 597         {
 598                 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 599                 {
 600                         DEBUG("D-Cache enabled, writing through to main memory");
 601                         u32 pa, cb, ap;
 602                         int type, domain;
 603
 604                         pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
 605                         if (type == -1)
 606                                 return ERROR_OK;
 607                         /* cacheable & bufferable means write-back region */
 608                         if (cb == 3)
 609                                 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
 610                 }
 611
 612                 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 613                 {
 614                         DEBUG("I-Cache enabled, invalidating affected I-Cache line");
 615                         arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
 616                 }
 617         }
 618
 619         return retval;
 620 }
 621
 622 int arm920t_soft_reset_halt(struct target_s *target)
 623 {
 624         armv4_5_common_t *armv4_5 = target->arch_info;
 625         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 626         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 627         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 628         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 629
 630         if (target->state == TARGET_RUNNING)
 631         {
 632                 target->type->halt(target);
 633         }
 634
 635         while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
 636         {
 637                 embeddedice_read_reg(dbg_stat);
 638                 jtag_execute_queue();
 639         }
 640
 641         target->state = TARGET_HALTED;
 642
 643         /* SVC, ARM state, IRQ and FIQ disabled */
 644         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 645         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 646         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 647
 648         /* start fetching from 0x0 */
 649         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 650         armv4_5->core_cache->reg_list[15].dirty = 1;
 651         armv4_5->core_cache->reg_list[15].valid = 1;
 652
 653         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 654         armv4_5->core_state = ARMV4_5_STATE_ARM;
 655
 656         arm920t_disable_mmu_caches(target, 1, 1, 1);
 657         arm920t->armv4_5_mmu.mmu_enabled = 0;
 658         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 659         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 660
 661         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 662
 663         return ERROR_OK;
 664 }
 665
 666 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 667 {
 668         arm9tdmi_init_target(cmd_ctx, target);
 669
 670         return ERROR_OK;
 671
 672 }
 673
 674 int arm920t_quit()
 675 {
 676
 677         return ERROR_OK;
 678 }
 679
 680 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
 681 {
 682         arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
 683         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 684
 685         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 686
 687         arm9tdmi->arch_info = arm920t;
 688         arm920t->common_magic = ARM920T_COMMON_MAGIC;
 689
 690         arm7_9->post_debug_entry = arm920t_post_debug_entry;
 691         arm7_9->pre_restore_context = arm920t_pre_restore_context;
 692
 693         arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 694         arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
 695         arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 696         arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 697         arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 698         arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 699         arm920t->armv4_5_mmu.has_tiny_pages = 1;
 700         arm920t->armv4_5_mmu.mmu_enabled = 0;
 701
 702         arm9tdmi->has_single_step = 1;
 703
 704         return ERROR_OK;
 705 }
 706
 707 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 708 {
 709         int chain_pos;
 710         char *variant = NULL;
 711         arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
 712
 713         if (argc < 4)
 714         {
 715                 ERROR("'target arm920t' requires at least one additional argument");
 716                 exit(-1);
 717         }
 718
 719         chain_pos = strtoul(args[3], NULL, 0);
 720
 721         if (argc >= 5)
 722                 variant = args[4];
 723
 724         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 725
 726         arm920t_init_arch_info(target, arm920t, chain_pos, variant);
 727
 728         return ERROR_OK;
 729 }
 730
 731 int arm920t_register_commands(struct command_context_s *cmd_ctx)
 732 {
 733         int retval;
 734         command_t *arm920t_cmd;
 735
 736
 737         retval = arm9tdmi_register_commands(cmd_ctx);
 738
 739         arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
 740
 741         register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
 742         register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
 743         register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 744         register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 745
 746         register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 747         register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 748         register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 749
 750         register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 751         register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 752         register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 753
 754         return ERROR_OK;
 755 }
 756
 757 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 758 {
 759         int retval;
 760         target_t *target = get_current_target(cmd_ctx);
 761         armv4_5_common_t *armv4_5;
 762         arm7_9_common_t *arm7_9;
 763         arm9tdmi_common_t *arm9tdmi;
 764         arm920t_common_t *arm920t;
 765         arm_jtag_t *jtag_info;
 766
 767         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 768         {
 769                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 770                 return ERROR_OK;
 771         }
 772
 773         jtag_info = &arm7_9->jtag_info;
 774
 775         if (target->state != TARGET_HALTED)
 776         {
 777                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 778                 return ERROR_OK;
 779         }
 780
 781         /* one or more argument, access a single register (write if second argument is given */
 782         if (argc >= 1)
 783         {
 784                 int address = strtoul(args[0], NULL, 0);
 785
 786                 if (argc == 1)
 787                 {
 788                         u32 value;
 789                         if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
 790                         {
 791                                 command_print(cmd_ctx, "couldn't access reg %i", address);
 792                                 return ERROR_OK;
 793                         }
 794                         jtag_execute_queue();
 795
 796                         command_print(cmd_ctx, "%i: %8.8x", address, value);
 797                 }
 798                 else if (argc == 2)
 799                 {
 800                         u32 value = strtoul(args[1], NULL, 0);
 801                         if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
 802                         {
 803                                 command_print(cmd_ctx, "couldn't access reg %i", address);
 804                                 return ERROR_OK;
 805                         }
 806                         command_print(cmd_ctx, "%i: %8.8x", address, value);
 807                 }
 808         }
 809
 810         return ERROR_OK;
 811 }
 812
 813 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 814 {
 815         int retval;
 816         target_t *target = get_current_target(cmd_ctx);
 817         armv4_5_common_t *armv4_5;
 818         arm7_9_common_t *arm7_9;
 819         arm9tdmi_common_t *arm9tdmi;
 820         arm920t_common_t *arm920t;
 821         arm_jtag_t *jtag_info;
 822
 823         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 824         {
 825                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 826                 return ERROR_OK;
 827         }
 828
 829         jtag_info = &arm7_9->jtag_info;
 830
 831         if (target->state != TARGET_HALTED)
 832         {
 833                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 834                 return ERROR_OK;
 835         }
 836
 837         /* one or more argument, access a single register (write if second argument is given */
 838         if (argc >= 1)
 839         {
 840                 u32 opcode = strtoul(args[0], NULL, 0);
 841
 842                 if (argc == 1)
 843                 {
 844                         u32 value;
 845                         if ((retval = arm920t_read_cp15_interpreted(target, opcode, &value)) != ERROR_OK)
 846                         {
 847                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
 848                                 return ERROR_OK;
 849                         }
 850
 851                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
 852                 }
 853                 else if (argc == 2)
 854                 {
 855                         u32 value = strtoul(args[1], NULL, 0);
 856                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
 857                         {
 858                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
 859                                 return ERROR_OK;
 860                         }
 861                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
 862                 }
 863                 else if (argc == 3)
 864                 {
 865                         u32 value = strtoul(args[1], NULL, 0);
 866                         u32 address = strtoul(args[2], NULL, 0);
 867                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
 868                         {
 869                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
 870                                 return ERROR_OK;
 871                         }
 872                         command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
 873                 }
 874         }
 875
 876         return ERROR_OK;
 877 }
 878
 879 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 880 {
 881         target_t *target = get_current_target(cmd_ctx);
 882         armv4_5_common_t *armv4_5;
 883         arm7_9_common_t *arm7_9;
 884         arm9tdmi_common_t *arm9tdmi;
 885         arm920t_common_t *arm920t;
 886
 887         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 888         {
 889                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 890                 return ERROR_OK;
 891         }
 892
 893         return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
 894 }
 895
 896 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 897 {
 898         target_t *target = get_current_target(cmd_ctx);
 899         armv4_5_common_t *armv4_5;
 900         arm7_9_common_t *arm7_9;
 901         arm9tdmi_common_t *arm9tdmi;
 902         arm920t_common_t *arm920t;
 903         arm_jtag_t *jtag_info;
 904
 905         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 906         {
 907                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 908                 return ERROR_OK;
 909         }
 910
 911         jtag_info = &arm7_9->jtag_info;
 912
 913         if (target->state != TARGET_HALTED)
 914         {
 915                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 916                 return ERROR_OK;
 917         }
 918
 919         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
 920 }
 921
 922 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 923 {
 924         target_t *target = get_current_target(cmd_ctx);
 925         armv4_5_common_t *armv4_5;
 926         arm7_9_common_t *arm7_9;
 927         arm9tdmi_common_t *arm9tdmi;
 928         arm920t_common_t *arm920t;
 929         arm_jtag_t *jtag_info;
 930
 931         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 932         {
 933                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 934                 return ERROR_OK;
 935         }
 936
 937         jtag_info = &arm7_9->jtag_info;
 938
 939         if (target->state != TARGET_HALTED)
 940         {
 941                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 942                 return ERROR_OK;
 943         }
 944
 945         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
 946 }
 947
 948 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 949 {
 950         target_t *target = get_current_target(cmd_ctx);
 951         armv4_5_common_t *armv4_5;
 952         arm7_9_common_t *arm7_9;
 953         arm9tdmi_common_t *arm9tdmi;
 954         arm920t_common_t *arm920t;
 955         arm_jtag_t *jtag_info;
 956
 957         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 958         {
 959                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 960                 return ERROR_OK;
 961         }
 962
 963         jtag_info = &arm7_9->jtag_info;
 964
 965         if (target->state != TARGET_HALTED)
 966         {
 967                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 968                 return ERROR_OK;
 969         }
 970
 971         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
 972 }