1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include "time_support.h"
26 #include "target_type.h"
31 * For information about the ARM920T, see ARM DDI 0151C especially
32 * Chapter 9 about debug support, which shows how to manipulate each
33 * of the different scan chains:
35 * 0 ... ARM920 signals, e.g. to rest of SOC (unused here)
36 * 1 ... debugging; watchpoint and breakpoint status, etc; also
37 * MMU and cache access in conjunction with scan chain 15
39 * 3 ... external boundary scan (SoC-specific, unused here)
40 * 4 ... access to cache tag RAM
42 * 15 ... access coprocessor 15, "physical" or "interpreted" modes
43 * "interpreted" works with a few actual MRC/MCR instructions
44 * "physical" provides register-like behaviors.
46 * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
50 #define _DEBUG_INSTRUCTION_EXECUTION_
53 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
55 static int arm920t_read_cp15_physical(struct target *target,
56 int reg_addr, uint32_t *value)
58 struct arm920t_common *arm920t = target_to_arm920(target);
59 struct arm_jtag *jtag_info;
60 struct scan_field fields[4];
61 uint8_t access_type_buf = 1;
62 uint8_t reg_addr_buf = reg_addr & 0x3f;
65 jtag_info = &arm920t->arm7_9_common.jtag_info;
67 jtag_set_end_state(TAP_IDLE);
68 arm_jtag_scann(jtag_info, 0xf);
69 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
71 fields[0].tap = jtag_info->tap;
72 fields[0].num_bits = 1;
73 fields[0].out_value = &access_type_buf;
74 fields[0].in_value = NULL;
76 fields[1].tap = jtag_info->tap;
77 fields[1].num_bits = 32;
78 fields[1].out_value = NULL;
79 fields[1].in_value = NULL;
81 fields[2].tap = jtag_info->tap;
82 fields[2].num_bits = 6;
83 fields[2].out_value = ®_addr_buf;
84 fields[2].in_value = NULL;
86 fields[3].tap = jtag_info->tap;
87 fields[3].num_bits = 1;
88 fields[3].out_value = &nr_w_buf;
89 fields[3].in_value = NULL;
91 jtag_add_dr_scan(4, fields, jtag_get_end_state());
93 fields[1].in_value = (uint8_t *)value;
95 jtag_add_dr_scan(4, fields, jtag_get_end_state());
97 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
99 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
100 jtag_execute_queue();
101 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
107 static int arm920t_write_cp15_physical(struct target *target,
108 int reg_addr, uint32_t value)
110 struct arm920t_common *arm920t = target_to_arm920(target);
111 struct arm_jtag *jtag_info;
112 struct scan_field fields[4];
113 uint8_t access_type_buf = 1;
114 uint8_t reg_addr_buf = reg_addr & 0x3f;
115 uint8_t nr_w_buf = 1;
116 uint8_t value_buf[4];
118 jtag_info = &arm920t->arm7_9_common.jtag_info;
120 buf_set_u32(value_buf, 0, 32, value);
122 jtag_set_end_state(TAP_IDLE);
123 arm_jtag_scann(jtag_info, 0xf);
124 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
126 fields[0].tap = jtag_info->tap;
127 fields[0].num_bits = 1;
128 fields[0].out_value = &access_type_buf;
129 fields[0].in_value = NULL;
131 fields[1].tap = jtag_info->tap;
132 fields[1].num_bits = 32;
133 fields[1].out_value = value_buf;
134 fields[1].in_value = NULL;
136 fields[2].tap = jtag_info->tap;
137 fields[2].num_bits = 6;
138 fields[2].out_value = ®_addr_buf;
139 fields[2].in_value = NULL;
141 fields[3].tap = jtag_info->tap;
142 fields[3].num_bits = 1;
143 fields[3].out_value = &nr_w_buf;
144 fields[3].in_value = NULL;
146 jtag_add_dr_scan(4, fields, jtag_get_end_state());
148 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
149 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
155 static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
159 struct arm920t_common *arm920t = target_to_arm920(target);
160 struct arm_jtag *jtag_info;
161 struct scan_field fields[4];
162 uint8_t access_type_buf = 0; /* interpreted access */
163 uint8_t reg_addr_buf = 0x0;
164 uint8_t nr_w_buf = 0;
165 uint8_t cp15_opcode_buf[4];
167 jtag_info = &arm920t->arm7_9_common.jtag_info;
169 jtag_set_end_state(TAP_IDLE);
170 arm_jtag_scann(jtag_info, 0xf);
171 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
173 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
175 fields[0].tap = jtag_info->tap;
176 fields[0].num_bits = 1;
177 fields[0].out_value = &access_type_buf;
178 fields[0].in_value = NULL;
180 fields[1].tap = jtag_info->tap;
181 fields[1].num_bits = 32;
182 fields[1].out_value = cp15_opcode_buf;
183 fields[1].in_value = NULL;
185 fields[2].tap = jtag_info->tap;
186 fields[2].num_bits = 6;
187 fields[2].out_value = ®_addr_buf;
188 fields[2].in_value = NULL;
190 fields[3].tap = jtag_info->tap;
191 fields[3].num_bits = 1;
192 fields[3].out_value = &nr_w_buf;
193 fields[3].in_value = NULL;
195 jtag_add_dr_scan(4, fields, jtag_get_end_state());
197 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
198 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
199 retval = arm7_9_execute_sys_speed(target);
200 if (retval != ERROR_OK)
203 if ((retval = jtag_execute_queue()) != ERROR_OK)
205 LOG_ERROR("failed executing JTAG queue");
212 static int arm920t_read_cp15_interpreted(struct target *target,
213 uint32_t cp15_opcode, uint32_t address, uint32_t *value)
215 struct arm *armv4_5 = target_to_armv4_5(target);
218 uint32_t cp15c15 = 0x0;
219 struct reg *r = armv4_5->core_cache->reg_list;
221 /* load address into R1 */
223 arm9tdmi_write_core_regs(target, 0x2, regs);
225 /* read-modify-write CP15 test state register
226 * to enable interpreted access mode */
227 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
228 jtag_execute_queue();
229 cp15c15 |= 1; /* set interpret mode */
230 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
232 /* execute CP15 instruction and ARM load (reading from coprocessor) */
233 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
235 /* disable interpreted access mode */
236 cp15c15 &= ~1U; /* clear interpret mode */
237 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
239 /* retrieve value from R0 */
241 arm9tdmi_read_core_regs(target, 0x1, regs_p);
242 jtag_execute_queue();
244 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
245 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
248 if (!is_arm_mode(armv4_5->core_mode))
258 int arm920t_write_cp15_interpreted(struct target *target,
259 uint32_t cp15_opcode, uint32_t value, uint32_t address)
261 uint32_t cp15c15 = 0x0;
262 struct arm *armv4_5 = target_to_armv4_5(target);
264 struct reg *r = armv4_5->core_cache->reg_list;
266 /* load value, address into R0, R1 */
269 arm9tdmi_write_core_regs(target, 0x3, regs);
271 /* read-modify-write CP15 test state register
272 * to enable interpreted access mode */
273 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
274 jtag_execute_queue();
275 cp15c15 |= 1; /* set interpret mode */
276 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
278 /* execute CP15 instruction and ARM store (writing to coprocessor) */
279 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
281 /* disable interpreted access mode */
282 cp15c15 &= ~1U; /* set interpret mode */
283 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
285 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
286 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
289 if (!is_arm_mode(armv4_5->core_mode))
299 uint32_t arm920t_get_ttb(struct target *target)
304 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
311 void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
313 uint32_t cp15_control;
315 /* read cp15 control register */
316 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
317 jtag_execute_queue();
320 cp15_control &= ~0x1U;
323 cp15_control &= ~0x4U;
326 cp15_control &= ~0x1000U;
328 arm920t_write_cp15_physical(target, 0x2, cp15_control);
332 void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
334 uint32_t cp15_control;
336 /* read cp15 control register */
337 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
338 jtag_execute_queue();
341 cp15_control |= 0x1U;
344 cp15_control |= 0x4U;
347 cp15_control |= 0x1000U;
349 arm920t_write_cp15_physical(target, 0x2, cp15_control);
353 void arm920t_post_debug_entry(struct target *target)
356 struct arm920t_common *arm920t = target_to_arm920(target);
358 /* examine cp15 control reg */
359 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
360 jtag_execute_queue();
361 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
363 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
365 uint32_t cache_type_reg;
366 /* identify caches */
367 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
368 jtag_execute_queue();
369 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
372 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
373 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
374 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
376 /* save i/d fault status and address register */
377 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
378 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
379 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
380 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
382 LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
383 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
385 if (arm920t->preserve_cache)
387 /* read-modify-write CP15 test state register
388 * to disable I/D-cache linefills */
389 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
390 jtag_execute_queue();
392 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
397 void arm920t_pre_restore_context(struct target *target)
400 struct arm920t_common *arm920t = target_to_arm920(target);
402 /* restore i/d fault status and address register */
403 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
404 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
405 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
406 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
408 /* read-modify-write CP15 test state register
409 * to reenable I/D-cache linefills */
410 if (arm920t->preserve_cache)
412 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
413 jtag_execute_queue();
415 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
419 static const char arm920_not[] = "target is not an ARM920";
421 static int arm920t_verify_pointer(struct command_context *cmd_ctx,
422 struct arm920t_common *arm920t)
424 if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
425 command_print(cmd_ctx, arm920_not);
426 return ERROR_TARGET_INVALID;
432 /** Logs summary of ARM920 state for a halted target. */
433 int arm920t_arch_state(struct target *target)
435 static const char *state[] =
437 "disabled", "enabled"
440 struct arm920t_common *arm920t = target_to_arm920(target);
443 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
445 LOG_ERROR("BUG: %s", arm920_not);
446 return ERROR_TARGET_INVALID;
449 armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
451 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
452 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
453 "MMU: %s, D-Cache: %s, I-Cache: %s",
454 armv4_5_state_strings[armv4_5->core_state],
455 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
456 arm_mode_name(armv4_5->core_mode),
457 buf_get_u32(armv4_5->cpsr->value, 0, 32),
458 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
459 state[arm920t->armv4_5_mmu.mmu_enabled],
460 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
461 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
466 static int arm920_mmu(struct target *target, int *enabled)
468 if (target->state != TARGET_HALTED) {
469 LOG_ERROR("%s: target not halted", __func__);
470 return ERROR_TARGET_INVALID;
473 *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled;
477 static int arm920_virt2phys(struct target *target,
478 uint32_t virt, uint32_t *phys)
480 /** @todo Implement this! */
481 LOG_ERROR("%s: not implemented", __func__);
485 /** Reads a buffer, in the specified word size, with current MMU settings. */
486 int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
490 retval = arm7_9_read_memory(target, address, size, count, buffer);
496 static int arm920t_read_phys_memory(struct target *target,
497 uint32_t address, uint32_t size,
498 uint32_t count, uint8_t *buffer)
500 struct arm920t_common *arm920t = target_to_arm920(target);
502 return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu,
503 address, size, count, buffer);
506 static int arm920t_write_phys_memory(struct target *target,
507 uint32_t address, uint32_t size,
508 uint32_t count, uint8_t *buffer)
510 struct arm920t_common *arm920t = target_to_arm920(target);
512 return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
513 address, size, count, buffer);
517 /** Writes a buffer, in the specified word size, with current MMU settings. */
518 int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
522 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
525 /* This fn is used to write breakpoints, so we need to make sure
526 * that the data cache is flushed and the instruction cache is
529 if (((size == 4) || (size == 2)) && (count == 1))
531 struct arm920t_common *arm920t = target_to_arm920(target);
533 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
535 LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
536 /* MCR p15,0,Rd,c7,c10,2 */
537 retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
538 if (retval != ERROR_OK)
542 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
544 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
545 retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
546 if (retval != ERROR_OK)
555 int arm920t_soft_reset_halt(struct target *target)
557 int retval = ERROR_OK;
558 struct arm920t_common *arm920t = target_to_arm920(target);
559 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
560 struct arm *armv4_5 = &arm7_9->armv4_5_common;
561 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
563 if ((retval = target_halt(target)) != ERROR_OK)
568 long long then = timeval_ms();
570 while (!(timeout = ((timeval_ms()-then) > 1000)))
572 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
574 embeddedice_read_reg(dbg_stat);
575 if ((retval = jtag_execute_queue()) != ERROR_OK)
583 if (debug_level >= 3)
585 /* do not eat all CPU, time out after 1 se*/
594 LOG_ERROR("Failed to halt CPU after 1 sec");
595 return ERROR_TARGET_TIMEOUT;
598 target->state = TARGET_HALTED;
600 /* SVC, ARM state, IRQ and FIQ disabled */
603 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
606 arm_set_cpsr(armv4_5, cpsr);
607 armv4_5->cpsr->dirty = 1;
609 /* start fetching from 0x0 */
610 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
611 armv4_5->core_cache->reg_list[15].dirty = 1;
612 armv4_5->core_cache->reg_list[15].valid = 1;
614 arm920t_disable_mmu_caches(target, 1, 1, 1);
615 arm920t->armv4_5_mmu.mmu_enabled = 0;
616 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
617 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
619 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
627 int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
629 struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
631 /* initialize arm7/arm9 specific info (including armv4_5) */
632 arm9tdmi_init_arch_info(target, arm7_9, tap);
634 arm920t->common_magic = ARM920T_COMMON_MAGIC;
636 arm7_9->post_debug_entry = arm920t_post_debug_entry;
637 arm7_9->pre_restore_context = arm920t_pre_restore_context;
639 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
640 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
641 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
642 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
643 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
644 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
645 arm920t->armv4_5_mmu.has_tiny_pages = 1;
646 arm920t->armv4_5_mmu.mmu_enabled = 0;
648 /* disabling linefills leads to lockups, so keep them enabled for now
649 * this doesn't affect correctness, but might affect timing issues, if
650 * important data is evicted from the cache during the debug session
652 arm920t->preserve_cache = 0;
654 /* override hw single-step capability from ARM9TDMI */
655 arm7_9->has_single_step = 1;
660 static int arm920t_target_create(struct target *target, Jim_Interp *interp)
662 struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
664 return arm920t_init_arch_info(target, arm920t, target->tap);
667 COMMAND_HANDLER(arm920t_handle_read_cache_command)
669 int retval = ERROR_OK;
670 struct target *target = get_current_target(CMD_CTX);
671 struct arm920t_common *arm920t = target_to_arm920(target);
672 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
673 struct arm *armv4_5 = &arm7_9->armv4_5_common;
675 uint32_t cp15_ctrl, cp15_ctrl_saved;
677 uint32_t *regs_p[16];
678 uint32_t C15_C_D_Ind, C15_C_I_Ind;
681 struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
685 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
686 if (retval != ERROR_OK)
691 command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
695 if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
697 LOG_DEBUG("error opening cache content file");
701 for (i = 0; i < 16; i++)
702 regs_p[i] = ®s[i];
704 /* disable MMU and Caches */
705 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
706 if ((retval = jtag_execute_queue()) != ERROR_OK)
710 cp15_ctrl_saved = cp15_ctrl;
711 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
712 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
714 /* read CP15 test state register */
715 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
716 jtag_execute_queue();
718 /* read DCache content */
719 fprintf(output, "DCache:\n");
721 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
722 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
724 fprintf(output, "\nsegment: %i\n----------", segment);
726 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
727 regs[0] = 0x0 | (segment << 5);
728 arm9tdmi_write_core_regs(target, 0x1, regs);
730 /* set interpret mode */
732 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
734 /* D CAM Read, loads current victim into C15.C.D.Ind */
735 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
737 /* read current victim */
738 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
740 /* clear interpret mode */
742 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
744 for (index = 0; index < 64; index++)
746 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
747 regs[0] = 0x0 | (segment << 5) | (index << 26);
748 arm9tdmi_write_core_regs(target, 0x1, regs);
750 /* set interpret mode */
752 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
754 /* Write DCache victim */
755 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
758 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
761 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
763 /* clear interpret mode */
765 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
767 /* read D RAM and CAM content */
768 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
769 if ((retval = jtag_execute_queue()) != ERROR_OK)
774 d_cache[segment][index].cam = regs[9];
777 regs[9] &= 0xfffffffe;
778 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
780 for (i = 1; i < 9; i++)
782 d_cache[segment][index].data[i] = regs[i];
783 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
788 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
789 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
790 arm9tdmi_write_core_regs(target, 0x1, regs);
792 /* set interpret mode */
794 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
796 /* Write DCache victim */
797 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
799 /* clear interpret mode */
801 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
804 /* read ICache content */
805 fprintf(output, "ICache:\n");
807 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
808 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
810 fprintf(output, "segment: %i\n----------", segment);
812 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
813 regs[0] = 0x0 | (segment << 5);
814 arm9tdmi_write_core_regs(target, 0x1, regs);
816 /* set interpret mode */
818 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
820 /* I CAM Read, loads current victim into C15.C.I.Ind */
821 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
823 /* read current victim */
824 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
826 /* clear interpret mode */
828 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
830 for (index = 0; index < 64; index++)
832 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
833 regs[0] = 0x0 | (segment << 5) | (index << 26);
834 arm9tdmi_write_core_regs(target, 0x1, regs);
836 /* set interpret mode */
838 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
840 /* Write ICache victim */
841 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
844 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
847 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
849 /* clear interpret mode */
851 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
853 /* read I RAM and CAM content */
854 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
855 if ((retval = jtag_execute_queue()) != ERROR_OK)
860 i_cache[segment][index].cam = regs[9];
863 regs[9] &= 0xfffffffe;
864 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
866 for (i = 1; i < 9; i++)
868 i_cache[segment][index].data[i] = regs[i];
869 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
873 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
874 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
875 arm9tdmi_write_core_regs(target, 0x1, regs);
877 /* set interpret mode */
879 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
881 /* Write ICache victim */
882 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
884 /* clear interpret mode */
886 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
889 /* restore CP15 MMU and Cache settings */
890 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
892 command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
896 if (!is_arm_mode(armv4_5->core_mode))
899 /* force writeback of the valid data */
900 r = armv4_5->core_cache->reg_list;
901 r[0].dirty = r[0].valid;
902 r[1].dirty = r[1].valid;
903 r[2].dirty = r[2].valid;
904 r[3].dirty = r[3].valid;
905 r[4].dirty = r[4].valid;
906 r[5].dirty = r[5].valid;
907 r[6].dirty = r[6].valid;
908 r[7].dirty = r[7].valid;
910 r = arm_reg_current(armv4_5, 8);
913 r = arm_reg_current(armv4_5, 9);
919 COMMAND_HANDLER(arm920t_handle_read_mmu_command)
921 int retval = ERROR_OK;
922 struct target *target = get_current_target(CMD_CTX);
923 struct arm920t_common *arm920t = target_to_arm920(target);
924 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
925 struct arm *armv4_5 = &arm7_9->armv4_5_common;
927 uint32_t cp15_ctrl, cp15_ctrl_saved;
929 uint32_t *regs_p[16];
932 uint32_t Dlockdown, Ilockdown;
933 struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
937 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
938 if (retval != ERROR_OK)
943 command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
947 if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
949 LOG_DEBUG("error opening mmu content file");
953 for (i = 0; i < 16; i++)
954 regs_p[i] = ®s[i];
956 /* disable MMU and Caches */
957 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
958 if ((retval = jtag_execute_queue()) != ERROR_OK)
962 cp15_ctrl_saved = cp15_ctrl;
963 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
964 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
966 /* read CP15 test state register */
967 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
968 if ((retval = jtag_execute_queue()) != ERROR_OK)
973 /* prepare reading D TLB content
976 /* set interpret mode */
978 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
980 /* Read D TLB lockdown */
981 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
983 /* clear interpret mode */
985 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
987 /* read D TLB lockdown stored to r1 */
988 arm9tdmi_read_core_regs(target, 0x2, regs_p);
989 if ((retval = jtag_execute_queue()) != ERROR_OK)
995 for (victim = 0; victim < 64; victim += 8)
997 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
998 * base remains unchanged, victim goes through entries 0 to 63 */
999 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1000 arm9tdmi_write_core_regs(target, 0x2, regs);
1002 /* set interpret mode */
1004 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1006 /* Write D TLB lockdown */
1007 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1009 /* Read D TLB CAM */
1010 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1012 /* clear interpret mode */
1014 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1016 /* read D TLB CAM content stored to r2-r9 */
1017 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1018 if ((retval = jtag_execute_queue()) != ERROR_OK)
1023 for (i = 0; i < 8; i++)
1024 d_tlb[victim + i].cam = regs[i + 2];
1027 for (victim = 0; victim < 64; victim++)
1029 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1030 * base remains unchanged, victim goes through entries 0 to 63 */
1031 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1032 arm9tdmi_write_core_regs(target, 0x2, regs);
1034 /* set interpret mode */
1036 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1038 /* Write D TLB lockdown */
1039 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1041 /* Read D TLB RAM1 */
1042 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1044 /* Read D TLB RAM2 */
1045 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1047 /* clear interpret mode */
1049 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1051 /* read D TLB RAM content stored to r2 and r3 */
1052 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1053 if ((retval = jtag_execute_queue()) != ERROR_OK)
1058 d_tlb[victim].ram1 = regs[2];
1059 d_tlb[victim].ram2 = regs[3];
1062 /* restore D TLB lockdown */
1063 regs[1] = Dlockdown;
1064 arm9tdmi_write_core_regs(target, 0x2, regs);
1066 /* Write D TLB lockdown */
1067 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1069 /* prepare reading I TLB content
1072 /* set interpret mode */
1074 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1076 /* Read I TLB lockdown */
1077 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1079 /* clear interpret mode */
1081 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1083 /* read I TLB lockdown stored to r1 */
1084 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1085 if ((retval = jtag_execute_queue()) != ERROR_OK)
1089 Ilockdown = regs[1];
1091 for (victim = 0; victim < 64; victim += 8)
1093 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1094 * base remains unchanged, victim goes through entries 0 to 63 */
1095 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1096 arm9tdmi_write_core_regs(target, 0x2, regs);
1098 /* set interpret mode */
1100 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1102 /* Write I TLB lockdown */
1103 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1105 /* Read I TLB CAM */
1106 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1108 /* clear interpret mode */
1110 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1112 /* read I TLB CAM content stored to r2-r9 */
1113 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1114 if ((retval = jtag_execute_queue()) != ERROR_OK)
1119 for (i = 0; i < 8; i++)
1120 i_tlb[i + victim].cam = regs[i + 2];
1123 for (victim = 0; victim < 64; victim++)
1125 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1126 * base remains unchanged, victim goes through entries 0 to 63 */
1127 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1128 arm9tdmi_write_core_regs(target, 0x2, regs);
1130 /* set interpret mode */
1132 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1134 /* Write I TLB lockdown */
1135 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1137 /* Read I TLB RAM1 */
1138 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1140 /* Read I TLB RAM2 */
1141 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1143 /* clear interpret mode */
1145 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1147 /* read I TLB RAM content stored to r2 and r3 */
1148 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1149 if ((retval = jtag_execute_queue()) != ERROR_OK)
1154 i_tlb[victim].ram1 = regs[2];
1155 i_tlb[victim].ram2 = regs[3];
1158 /* restore I TLB lockdown */
1159 regs[1] = Ilockdown;
1160 arm9tdmi_write_core_regs(target, 0x2, regs);
1162 /* Write I TLB lockdown */
1163 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1165 /* restore CP15 MMU and Cache settings */
1166 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1168 /* output data to file */
1169 fprintf(output, "D TLB content:\n");
1170 for (i = 0; i < 64; i++)
1172 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1175 fprintf(output, "\n\nI TLB content:\n");
1176 for (i = 0; i < 64; i++)
1178 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1181 command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
1185 if (!is_arm_mode(armv4_5->core_mode))
1188 /* force writeback of the valid data */
1189 r = armv4_5->core_cache->reg_list;
1190 r[0].dirty = r[0].valid;
1191 r[1].dirty = r[1].valid;
1192 r[2].dirty = r[2].valid;
1193 r[3].dirty = r[3].valid;
1194 r[4].dirty = r[4].valid;
1195 r[5].dirty = r[5].valid;
1196 r[6].dirty = r[6].valid;
1197 r[7].dirty = r[7].valid;
1199 r = arm_reg_current(armv4_5, 8);
1200 r->dirty = r->valid;
1202 r = arm_reg_current(armv4_5, 9);
1203 r->dirty = r->valid;
1208 COMMAND_HANDLER(arm920t_handle_cp15_command)
1211 struct target *target = get_current_target(CMD_CTX);
1212 struct arm920t_common *arm920t = target_to_arm920(target);
1214 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1215 if (retval != ERROR_OK)
1218 if (target->state != TARGET_HALTED)
1220 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1224 /* one or more argument, access a single register (write if second argument is given */
1228 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
1233 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1235 command_print(CMD_CTX, "couldn't access reg %i", address);
1238 if ((retval = jtag_execute_queue()) != ERROR_OK)
1243 command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1245 else if (CMD_ARGC == 2)
1248 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1249 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1251 command_print(CMD_CTX, "couldn't access reg %i", address);
1254 command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1261 COMMAND_HANDLER(arm920t_handle_cp15i_command)
1264 struct target *target = get_current_target(CMD_CTX);
1265 struct arm920t_common *arm920t = target_to_arm920(target);
1267 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1268 if (retval != ERROR_OK)
1272 if (target->state != TARGET_HALTED)
1274 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1278 /* one or more argument, access a single register (write if second argument is given */
1282 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
1287 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1289 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1293 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1295 else if (CMD_ARGC == 2)
1298 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1299 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1301 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1304 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1306 else if (CMD_ARGC == 3)
1309 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1311 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
1312 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1314 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1317 command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
1322 command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
1328 COMMAND_HANDLER(arm920t_handle_cache_info_command)
1331 struct target *target = get_current_target(CMD_CTX);
1332 struct arm920t_common *arm920t = target_to_arm920(target);
1334 retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1335 if (retval != ERROR_OK)
1338 return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
1342 static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
1346 LOG_ERROR("Only cp15 is supported");
1350 return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
1353 static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
1357 LOG_ERROR("Only cp15 is supported");
1361 return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
1364 static const struct command_registration arm920t_exec_command_handlers[] = {
1367 .handler = &arm920t_handle_cp15_command,
1368 .mode = COMMAND_EXEC,
1369 .help = "display/modify cp15 register",
1370 .usage = "<num> [value]",
1374 .handler = &arm920t_handle_cp15i_command,
1375 .mode = COMMAND_EXEC,
1376 .help = "display/modify cp15 (interpreted access)",
1377 .usage = "<opcode> [value] [address]",
1380 .name = "cache_info",
1381 .handler = &arm920t_handle_cache_info_command,
1382 .mode = COMMAND_EXEC,
1383 .help = "display information about target caches",
1386 .name = "read_cache",
1387 .handler = &arm920t_handle_read_cache_command,
1388 .mode = COMMAND_EXEC,
1389 .help = "display I/D cache content",
1393 .handler = &arm920t_handle_read_mmu_command,
1394 .mode = COMMAND_EXEC,
1395 .help = "display I/D mmu content",
1397 COMMAND_REGISTRATION_DONE
1399 const struct command_registration arm920t_command_handlers[] = {
1401 .chain = arm9tdmi_command_handlers,
1405 .mode = COMMAND_ANY,
1406 .help = "arm920t command group",
1407 .chain = arm920t_exec_command_handlers,
1409 COMMAND_REGISTRATION_DONE
1412 /** Holds methods for ARM920 targets. */
1413 struct target_type arm920t_target =
1417 .poll = arm7_9_poll,
1418 .arch_state = arm920t_arch_state,
1420 .target_request_data = arm7_9_target_request_data,
1422 .halt = arm7_9_halt,
1423 .resume = arm7_9_resume,
1424 .step = arm7_9_step,
1426 .assert_reset = arm7_9_assert_reset,
1427 .deassert_reset = arm7_9_deassert_reset,
1428 .soft_reset_halt = arm920t_soft_reset_halt,
1430 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1432 .read_memory = arm920t_read_memory,
1433 .write_memory = arm920t_write_memory,
1434 .read_phys_memory = arm920t_read_phys_memory,
1435 .write_phys_memory = arm920t_write_phys_memory,
1437 .virt2phys = arm920_virt2phys,
1439 .bulk_write_memory = arm7_9_bulk_write_memory,
1441 .checksum_memory = arm_checksum_memory,
1442 .blank_check_memory = arm_blank_check_memory,
1444 .run_algorithm = armv4_5_run_algorithm,
1446 .add_breakpoint = arm7_9_add_breakpoint,
1447 .remove_breakpoint = arm7_9_remove_breakpoint,
1448 .add_watchpoint = arm7_9_add_watchpoint,
1449 .remove_watchpoint = arm7_9_remove_watchpoint,
1451 .commands = arm920t_command_handlers,
1452 .target_create = arm920t_target_create,
1453 .init_target = arm9tdmi_init_target,
1454 .examine = arm7_9_examine,