1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
25 #include "time_support.h"
29 #define _DEBUG_INSTRUCTION_EXECUTION_
33 int arm920t_register_commands(struct command_context_s *cmd_ctx);
35 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 /* forward declarations */
46 int arm920t_target_create(struct target_s *target, Jim_Interp *interp);
47 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
48 int arm920t_quit(void);
49 int arm920t_arch_state(struct target_s *target);
50 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
51 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
52 int arm920t_soft_reset_halt(struct target_s *target);
54 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
56 target_type_t arm920t_target =
61 .arch_state = arm920t_arch_state,
63 .target_request_data = arm7_9_target_request_data,
66 .resume = arm7_9_resume,
69 .assert_reset = arm7_9_assert_reset,
70 .deassert_reset = arm7_9_deassert_reset,
71 .soft_reset_halt = arm920t_soft_reset_halt,
73 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
75 .read_memory = arm920t_read_memory,
76 .write_memory = arm920t_write_memory,
77 .bulk_write_memory = arm7_9_bulk_write_memory,
78 .checksum_memory = arm7_9_checksum_memory,
79 .blank_check_memory = arm7_9_blank_check_memory,
81 .run_algorithm = armv4_5_run_algorithm,
83 .add_breakpoint = arm7_9_add_breakpoint,
84 .remove_breakpoint = arm7_9_remove_breakpoint,
85 .add_watchpoint = arm7_9_add_watchpoint,
86 .remove_watchpoint = arm7_9_remove_watchpoint,
88 .register_commands = arm920t_register_commands,
89 .target_create = arm920t_target_create,
90 .init_target = arm920t_init_target,
91 .examine = arm9tdmi_examine,
95 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
97 armv4_5_common_t *armv4_5 = target->arch_info;
98 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
99 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
100 scan_field_t fields[4];
101 u8 access_type_buf = 1;
102 u8 reg_addr_buf = reg_addr & 0x3f;
105 jtag_add_end_state(TAP_IDLE);
106 arm_jtag_scann(jtag_info, 0xf);
107 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
109 fields[0].tap = jtag_info->tap;
110 fields[0].num_bits = 1;
111 fields[0].out_value = &access_type_buf;
112 fields[0].in_value = NULL;
114 fields[1].tap = jtag_info->tap;
115 fields[1].num_bits = 32;
116 fields[1].out_value = NULL;
117 fields[1].in_value = NULL;
119 fields[2].tap = jtag_info->tap;
120 fields[2].num_bits = 6;
121 fields[2].out_value = ®_addr_buf;
122 fields[2].in_value = NULL;
124 fields[3].tap = jtag_info->tap;
125 fields[3].num_bits = 1;
126 fields[3].out_value = &nr_w_buf;
127 fields[3].in_value = NULL;
129 jtag_add_dr_scan(4, fields, TAP_INVALID);
131 fields[1].in_value = (u8 *)value;
133 jtag_add_dr_scan(4, fields, TAP_INVALID);
135 jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
137 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
138 jtag_execute_queue();
139 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
145 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
147 armv4_5_common_t *armv4_5 = target->arch_info;
148 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
149 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
150 scan_field_t fields[4];
151 u8 access_type_buf = 1;
152 u8 reg_addr_buf = reg_addr & 0x3f;
156 buf_set_u32(value_buf, 0, 32, value);
158 jtag_add_end_state(TAP_IDLE);
159 arm_jtag_scann(jtag_info, 0xf);
160 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
162 fields[0].tap = jtag_info->tap;
163 fields[0].num_bits = 1;
164 fields[0].out_value = &access_type_buf;
165 fields[0].in_value = NULL;
167 fields[1].tap = jtag_info->tap;
168 fields[1].num_bits = 32;
169 fields[1].out_value = value_buf;
170 fields[1].in_value = NULL;
172 fields[2].tap = jtag_info->tap;
173 fields[2].num_bits = 6;
174 fields[2].out_value = ®_addr_buf;
175 fields[2].in_value = NULL;
177 fields[3].tap = jtag_info->tap;
178 fields[3].num_bits = 1;
179 fields[3].out_value = &nr_w_buf;
180 fields[3].in_value = NULL;
182 jtag_add_dr_scan(4, fields, TAP_INVALID);
184 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
185 LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
191 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
194 armv4_5_common_t *armv4_5 = target->arch_info;
195 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
196 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
197 scan_field_t fields[4];
198 u8 access_type_buf = 0; /* interpreted access */
199 u8 reg_addr_buf = 0x0;
201 u8 cp15_opcode_buf[4];
203 jtag_add_end_state(TAP_IDLE);
204 arm_jtag_scann(jtag_info, 0xf);
205 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
207 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
209 fields[0].tap = jtag_info->tap;
210 fields[0].num_bits = 1;
211 fields[0].out_value = &access_type_buf;
212 fields[0].in_value = NULL;
214 fields[1].tap = jtag_info->tap;
215 fields[1].num_bits = 32;
216 fields[1].out_value = cp15_opcode_buf;
217 fields[1].in_value = NULL;
219 fields[2].tap = jtag_info->tap;
220 fields[2].num_bits = 6;
221 fields[2].out_value = ®_addr_buf;
222 fields[2].in_value = NULL;
224 fields[3].tap = jtag_info->tap;
225 fields[3].num_bits = 1;
226 fields[3].out_value = &nr_w_buf;
227 fields[3].in_value = NULL;
229 jtag_add_dr_scan(4, fields, TAP_INVALID);
231 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
232 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
233 retval = arm7_9_execute_sys_speed(target);
234 if (retval != ERROR_OK)
237 if ((retval = jtag_execute_queue()) != ERROR_OK)
239 LOG_ERROR("failed executing JTAG queue, exiting");
246 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
248 armv4_5_common_t *armv4_5 = target->arch_info;
253 /* load address into R1 */
255 arm9tdmi_write_core_regs(target, 0x2, regs);
257 /* read-modify-write CP15 test state register
258 * to enable interpreted access mode */
259 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
260 jtag_execute_queue();
261 cp15c15 |= 1; /* set interpret mode */
262 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
264 /* execute CP15 instruction and ARM load (reading from coprocessor) */
265 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
267 /* disable interpreted access mode */
268 cp15c15 &= ~1U; /* clear interpret mode */
269 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
271 /* retrieve value from R0 */
273 arm9tdmi_read_core_regs(target, 0x1, regs_p);
274 jtag_execute_queue();
276 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
277 LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
280 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
283 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
284 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
289 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
292 armv4_5_common_t *armv4_5 = target->arch_info;
295 /* load value, address into R0, R1 */
298 arm9tdmi_write_core_regs(target, 0x3, regs);
300 /* read-modify-write CP15 test state register
301 * to enable interpreted access mode */
302 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
303 jtag_execute_queue();
304 cp15c15 |= 1; /* set interpret mode */
305 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
307 /* execute CP15 instruction and ARM store (writing to coprocessor) */
308 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
310 /* disable interpreted access mode */
311 cp15c15 &= ~1U; /* set interpret mode */
312 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
314 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
315 LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
318 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
321 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
322 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
327 u32 arm920t_get_ttb(target_t *target)
332 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
338 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
342 /* read cp15 control register */
343 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
344 jtag_execute_queue();
347 cp15_control &= ~0x1U;
350 cp15_control &= ~0x4U;
353 cp15_control &= ~0x1000U;
355 arm920t_write_cp15_physical(target, 0x2, cp15_control);
358 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
362 /* read cp15 control register */
363 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
364 jtag_execute_queue();
367 cp15_control |= 0x1U;
370 cp15_control |= 0x4U;
373 cp15_control |= 0x1000U;
375 arm920t_write_cp15_physical(target, 0x2, cp15_control);
378 void arm920t_post_debug_entry(target_t *target)
381 armv4_5_common_t *armv4_5 = target->arch_info;
382 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
383 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
384 arm920t_common_t *arm920t = arm9tdmi->arch_info;
386 /* examine cp15 control reg */
387 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
388 jtag_execute_queue();
389 LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
391 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
394 /* identify caches */
395 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
396 jtag_execute_queue();
397 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
400 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
401 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
402 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
404 /* save i/d fault status and address register */
405 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
406 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
407 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
408 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
410 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
411 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
413 if (arm920t->preserve_cache)
415 /* read-modify-write CP15 test state register
416 * to disable I/D-cache linefills */
417 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
418 jtag_execute_queue();
420 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
424 void arm920t_pre_restore_context(target_t *target)
427 armv4_5_common_t *armv4_5 = target->arch_info;
428 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
429 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
430 arm920t_common_t *arm920t = arm9tdmi->arch_info;
432 /* restore i/d fault status and address register */
433 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
434 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
435 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
436 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
438 /* read-modify-write CP15 test state register
439 * to reenable I/D-cache linefills */
440 if (arm920t->preserve_cache)
442 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
443 jtag_execute_queue();
445 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
449 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
451 armv4_5_common_t *armv4_5 = target->arch_info;
452 arm7_9_common_t *arm7_9;
453 arm9tdmi_common_t *arm9tdmi;
454 arm920t_common_t *arm920t;
456 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
461 arm7_9 = armv4_5->arch_info;
462 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
467 arm9tdmi = arm7_9->arch_info;
468 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
473 arm920t = arm9tdmi->arch_info;
474 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
479 *armv4_5_p = armv4_5;
481 *arm9tdmi_p = arm9tdmi;
482 *arm920t_p = arm920t;
487 int arm920t_arch_state(struct target_s *target)
489 armv4_5_common_t *armv4_5 = target->arch_info;
490 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
491 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
492 arm920t_common_t *arm920t = arm9tdmi->arch_info;
496 "disabled", "enabled"
499 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
501 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
505 LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
506 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
507 "MMU: %s, D-Cache: %s, I-Cache: %s",
508 armv4_5_state_strings[armv4_5->core_state],
509 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
510 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
511 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
512 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
513 state[arm920t->armv4_5_mmu.mmu_enabled],
514 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
515 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
520 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
524 retval = arm7_9_read_memory(target, address, size, count, buffer);
529 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
532 armv4_5_common_t *armv4_5 = target->arch_info;
533 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
534 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
535 arm920t_common_t *arm920t = arm9tdmi->arch_info;
537 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
540 if (((size == 4) || (size == 2)) && (count == 1))
542 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
544 LOG_DEBUG("D-Cache enabled, writing through to main memory");
548 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
551 /* cacheable & bufferable means write-back region */
553 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
556 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
558 LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
559 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
566 int arm920t_soft_reset_halt(struct target_s *target)
568 int retval = ERROR_OK;
569 armv4_5_common_t *armv4_5 = target->arch_info;
570 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
571 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
572 arm920t_common_t *arm920t = arm9tdmi->arch_info;
573 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
575 if ((retval = target_halt(target)) != ERROR_OK)
580 long long then=timeval_ms();
582 while (!(timeout=((timeval_ms()-then)>1000)))
584 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
586 embeddedice_read_reg(dbg_stat);
587 if ((retval = jtag_execute_queue()) != ERROR_OK)
597 /* do not eat all CPU, time out after 1 se*/
606 LOG_ERROR("Failed to halt CPU after 1 sec");
607 return ERROR_TARGET_TIMEOUT;
610 target->state = TARGET_HALTED;
612 /* SVC, ARM state, IRQ and FIQ disabled */
613 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
614 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
615 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
617 /* start fetching from 0x0 */
618 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
619 armv4_5->core_cache->reg_list[15].dirty = 1;
620 armv4_5->core_cache->reg_list[15].valid = 1;
622 armv4_5->core_mode = ARMV4_5_MODE_SVC;
623 armv4_5->core_state = ARMV4_5_STATE_ARM;
625 arm920t_disable_mmu_caches(target, 1, 1, 1);
626 arm920t->armv4_5_mmu.mmu_enabled = 0;
627 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
628 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
630 if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
638 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
640 arm9tdmi_init_target(cmd_ctx, target);
645 int arm920t_quit(void)
650 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap_t *tap)
652 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
653 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
655 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
657 arm9tdmi_init_arch_info(target, arm9tdmi, tap);
659 arm9tdmi->arch_info = arm920t;
660 arm920t->common_magic = ARM920T_COMMON_MAGIC;
662 arm7_9->post_debug_entry = arm920t_post_debug_entry;
663 arm7_9->pre_restore_context = arm920t_pre_restore_context;
665 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
666 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
667 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
668 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
669 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
670 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
671 arm920t->armv4_5_mmu.has_tiny_pages = 1;
672 arm920t->armv4_5_mmu.mmu_enabled = 0;
674 /* disabling linefills leads to lockups, so keep them enabled for now
675 * this doesn't affect correctness, but might affect timing issues, if
676 * important data is evicted from the cache during the debug session
678 arm920t->preserve_cache = 0;
680 /* override hw single-step capability from ARM9TDMI */
681 arm7_9->has_single_step = 1;
686 int arm920t_target_create(struct target_s *target, Jim_Interp *interp)
688 arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t));
690 arm920t_init_arch_info(target, arm920t, target->tap);
695 int arm920t_register_commands(struct command_context_s *cmd_ctx)
698 command_t *arm920t_cmd;
701 retval = arm9tdmi_register_commands(cmd_ctx);
703 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
705 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
706 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
707 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
708 register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
710 register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
711 register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
712 register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
714 register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
715 register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
716 register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
718 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
719 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
724 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
726 int retval = ERROR_OK;
727 target_t *target = get_current_target(cmd_ctx);
728 armv4_5_common_t *armv4_5;
729 arm7_9_common_t *arm7_9;
730 arm9tdmi_common_t *arm9tdmi;
731 arm920t_common_t *arm920t;
732 arm_jtag_t *jtag_info;
734 u32 cp15_ctrl, cp15_ctrl_saved;
737 u32 C15_C_D_Ind, C15_C_I_Ind;
740 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
745 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
749 if ((output = fopen(args[0], "w")) == NULL)
751 LOG_DEBUG("error opening cache content file");
755 for (i = 0; i < 16; i++)
756 regs_p[i] = ®s[i];
758 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
760 command_print(cmd_ctx, "current target isn't an ARM920t target");
764 jtag_info = &arm7_9->jtag_info;
766 /* disable MMU and Caches */
767 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
768 if ((retval = jtag_execute_queue()) != ERROR_OK)
772 cp15_ctrl_saved = cp15_ctrl;
773 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
774 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
776 /* read CP15 test state register */
777 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
778 jtag_execute_queue();
780 /* read DCache content */
781 fprintf(output, "DCache:\n");
783 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
784 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
786 fprintf(output, "\nsegment: %i\n----------", segment);
788 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
789 regs[0] = 0x0 | (segment << 5);
790 arm9tdmi_write_core_regs(target, 0x1, regs);
792 /* set interpret mode */
794 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
796 /* D CAM Read, loads current victim into C15.C.D.Ind */
797 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
799 /* read current victim */
800 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
802 /* clear interpret mode */
804 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
806 for (index = 0; index < 64; index++)
808 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
809 regs[0] = 0x0 | (segment << 5) | (index << 26);
810 arm9tdmi_write_core_regs(target, 0x1, regs);
812 /* set interpret mode */
814 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
816 /* Write DCache victim */
817 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
820 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
823 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
825 /* clear interpret mode */
827 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
829 /* read D RAM and CAM content */
830 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
831 if ((retval = jtag_execute_queue()) != ERROR_OK)
836 d_cache[segment][index].cam = regs[9];
839 regs[9] &= 0xfffffffe;
840 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
842 for (i = 1; i < 9; i++)
844 d_cache[segment][index].data[i] = regs[i];
845 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
850 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
851 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
852 arm9tdmi_write_core_regs(target, 0x1, regs);
854 /* set interpret mode */
856 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
858 /* Write DCache victim */
859 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
861 /* clear interpret mode */
863 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
866 /* read ICache content */
867 fprintf(output, "ICache:\n");
869 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
870 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
872 fprintf(output, "segment: %i\n----------", segment);
874 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
875 regs[0] = 0x0 | (segment << 5);
876 arm9tdmi_write_core_regs(target, 0x1, regs);
878 /* set interpret mode */
880 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
882 /* I CAM Read, loads current victim into C15.C.I.Ind */
883 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
885 /* read current victim */
886 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
888 /* clear interpret mode */
890 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
892 for (index = 0; index < 64; index++)
894 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
895 regs[0] = 0x0 | (segment << 5) | (index << 26);
896 arm9tdmi_write_core_regs(target, 0x1, regs);
898 /* set interpret mode */
900 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
902 /* Write ICache victim */
903 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
906 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
909 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
911 /* clear interpret mode */
913 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
915 /* read I RAM and CAM content */
916 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
917 if ((retval = jtag_execute_queue()) != ERROR_OK)
922 i_cache[segment][index].cam = regs[9];
925 regs[9] &= 0xfffffffe;
926 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
928 for (i = 1; i < 9; i++)
930 i_cache[segment][index].data[i] = regs[i];
931 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
935 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
936 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
937 arm9tdmi_write_core_regs(target, 0x1, regs);
939 /* set interpret mode */
941 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
943 /* Write ICache victim */
944 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
946 /* clear interpret mode */
948 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
951 /* restore CP15 MMU and Cache settings */
952 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
954 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
958 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
961 /* mark registers dirty. */
962 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
963 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
964 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
965 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
966 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
967 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
968 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
969 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
970 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
971 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
976 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
978 int retval = ERROR_OK;
979 target_t *target = get_current_target(cmd_ctx);
980 armv4_5_common_t *armv4_5;
981 arm7_9_common_t *arm7_9;
982 arm9tdmi_common_t *arm9tdmi;
983 arm920t_common_t *arm920t;
984 arm_jtag_t *jtag_info;
986 u32 cp15_ctrl, cp15_ctrl_saved;
991 u32 Dlockdown, Ilockdown;
992 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
997 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1001 if ((output = fopen(args[0], "w")) == NULL)
1003 LOG_DEBUG("error opening mmu content file");
1007 for (i = 0; i < 16; i++)
1008 regs_p[i] = ®s[i];
1010 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1012 command_print(cmd_ctx, "current target isn't an ARM920t target");
1016 jtag_info = &arm7_9->jtag_info;
1018 /* disable MMU and Caches */
1019 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1020 if ((retval = jtag_execute_queue()) != ERROR_OK)
1024 cp15_ctrl_saved = cp15_ctrl;
1025 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1026 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1028 /* read CP15 test state register */
1029 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1030 if ((retval = jtag_execute_queue()) != ERROR_OK)
1035 /* prepare reading D TLB content
1038 /* set interpret mode */
1040 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1042 /* Read D TLB lockdown */
1043 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1045 /* clear interpret mode */
1047 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1049 /* read D TLB lockdown stored to r1 */
1050 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1051 if ((retval = jtag_execute_queue()) != ERROR_OK)
1055 Dlockdown = regs[1];
1057 for (victim = 0; victim < 64; victim += 8)
1059 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1060 * base remains unchanged, victim goes through entries 0 to 63 */
1061 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1062 arm9tdmi_write_core_regs(target, 0x2, regs);
1064 /* set interpret mode */
1066 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1068 /* Write D TLB lockdown */
1069 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1071 /* Read D TLB CAM */
1072 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1074 /* clear interpret mode */
1076 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1078 /* read D TLB CAM content stored to r2-r9 */
1079 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1080 if ((retval = jtag_execute_queue()) != ERROR_OK)
1085 for (i = 0; i < 8; i++)
1086 d_tlb[victim + i].cam = regs[i + 2];
1089 for (victim = 0; victim < 64; victim++)
1091 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1092 * base remains unchanged, victim goes through entries 0 to 63 */
1093 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1094 arm9tdmi_write_core_regs(target, 0x2, regs);
1096 /* set interpret mode */
1098 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1100 /* Write D TLB lockdown */
1101 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1103 /* Read D TLB RAM1 */
1104 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1106 /* Read D TLB RAM2 */
1107 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1109 /* clear interpret mode */
1111 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1113 /* read D TLB RAM content stored to r2 and r3 */
1114 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1115 if ((retval = jtag_execute_queue()) != ERROR_OK)
1120 d_tlb[victim].ram1 = regs[2];
1121 d_tlb[victim].ram2 = regs[3];
1124 /* restore D TLB lockdown */
1125 regs[1] = Dlockdown;
1126 arm9tdmi_write_core_regs(target, 0x2, regs);
1128 /* Write D TLB lockdown */
1129 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1131 /* prepare reading I TLB content
1134 /* set interpret mode */
1136 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1138 /* Read I TLB lockdown */
1139 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1141 /* clear interpret mode */
1143 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1145 /* read I TLB lockdown stored to r1 */
1146 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1147 if ((retval = jtag_execute_queue()) != ERROR_OK)
1151 Ilockdown = regs[1];
1153 for (victim = 0; victim < 64; victim += 8)
1155 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1156 * base remains unchanged, victim goes through entries 0 to 63 */
1157 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1158 arm9tdmi_write_core_regs(target, 0x2, regs);
1160 /* set interpret mode */
1162 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1164 /* Write I TLB lockdown */
1165 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1167 /* Read I TLB CAM */
1168 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1170 /* clear interpret mode */
1172 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1174 /* read I TLB CAM content stored to r2-r9 */
1175 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1176 if ((retval = jtag_execute_queue()) != ERROR_OK)
1181 for (i = 0; i < 8; i++)
1182 i_tlb[i + victim].cam = regs[i + 2];
1185 for (victim = 0; victim < 64; victim++)
1187 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1188 * base remains unchanged, victim goes through entries 0 to 63 */
1189 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1190 arm9tdmi_write_core_regs(target, 0x2, regs);
1192 /* set interpret mode */
1194 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1196 /* Write I TLB lockdown */
1197 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1199 /* Read I TLB RAM1 */
1200 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1202 /* Read I TLB RAM2 */
1203 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1205 /* clear interpret mode */
1207 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1209 /* read I TLB RAM content stored to r2 and r3 */
1210 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1211 if ((retval = jtag_execute_queue()) != ERROR_OK)
1216 i_tlb[victim].ram1 = regs[2];
1217 i_tlb[victim].ram2 = regs[3];
1220 /* restore I TLB lockdown */
1221 regs[1] = Ilockdown;
1222 arm9tdmi_write_core_regs(target, 0x2, regs);
1224 /* Write I TLB lockdown */
1225 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1227 /* restore CP15 MMU and Cache settings */
1228 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1230 /* output data to file */
1231 fprintf(output, "D TLB content:\n");
1232 for (i = 0; i < 64; i++)
1234 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1237 fprintf(output, "\n\nI TLB content:\n");
1238 for (i = 0; i < 64; i++)
1240 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1243 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1247 if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1250 /* mark registers dirty */
1251 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1252 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1253 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1254 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1255 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1256 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1257 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1258 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1259 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1260 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1264 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1267 target_t *target = get_current_target(cmd_ctx);
1268 armv4_5_common_t *armv4_5;
1269 arm7_9_common_t *arm7_9;
1270 arm9tdmi_common_t *arm9tdmi;
1271 arm920t_common_t *arm920t;
1272 arm_jtag_t *jtag_info;
1274 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1276 command_print(cmd_ctx, "current target isn't an ARM920t target");
1280 jtag_info = &arm7_9->jtag_info;
1282 if (target->state != TARGET_HALTED)
1284 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1288 /* one or more argument, access a single register (write if second argument is given */
1291 int address = strtoul(args[0], NULL, 0);
1296 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1298 command_print(cmd_ctx, "couldn't access reg %i", address);
1301 if ((retval = jtag_execute_queue()) != ERROR_OK)
1306 command_print(cmd_ctx, "%i: %8.8x", address, value);
1310 u32 value = strtoul(args[1], NULL, 0);
1311 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1313 command_print(cmd_ctx, "couldn't access reg %i", address);
1316 command_print(cmd_ctx, "%i: %8.8x", address, value);
1323 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1326 target_t *target = get_current_target(cmd_ctx);
1327 armv4_5_common_t *armv4_5;
1328 arm7_9_common_t *arm7_9;
1329 arm9tdmi_common_t *arm9tdmi;
1330 arm920t_common_t *arm920t;
1331 arm_jtag_t *jtag_info;
1333 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1335 command_print(cmd_ctx, "current target isn't an ARM920t target");
1339 jtag_info = &arm7_9->jtag_info;
1341 if (target->state != TARGET_HALTED)
1343 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1347 /* one or more argument, access a single register (write if second argument is given */
1350 u32 opcode = strtoul(args[0], NULL, 0);
1355 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1357 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1361 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1365 u32 value = strtoul(args[1], NULL, 0);
1366 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1368 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1371 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1375 u32 value = strtoul(args[1], NULL, 0);
1376 u32 address = strtoul(args[2], NULL, 0);
1377 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1379 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1382 command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1387 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1393 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1395 target_t *target = get_current_target(cmd_ctx);
1396 armv4_5_common_t *armv4_5;
1397 arm7_9_common_t *arm7_9;
1398 arm9tdmi_common_t *arm9tdmi;
1399 arm920t_common_t *arm920t;
1401 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1403 command_print(cmd_ctx, "current target isn't an ARM920t target");
1407 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1410 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1412 target_t *target = get_current_target(cmd_ctx);
1413 armv4_5_common_t *armv4_5;
1414 arm7_9_common_t *arm7_9;
1415 arm9tdmi_common_t *arm9tdmi;
1416 arm920t_common_t *arm920t;
1417 arm_jtag_t *jtag_info;
1419 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1421 command_print(cmd_ctx, "current target isn't an ARM920t target");
1425 jtag_info = &arm7_9->jtag_info;
1427 if (target->state != TARGET_HALTED)
1429 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1433 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1436 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1438 target_t *target = get_current_target(cmd_ctx);
1439 armv4_5_common_t *armv4_5;
1440 arm7_9_common_t *arm7_9;
1441 arm9tdmi_common_t *arm9tdmi;
1442 arm920t_common_t *arm920t;
1443 arm_jtag_t *jtag_info;
1445 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1447 command_print(cmd_ctx, "current target isn't an ARM920t target");
1451 jtag_info = &arm7_9->jtag_info;
1453 if (target->state != TARGET_HALTED)
1455 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1459 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1462 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1464 target_t *target = get_current_target(cmd_ctx);
1465 armv4_5_common_t *armv4_5;
1466 arm7_9_common_t *arm7_9;
1467 arm9tdmi_common_t *arm9tdmi;
1468 arm920t_common_t *arm920t;
1469 arm_jtag_t *jtag_info;
1471 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1473 command_print(cmd_ctx, "current target isn't an ARM920t target");
1477 jtag_info = &arm7_9->jtag_info;
1479 if (target->state != TARGET_HALTED)
1481 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1485 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);