1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 /* forward declarations */
49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size);
53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm920t_soft_reset_halt(struct target_s *target);
57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
59 target_type_t arm920t_target =
64 .arch_state = arm920t_arch_state,
66 .target_request_data = arm7_9_target_request_data,
69 .resume = arm7_9_resume,
72 .assert_reset = arm7_9_assert_reset,
73 .deassert_reset = arm7_9_deassert_reset,
74 .soft_reset_halt = arm920t_soft_reset_halt,
75 .prepare_reset_halt = arm7_9_prepare_reset_halt,
77 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
79 .read_memory = arm920t_read_memory,
80 .write_memory = arm920t_write_memory,
81 .bulk_write_memory = arm7_9_bulk_write_memory,
82 .checksum_memory = arm7_9_checksum_memory,
84 .run_algorithm = armv4_5_run_algorithm,
86 .add_breakpoint = arm7_9_add_breakpoint,
87 .remove_breakpoint = arm7_9_remove_breakpoint,
88 .add_watchpoint = arm7_9_add_watchpoint,
89 .remove_watchpoint = arm7_9_remove_watchpoint,
91 .register_commands = arm920t_register_commands,
92 .target_command = arm920t_target_command,
93 .init_target = arm920t_init_target,
97 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
99 armv4_5_common_t *armv4_5 = target->arch_info;
100 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
101 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
102 scan_field_t fields[4];
103 u8 access_type_buf = 1;
104 u8 reg_addr_buf = reg_addr & 0x3f;
107 jtag_add_end_state(TAP_RTI);
108 arm_jtag_scann(jtag_info, 0xf);
109 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
111 fields[0].device = jtag_info->chain_pos;
112 fields[0].num_bits = 1;
113 fields[0].out_value = &access_type_buf;
114 fields[0].out_mask = NULL;
115 fields[0].in_value = NULL;
116 fields[0].in_check_value = NULL;
117 fields[0].in_check_mask = NULL;
118 fields[0].in_handler = NULL;
119 fields[0].in_handler_priv = NULL;
121 fields[1].device = jtag_info->chain_pos;
122 fields[1].num_bits = 32;
123 fields[1].out_value = NULL;
124 fields[1].out_mask = NULL;
125 fields[1].in_value = NULL;
126 fields[1].in_check_value = NULL;
127 fields[1].in_check_mask = NULL;
128 fields[1].in_handler = NULL;
129 fields[1].in_handler_priv = NULL;
131 fields[2].device = jtag_info->chain_pos;
132 fields[2].num_bits = 6;
133 fields[2].out_value = ®_addr_buf;
134 fields[2].out_mask = NULL;
135 fields[2].in_value = NULL;
136 fields[2].in_check_value = NULL;
137 fields[2].in_check_mask = NULL;
138 fields[2].in_handler = NULL;
139 fields[2].in_handler_priv = NULL;
141 fields[3].device = jtag_info->chain_pos;
142 fields[3].num_bits = 1;
143 fields[3].out_value = &nr_w_buf;
144 fields[3].out_mask = NULL;
145 fields[3].in_value = NULL;
146 fields[3].in_check_value = NULL;
147 fields[3].in_check_mask = NULL;
148 fields[3].in_handler = NULL;
149 fields[3].in_handler_priv = NULL;
151 jtag_add_dr_scan(4, fields, -1, NULL);
153 fields[1].in_handler_priv = value;
154 fields[1].in_handler = arm_jtag_buf_to_u32;
156 jtag_add_dr_scan(4, fields, -1, NULL);
158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
159 jtag_execute_queue();
160 DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
166 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
168 armv4_5_common_t *armv4_5 = target->arch_info;
169 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
170 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
171 scan_field_t fields[4];
172 u8 access_type_buf = 1;
173 u8 reg_addr_buf = reg_addr & 0x3f;
177 buf_set_u32(value_buf, 0, 32, value);
179 jtag_add_end_state(TAP_RTI);
180 arm_jtag_scann(jtag_info, 0xf);
181 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
183 fields[0].device = jtag_info->chain_pos;
184 fields[0].num_bits = 1;
185 fields[0].out_value = &access_type_buf;
186 fields[0].out_mask = NULL;
187 fields[0].in_value = NULL;
188 fields[0].in_check_value = NULL;
189 fields[0].in_check_mask = NULL;
190 fields[0].in_handler = NULL;
191 fields[0].in_handler_priv = NULL;
193 fields[1].device = jtag_info->chain_pos;
194 fields[1].num_bits = 32;
195 fields[1].out_value = value_buf;
196 fields[1].out_mask = NULL;
197 fields[1].in_value = NULL;
198 fields[1].in_check_value = NULL;
199 fields[1].in_check_mask = NULL;
200 fields[1].in_handler = NULL;
201 fields[1].in_handler_priv = NULL;
203 fields[2].device = jtag_info->chain_pos;
204 fields[2].num_bits = 6;
205 fields[2].out_value = ®_addr_buf;
206 fields[2].out_mask = NULL;
207 fields[2].in_value = NULL;
208 fields[2].in_check_value = NULL;
209 fields[2].in_check_mask = NULL;
210 fields[2].in_handler = NULL;
211 fields[2].in_handler_priv = NULL;
213 fields[3].device = jtag_info->chain_pos;
214 fields[3].num_bits = 1;
215 fields[3].out_value = &nr_w_buf;
216 fields[3].out_mask = NULL;
217 fields[3].in_value = NULL;
218 fields[3].in_check_value = NULL;
219 fields[3].in_check_mask = NULL;
220 fields[3].in_handler = NULL;
221 fields[3].in_handler_priv = NULL;
223 jtag_add_dr_scan(4, fields, -1, NULL);
225 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
226 DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
232 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
234 armv4_5_common_t *armv4_5 = target->arch_info;
235 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
236 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
237 scan_field_t fields[4];
238 u8 access_type_buf = 0; /* interpreted access */
239 u8 reg_addr_buf = 0x0;
241 u8 cp15_opcode_buf[4];
243 jtag_add_end_state(TAP_RTI);
244 arm_jtag_scann(jtag_info, 0xf);
245 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
247 buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
249 fields[0].device = jtag_info->chain_pos;
250 fields[0].num_bits = 1;
251 fields[0].out_value = &access_type_buf;
252 fields[0].out_mask = NULL;
253 fields[0].in_value = NULL;
254 fields[0].in_check_value = NULL;
255 fields[0].in_check_mask = NULL;
256 fields[0].in_handler = NULL;
257 fields[0].in_handler_priv = NULL;
259 fields[1].device = jtag_info->chain_pos;
260 fields[1].num_bits = 32;
261 fields[1].out_value = cp15_opcode_buf;
262 fields[1].out_mask = NULL;
263 fields[1].in_value = NULL;
264 fields[1].in_check_value = NULL;
265 fields[1].in_check_mask = NULL;
266 fields[1].in_handler = NULL;
267 fields[1].in_handler_priv = NULL;
269 fields[2].device = jtag_info->chain_pos;
270 fields[2].num_bits = 6;
271 fields[2].out_value = ®_addr_buf;
272 fields[2].out_mask = NULL;
273 fields[2].in_value = NULL;
274 fields[2].in_check_value = NULL;
275 fields[2].in_check_mask = NULL;
276 fields[2].in_handler = NULL;
277 fields[2].in_handler_priv = NULL;
279 fields[3].device = jtag_info->chain_pos;
280 fields[3].num_bits = 1;
281 fields[3].out_value = &nr_w_buf;
282 fields[3].out_mask = NULL;
283 fields[3].in_value = NULL;
284 fields[3].in_check_value = NULL;
285 fields[3].in_check_mask = NULL;
286 fields[3].in_handler = NULL;
287 fields[3].in_handler_priv = NULL;
289 jtag_add_dr_scan(4, fields, -1, NULL);
291 arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
292 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
293 arm7_9_execute_sys_speed(target);
295 if (jtag_execute_queue() != ERROR_OK)
297 ERROR("failed executing JTAG queue, exiting");
304 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
306 armv4_5_common_t *armv4_5 = target->arch_info;
311 /* load address into R1 */
313 arm9tdmi_write_core_regs(target, 0x2, regs);
315 /* read-modify-write CP15 test state register
316 * to enable interpreted access mode */
317 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
318 jtag_execute_queue();
319 cp15c15 |= 1; /* set interpret mode */
320 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
322 /* execute CP15 instruction and ARM load (reading from coprocessor) */
323 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
325 /* disable interpreted access mode */
326 cp15c15 &= ~1U; /* clear interpret mode */
327 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
329 /* retrieve value from R0 */
331 arm9tdmi_read_core_regs(target, 0x1, regs_p);
332 jtag_execute_queue();
334 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
335 DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
338 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
339 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
344 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
347 armv4_5_common_t *armv4_5 = target->arch_info;
350 /* load value, address into R0, R1 */
353 arm9tdmi_write_core_regs(target, 0x3, regs);
355 /* read-modify-write CP15 test state register
356 * to enable interpreted access mode */
357 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
358 jtag_execute_queue();
359 cp15c15 |= 1; /* set interpret mode */
360 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
362 /* execute CP15 instruction and ARM store (writing to coprocessor) */
363 arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
365 /* disable interpreted access mode */
366 cp15c15 &= ~1U; /* set interpret mode */
367 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
369 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
370 DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
373 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
374 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
379 u32 arm920t_get_ttb(target_t *target)
384 if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
390 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
394 /* read cp15 control register */
395 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
396 jtag_execute_queue();
399 cp15_control &= ~0x1U;
402 cp15_control &= ~0x4U;
405 cp15_control &= ~0x1000U;
407 arm920t_write_cp15_physical(target, 0x2, cp15_control);
410 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
414 /* read cp15 control register */
415 arm920t_read_cp15_physical(target, 0x2, &cp15_control);
416 jtag_execute_queue();
419 cp15_control |= 0x1U;
422 cp15_control |= 0x4U;
425 cp15_control |= 0x1000U;
427 arm920t_write_cp15_physical(target, 0x2, cp15_control);
430 void arm920t_post_debug_entry(target_t *target)
433 armv4_5_common_t *armv4_5 = target->arch_info;
434 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
435 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
436 arm920t_common_t *arm920t = arm9tdmi->arch_info;
438 /* examine cp15 control reg */
439 arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
440 jtag_execute_queue();
441 DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
443 if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
446 /* identify caches */
447 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
448 jtag_execute_queue();
449 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
452 arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
453 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
454 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
456 /* save i/d fault status and address register */
457 arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
458 arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
459 arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
460 arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
462 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
463 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
465 if (arm920t->preserve_cache)
467 /* read-modify-write CP15 test state register
468 * to disable I/D-cache linefills */
469 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
470 jtag_execute_queue();
472 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
476 void arm920t_pre_restore_context(target_t *target)
479 armv4_5_common_t *armv4_5 = target->arch_info;
480 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
481 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
482 arm920t_common_t *arm920t = arm9tdmi->arch_info;
484 /* restore i/d fault status and address register */
485 arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
486 arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
487 arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
488 arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
490 /* read-modify-write CP15 test state register
491 * to reenable I/D-cache linefills */
492 if (arm920t->preserve_cache)
494 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
495 jtag_execute_queue();
497 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
501 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
503 armv4_5_common_t *armv4_5 = target->arch_info;
504 arm7_9_common_t *arm7_9;
505 arm9tdmi_common_t *arm9tdmi;
506 arm920t_common_t *arm920t;
508 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
513 arm7_9 = armv4_5->arch_info;
514 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
519 arm9tdmi = arm7_9->arch_info;
520 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
525 arm920t = arm9tdmi->arch_info;
526 if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
531 *armv4_5_p = armv4_5;
533 *arm9tdmi_p = arm9tdmi;
534 *arm920t_p = arm920t;
539 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
541 armv4_5_common_t *armv4_5 = target->arch_info;
542 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
543 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
544 arm920t_common_t *arm920t = arm9tdmi->arch_info;
548 "disabled", "enabled"
551 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
553 ERROR("BUG: called for a non-ARMv4/5 target");
557 snprintf(buf, buf_size,
558 "target halted in %s state due to %s, current mode: %s\n"
559 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
560 "MMU: %s, D-Cache: %s, I-Cache: %s",
561 armv4_5_state_strings[armv4_5->core_state],
562 target_debug_reason_strings[target->debug_reason],
563 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
564 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
565 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
566 state[arm920t->armv4_5_mmu.mmu_enabled],
567 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
568 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
573 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
577 retval = arm7_9_read_memory(target, address, size, count, buffer);
582 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
585 armv4_5_common_t *armv4_5 = target->arch_info;
586 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
587 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
588 arm920t_common_t *arm920t = arm9tdmi->arch_info;
590 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
593 if (((size == 4) || (size == 2)) && (count == 1))
595 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
597 DEBUG("D-Cache enabled, writing through to main memory");
601 pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
604 /* cacheable & bufferable means write-back region */
606 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
609 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
611 DEBUG("I-Cache enabled, invalidating affected I-Cache line");
612 arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
619 int arm920t_soft_reset_halt(struct target_s *target)
621 armv4_5_common_t *armv4_5 = target->arch_info;
622 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
623 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
624 arm920t_common_t *arm920t = arm9tdmi->arch_info;
625 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
627 if (target->state == TARGET_RUNNING)
629 target->type->halt(target);
632 while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
634 embeddedice_read_reg(dbg_stat);
635 jtag_execute_queue();
638 target->state = TARGET_HALTED;
640 /* SVC, ARM state, IRQ and FIQ disabled */
641 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
642 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
643 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
645 /* start fetching from 0x0 */
646 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
647 armv4_5->core_cache->reg_list[15].dirty = 1;
648 armv4_5->core_cache->reg_list[15].valid = 1;
650 armv4_5->core_mode = ARMV4_5_MODE_SVC;
651 armv4_5->core_state = ARMV4_5_STATE_ARM;
653 arm920t_disable_mmu_caches(target, 1, 1, 1);
654 arm920t->armv4_5_mmu.mmu_enabled = 0;
655 arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
656 arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
658 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
663 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
665 arm9tdmi_init_target(cmd_ctx, target);
677 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
679 arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
680 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
682 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
684 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
686 arm9tdmi->arch_info = arm920t;
687 arm920t->common_magic = ARM920T_COMMON_MAGIC;
689 arm7_9->post_debug_entry = arm920t_post_debug_entry;
690 arm7_9->pre_restore_context = arm920t_pre_restore_context;
692 arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
693 arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
694 arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
695 arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
696 arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
697 arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
698 arm920t->armv4_5_mmu.has_tiny_pages = 1;
699 arm920t->armv4_5_mmu.mmu_enabled = 0;
701 /* disabling linefills leads to lockups, so keep them enabled for now
702 * this doesn't affect correctness, but might affect timing issues, if
703 * important data is evicted from the cache during the debug session
705 arm920t->preserve_cache = 0;
707 /* override hw single-step capability from ARM9TDMI */
708 arm7_9->has_single_step = 1;
713 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
716 char *variant = NULL;
717 arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
721 ERROR("'target arm920t' requires at least one additional argument");
725 chain_pos = strtoul(args[3], NULL, 0);
730 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
732 arm920t_init_arch_info(target, arm920t, chain_pos, variant);
737 int arm920t_register_commands(struct command_context_s *cmd_ctx)
740 command_t *arm920t_cmd;
743 retval = arm9tdmi_register_commands(cmd_ctx);
745 arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
747 register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
748 register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
749 register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
750 register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
752 register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
753 register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
754 register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
756 register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
757 register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
758 register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
760 register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
761 register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
766 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
768 target_t *target = get_current_target(cmd_ctx);
769 armv4_5_common_t *armv4_5;
770 arm7_9_common_t *arm7_9;
771 arm9tdmi_common_t *arm9tdmi;
772 arm920t_common_t *arm920t;
773 arm_jtag_t *jtag_info;
775 u32 cp15_ctrl, cp15_ctrl_saved;
778 u32 C15_C_D_Ind, C15_C_I_Ind;
781 arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
786 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
790 if ((output = fopen(args[0], "w")) == NULL)
792 DEBUG("error opening cache content file");
796 for (i = 0; i < 16; i++)
797 regs_p[i] = ®s[i];
799 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
801 command_print(cmd_ctx, "current target isn't an ARM920t target");
805 jtag_info = &arm7_9->jtag_info;
807 /* disable MMU and Caches */
808 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
809 jtag_execute_queue();
810 cp15_ctrl_saved = cp15_ctrl;
811 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
812 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
814 /* read CP15 test state register */
815 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
816 jtag_execute_queue();
818 /* read DCache content */
819 fprintf(output, "DCache:\n");
821 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
822 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
824 fprintf(output, "\nsegment: %i\n----------", segment);
826 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
827 regs[0] = 0x0 | (segment << 5);
828 arm9tdmi_write_core_regs(target, 0x1, regs);
830 /* set interpret mode */
832 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
834 /* D CAM Read, loads current victim into C15.C.D.Ind */
835 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
837 /* read current victim */
838 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
840 /* clear interpret mode */
842 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
844 for (index = 0; index < 64; index++)
846 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
847 regs[0] = 0x0 | (segment << 5) | (index << 26);
848 arm9tdmi_write_core_regs(target, 0x1, regs);
850 /* set interpret mode */
852 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
854 /* Write DCache victim */
855 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
858 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
861 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
863 /* clear interpret mode */
865 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
867 /* read D RAM and CAM content */
868 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
869 jtag_execute_queue();
871 d_cache[segment][index].cam = regs[9];
874 regs[9] &= 0xfffffffe;
875 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
877 for (i = 1; i < 9; i++)
879 d_cache[segment][index].data[i] = regs[i];
880 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
885 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
886 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
887 arm9tdmi_write_core_regs(target, 0x1, regs);
889 /* set interpret mode */
891 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
893 /* Write DCache victim */
894 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
896 /* clear interpret mode */
898 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
901 /* read ICache content */
902 fprintf(output, "ICache:\n");
904 /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
905 for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
907 fprintf(output, "segment: %i\n----------", segment);
909 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
910 regs[0] = 0x0 | (segment << 5);
911 arm9tdmi_write_core_regs(target, 0x1, regs);
913 /* set interpret mode */
915 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
917 /* I CAM Read, loads current victim into C15.C.I.Ind */
918 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
920 /* read current victim */
921 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
923 /* clear interpret mode */
925 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
927 for (index = 0; index < 64; index++)
929 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
930 regs[0] = 0x0 | (segment << 5) | (index << 26);
931 arm9tdmi_write_core_regs(target, 0x1, regs);
933 /* set interpret mode */
935 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
937 /* Write ICache victim */
938 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
941 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
944 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
946 /* clear interpret mode */
948 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
950 /* read I RAM and CAM content */
951 arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
952 jtag_execute_queue();
954 i_cache[segment][index].cam = regs[9];
957 regs[9] &= 0xfffffffe;
958 fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
960 for (i = 1; i < 9; i++)
962 i_cache[segment][index].data[i] = regs[i];
963 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
969 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
970 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
971 arm9tdmi_write_core_regs(target, 0x1, regs);
973 /* set interpret mode */
975 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
977 /* Write ICache victim */
978 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
980 /* clear interpret mode */
982 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
985 /* restore CP15 MMU and Cache settings */
986 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
988 command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
992 /* mark registers dirty. */
993 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
994 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
995 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
996 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
997 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
998 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
999 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1000 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1001 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1002 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1007 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1009 target_t *target = get_current_target(cmd_ctx);
1010 armv4_5_common_t *armv4_5;
1011 arm7_9_common_t *arm7_9;
1012 arm9tdmi_common_t *arm9tdmi;
1013 arm920t_common_t *arm920t;
1014 arm_jtag_t *jtag_info;
1016 u32 cp15_ctrl, cp15_ctrl_saved;
1021 u32 Dlockdown, Ilockdown;
1022 arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1027 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1031 if ((output = fopen(args[0], "w")) == NULL)
1033 DEBUG("error opening mmu content file");
1037 for (i = 0; i < 16; i++)
1038 regs_p[i] = ®s[i];
1040 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1042 command_print(cmd_ctx, "current target isn't an ARM920t target");
1046 jtag_info = &arm7_9->jtag_info;
1048 /* disable MMU and Caches */
1049 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1050 jtag_execute_queue();
1051 cp15_ctrl_saved = cp15_ctrl;
1052 cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1053 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1055 /* read CP15 test state register */
1056 arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1057 jtag_execute_queue();
1059 /* prepare reading D TLB content
1062 /* set interpret mode */
1064 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1066 /* Read D TLB lockdown */
1067 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1069 /* clear interpret mode */
1071 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1073 /* read D TLB lockdown stored to r1 */
1074 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1075 jtag_execute_queue();
1076 Dlockdown = regs[1];
1078 for (victim = 0; victim < 64; victim += 8)
1080 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1081 * base remains unchanged, victim goes through entries 0 to 63 */
1082 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1083 arm9tdmi_write_core_regs(target, 0x2, regs);
1085 /* set interpret mode */
1087 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1089 /* Write D TLB lockdown */
1090 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1092 /* Read D TLB CAM */
1093 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1095 /* clear interpret mode */
1097 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1099 /* read D TLB CAM content stored to r2-r9 */
1100 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1101 jtag_execute_queue();
1103 for (i = 0; i < 8; i++)
1104 d_tlb[victim + i].cam = regs[i + 2];
1107 for (victim = 0; victim < 64; victim++)
1109 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1110 * base remains unchanged, victim goes through entries 0 to 63 */
1111 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1112 arm9tdmi_write_core_regs(target, 0x2, regs);
1114 /* set interpret mode */
1116 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1118 /* Write D TLB lockdown */
1119 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1121 /* Read D TLB RAM1 */
1122 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1124 /* Read D TLB RAM2 */
1125 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1127 /* clear interpret mode */
1129 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1131 /* read D TLB RAM content stored to r2 and r3 */
1132 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1133 jtag_execute_queue();
1135 d_tlb[victim].ram1 = regs[2];
1136 d_tlb[victim].ram2 = regs[3];
1139 /* restore D TLB lockdown */
1140 regs[1] = Dlockdown;
1141 arm9tdmi_write_core_regs(target, 0x2, regs);
1143 /* Write D TLB lockdown */
1144 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1146 /* prepare reading I TLB content
1149 /* set interpret mode */
1151 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1153 /* Read I TLB lockdown */
1154 arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1156 /* clear interpret mode */
1158 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1160 /* read I TLB lockdown stored to r1 */
1161 arm9tdmi_read_core_regs(target, 0x2, regs_p);
1162 jtag_execute_queue();
1163 Ilockdown = regs[1];
1165 for (victim = 0; victim < 64; victim += 8)
1167 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1168 * base remains unchanged, victim goes through entries 0 to 63 */
1169 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1170 arm9tdmi_write_core_regs(target, 0x2, regs);
1172 /* set interpret mode */
1174 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1176 /* Write I TLB lockdown */
1177 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1179 /* Read I TLB CAM */
1180 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1182 /* clear interpret mode */
1184 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1186 /* read I TLB CAM content stored to r2-r9 */
1187 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1188 jtag_execute_queue();
1190 for (i = 0; i < 8; i++)
1191 i_tlb[i + victim].cam = regs[i + 2];
1194 for (victim = 0; victim < 64; victim++)
1196 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1197 * base remains unchanged, victim goes through entries 0 to 63 */
1198 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1199 arm9tdmi_write_core_regs(target, 0x2, regs);
1201 /* set interpret mode */
1203 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1205 /* Write I TLB lockdown */
1206 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1208 /* Read I TLB RAM1 */
1209 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1211 /* Read I TLB RAM2 */
1212 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1214 /* clear interpret mode */
1216 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1218 /* read I TLB RAM content stored to r2 and r3 */
1219 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1220 jtag_execute_queue();
1222 i_tlb[victim].ram1 = regs[2];
1223 i_tlb[victim].ram2 = regs[3];
1226 /* restore I TLB lockdown */
1227 regs[1] = Ilockdown;
1228 arm9tdmi_write_core_regs(target, 0x2, regs);
1230 /* Write I TLB lockdown */
1231 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1233 /* restore CP15 MMU and Cache settings */
1234 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1236 /* output data to file */
1237 fprintf(output, "D TLB content:\n");
1238 for (i = 0; i < 64; i++)
1240 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1243 fprintf(output, "\n\nI TLB content:\n");
1244 for (i = 0; i < 64; i++)
1246 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1249 command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1253 /* mark registers dirty */
1254 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1255 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1256 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1257 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1258 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1259 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1260 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1261 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1262 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1263 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1267 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1270 target_t *target = get_current_target(cmd_ctx);
1271 armv4_5_common_t *armv4_5;
1272 arm7_9_common_t *arm7_9;
1273 arm9tdmi_common_t *arm9tdmi;
1274 arm920t_common_t *arm920t;
1275 arm_jtag_t *jtag_info;
1277 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1279 command_print(cmd_ctx, "current target isn't an ARM920t target");
1283 jtag_info = &arm7_9->jtag_info;
1285 if (target->state != TARGET_HALTED)
1287 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1291 /* one or more argument, access a single register (write if second argument is given */
1294 int address = strtoul(args[0], NULL, 0);
1299 if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1301 command_print(cmd_ctx, "couldn't access reg %i", address);
1304 jtag_execute_queue();
1306 command_print(cmd_ctx, "%i: %8.8x", address, value);
1310 u32 value = strtoul(args[1], NULL, 0);
1311 if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1313 command_print(cmd_ctx, "couldn't access reg %i", address);
1316 command_print(cmd_ctx, "%i: %8.8x", address, value);
1323 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1326 target_t *target = get_current_target(cmd_ctx);
1327 armv4_5_common_t *armv4_5;
1328 arm7_9_common_t *arm7_9;
1329 arm9tdmi_common_t *arm9tdmi;
1330 arm920t_common_t *arm920t;
1331 arm_jtag_t *jtag_info;
1333 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1335 command_print(cmd_ctx, "current target isn't an ARM920t target");
1339 jtag_info = &arm7_9->jtag_info;
1341 if (target->state != TARGET_HALTED)
1343 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1347 /* one or more argument, access a single register (write if second argument is given */
1350 u32 opcode = strtoul(args[0], NULL, 0);
1355 if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1357 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1361 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1365 u32 value = strtoul(args[1], NULL, 0);
1366 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1368 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1371 command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1375 u32 value = strtoul(args[1], NULL, 0);
1376 u32 address = strtoul(args[2], NULL, 0);
1377 if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1379 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1382 command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1387 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1393 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1395 target_t *target = get_current_target(cmd_ctx);
1396 armv4_5_common_t *armv4_5;
1397 arm7_9_common_t *arm7_9;
1398 arm9tdmi_common_t *arm9tdmi;
1399 arm920t_common_t *arm920t;
1401 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1403 command_print(cmd_ctx, "current target isn't an ARM920t target");
1407 return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1410 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1412 target_t *target = get_current_target(cmd_ctx);
1413 armv4_5_common_t *armv4_5;
1414 arm7_9_common_t *arm7_9;
1415 arm9tdmi_common_t *arm9tdmi;
1416 arm920t_common_t *arm920t;
1417 arm_jtag_t *jtag_info;
1419 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1421 command_print(cmd_ctx, "current target isn't an ARM920t target");
1425 jtag_info = &arm7_9->jtag_info;
1427 if (target->state != TARGET_HALTED)
1429 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1433 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1436 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1438 target_t *target = get_current_target(cmd_ctx);
1439 armv4_5_common_t *armv4_5;
1440 arm7_9_common_t *arm7_9;
1441 arm9tdmi_common_t *arm9tdmi;
1442 arm920t_common_t *arm920t;
1443 arm_jtag_t *jtag_info;
1445 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1447 command_print(cmd_ctx, "current target isn't an ARM920t target");
1451 jtag_info = &arm7_9->jtag_info;
1453 if (target->state != TARGET_HALTED)
1455 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1459 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1462 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1464 target_t *target = get_current_target(cmd_ctx);
1465 armv4_5_common_t *armv4_5;
1466 arm7_9_common_t *arm7_9;
1467 arm9tdmi_common_t *arm9tdmi;
1468 arm920t_common_t *arm920t;
1469 arm_jtag_t *jtag_info;
1471 if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1473 command_print(cmd_ctx, "current target isn't an ARM920t target");
1477 jtag_info = &arm7_9->jtag_info;
1479 if (target->state != TARGET_HALTED)
1481 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1485 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);