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fixed gaffe: disable interrupts reset init script
[openocd] / src / target / arm926ejs.c
1 /***************************************************************************
2  *   Copyright (C) 2007 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm926ejs.h"
25 #include "jtag.h"
26 #include "log.h"
27 #include "time_support.h"
28
29 #include <stdlib.h>
30 #include <string.h>
31
32 #if 0
33 #define _DEBUG_INSTRUCTION_EXECUTION_
34 #endif
35
36 /* cli handling */
37 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
38
39 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45
46 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48
49 /* forward declarations */
50 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
51 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 int arm926ejs_quit(void);
53 int arm926ejs_arch_state(struct target_s *target);
54 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
56 int arm926ejs_soft_reset_halt(struct target_s *target);
57 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
58 static int arm926ejs_mmu(struct target_s *target, int *enabled);
59
60 target_type_t arm926ejs_target =
61 {
62         .name = "arm926ejs",
63
64         .poll = arm7_9_poll,
65         .arch_state = arm926ejs_arch_state,
66
67         .target_request_data = arm7_9_target_request_data,
68
69         .halt = arm7_9_halt,
70         .resume = arm7_9_resume,
71         .step = arm7_9_step,
72
73         .assert_reset = arm7_9_assert_reset,
74         .deassert_reset = arm7_9_deassert_reset,
75         .soft_reset_halt = arm926ejs_soft_reset_halt,
76         
77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
78
79         .read_memory = arm7_9_read_memory,
80         .write_memory = arm926ejs_write_memory,
81         .bulk_write_memory = arm7_9_bulk_write_memory,
82         .checksum_memory = arm7_9_checksum_memory,
83         .blank_check_memory = arm7_9_blank_check_memory,
84         
85         .run_algorithm = armv4_5_run_algorithm,
86
87         .add_breakpoint = arm7_9_add_breakpoint,
88         .remove_breakpoint = arm7_9_remove_breakpoint,
89         .add_watchpoint = arm7_9_add_watchpoint,
90         .remove_watchpoint = arm7_9_remove_watchpoint,
91
92         .register_commands = arm926ejs_register_commands,
93         .target_create = arm926ejs_target_create,
94         .init_target = arm926ejs_init_target,
95         .examine = arm9tdmi_examine,
96         .quit = arm926ejs_quit,
97         .virt2phys = arm926ejs_virt2phys,
98         .mmu = arm926ejs_mmu
99 };
100
101
102 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
103 {
104         /* The ARM926EJ-S' instruction register is 4 bits wide */
105         u8 t = *captured & 0xf;
106         u8 t2 = *field->in_check_value & 0xf;
107         if (t == t2)
108         {
109                 return ERROR_OK;
110         }
111         else if ((t == 0x0f) || (t == 0x00))
112         {
113                 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
114                 return ERROR_OK;
115         }
116         return ERROR_JTAG_QUEUE_FAILED;;
117 }
118
119 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
120
121 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
122 {
123         armv4_5_common_t *armv4_5 = target->arch_info;
124         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
125         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
126         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
127         scan_field_t fields[4];
128         u8 address_buf[2];
129         u8 nr_w_buf = 0;
130         u8 access = 1;
131         
132         buf_set_u32(address_buf, 0, 14, address);
133         
134         jtag_add_end_state(TAP_RTI);
135         arm_jtag_scann(jtag_info, 0xf);
136         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
137
138         fields[0].device = jtag_info->chain_pos;
139         fields[0].num_bits = 32;
140         fields[0].out_value = NULL;
141         fields[0].out_mask = NULL;
142         fields[0].in_value = NULL;
143         fields[0].in_check_value = NULL;
144         fields[0].in_check_mask = NULL;
145         fields[0].in_handler = NULL;
146         fields[0].in_handler_priv = NULL;
147
148         fields[1].device = jtag_info->chain_pos;
149         fields[1].num_bits = 1;
150         fields[1].out_value = &access;
151         fields[1].out_mask = NULL;
152         fields[1].in_value = &access;
153         fields[1].in_check_value = NULL;
154         fields[1].in_check_mask = NULL;
155         fields[1].in_handler = NULL;
156         fields[1].in_handler_priv = NULL;
157
158         fields[2].device = jtag_info->chain_pos;
159         fields[2].num_bits = 14;
160         fields[2].out_value = address_buf;
161         fields[2].out_mask = NULL;
162         fields[2].in_value = NULL;
163         fields[2].in_check_value = NULL;
164         fields[2].in_check_mask = NULL;
165         fields[2].in_handler = NULL;
166         fields[2].in_handler_priv = NULL;
167
168         fields[3].device = jtag_info->chain_pos;
169         fields[3].num_bits = 1;
170         fields[3].out_value = &nr_w_buf;
171         fields[3].out_mask = NULL;
172         fields[3].in_value = NULL;
173         fields[3].in_check_value = NULL;
174         fields[3].in_check_mask = NULL;
175         fields[3].in_handler = NULL;
176         fields[3].in_handler_priv = NULL;
177         
178         jtag_add_dr_scan(4, fields, -1);
179
180         fields[0].in_handler_priv = value;
181         fields[0].in_handler = arm_jtag_buf_to_u32;
182         
183         /*TODO: add timeout*/
184         do
185         {
186                 /* rescan with NOP, to wait for the access to complete */
187                 access = 0;
188                 nr_w_buf = 0;
189                 jtag_add_dr_scan(4, fields, -1);
190                 jtag_execute_queue();
191         } while (buf_get_u32(&access, 0, 1) != 1);
192
193 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
194         LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
195 #endif
196         
197         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
198
199         return ERROR_OK;
200 }
201
202 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
203 {
204         armv4_5_common_t *armv4_5 = target->arch_info;
205         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
206         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
207         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
208         scan_field_t fields[4];
209         u8 value_buf[4];
210         u8 address_buf[2];
211         u8 nr_w_buf = 1;
212         u8 access = 1;
213         
214         buf_set_u32(address_buf, 0, 14, address);
215         buf_set_u32(value_buf, 0, 32, value);
216         
217         jtag_add_end_state(TAP_RTI);
218         arm_jtag_scann(jtag_info, 0xf);
219         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
220
221         fields[0].device = jtag_info->chain_pos;
222         fields[0].num_bits = 32;
223         fields[0].out_value = value_buf;
224         fields[0].out_mask = NULL;
225         fields[0].in_value = NULL;
226         fields[0].in_check_value = NULL;
227         fields[0].in_check_mask = NULL;
228         fields[0].in_handler = NULL;
229         fields[0].in_handler_priv = NULL;
230
231         fields[1].device = jtag_info->chain_pos;
232         fields[1].num_bits = 1;
233         fields[1].out_value = &access;
234         fields[1].out_mask = NULL;
235         fields[1].in_value = &access;
236         fields[1].in_check_value = NULL;
237         fields[1].in_check_mask = NULL;
238         fields[1].in_handler = NULL;
239         fields[1].in_handler_priv = NULL;
240
241         fields[2].device = jtag_info->chain_pos;
242         fields[2].num_bits = 14;
243         fields[2].out_value = address_buf;
244         fields[2].out_mask = NULL;
245         fields[2].in_value = NULL;
246         fields[2].in_check_value = NULL;
247         fields[2].in_check_mask = NULL;
248         fields[2].in_handler = NULL;
249         fields[2].in_handler_priv = NULL;
250
251         fields[3].device = jtag_info->chain_pos;
252         fields[3].num_bits = 1;
253         fields[3].out_value = &nr_w_buf;
254         fields[3].out_mask = NULL;
255         fields[3].in_value = NULL;
256         fields[3].in_check_value = NULL;
257         fields[3].in_check_mask = NULL;
258         fields[3].in_handler = NULL;
259         fields[3].in_handler_priv = NULL;
260         
261         jtag_add_dr_scan(4, fields, -1);
262         /*TODO: add timeout*/
263         do
264         {
265                 /* rescan with NOP, to wait for the access to complete */
266                 access = 0;
267                 nr_w_buf = 0;
268                 jtag_add_dr_scan(4, fields, -1);
269                 jtag_execute_queue();
270         } while (buf_get_u32(&access, 0, 1) != 1);
271
272 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
273         LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
274 #endif
275
276         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
277
278         return ERROR_OK;
279 }
280
281 int arm926ejs_examine_debug_reason(target_t *target)
282 {
283         armv4_5_common_t *armv4_5 = target->arch_info;
284         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
285         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
286         int debug_reason;
287         int retval;
288
289         embeddedice_read_reg(dbg_stat);
290         if ((retval = jtag_execute_queue()) != ERROR_OK)
291                 return retval;
292         
293         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
294         
295         switch (debug_reason)
296         {
297                 case 1:
298                         LOG_DEBUG("breakpoint from EICE unit 0");
299                         target->debug_reason = DBG_REASON_BREAKPOINT;
300                         break;
301                 case 2:
302                         LOG_DEBUG("breakpoint from EICE unit 1");
303                         target->debug_reason = DBG_REASON_BREAKPOINT;
304                         break;
305                 case 3:
306                         LOG_DEBUG("soft breakpoint (BKPT instruction)");
307                         target->debug_reason = DBG_REASON_BREAKPOINT;
308                         break;
309                 case 4:
310                         LOG_DEBUG("vector catch breakpoint");
311                         target->debug_reason = DBG_REASON_BREAKPOINT;
312                         break;
313                 case 5:
314                         LOG_DEBUG("external breakpoint");
315                         target->debug_reason = DBG_REASON_BREAKPOINT;
316                         break;
317                 case 6:
318                         LOG_DEBUG("watchpoint from EICE unit 0");
319                         target->debug_reason = DBG_REASON_WATCHPOINT;
320                         break;
321                 case 7:
322                         LOG_DEBUG("watchpoint from EICE unit 1");
323                         target->debug_reason = DBG_REASON_WATCHPOINT;
324                         break;
325                 case 8:
326                         LOG_DEBUG("external watchpoint");
327                         target->debug_reason = DBG_REASON_WATCHPOINT;
328                         break;
329                 case 9:
330                         LOG_DEBUG("internal debug request");
331                         target->debug_reason = DBG_REASON_DBGRQ;
332                         break;
333                 case 10:
334                         LOG_DEBUG("external debug request");
335                         target->debug_reason = DBG_REASON_DBGRQ;
336                         break;
337                 case 11:
338                         LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
339                         break;
340                 default:
341                         LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
342                         target->debug_reason = DBG_REASON_DBGRQ;
343                         retval = ERROR_TARGET_FAILURE;
344                         break;
345         }
346         
347         return retval;
348 }
349
350 u32 arm926ejs_get_ttb(target_t *target)
351 {
352         armv4_5_common_t *armv4_5 = target->arch_info;
353         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
354         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
355         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
356         int retval;
357         u32 ttb = 0x0;
358
359         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
360                 return retval;
361
362         return ttb;
363 }
364
365 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
366 {
367         armv4_5_common_t *armv4_5 = target->arch_info;
368         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
369         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
370         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
371         u32 cp15_control;
372
373         /* read cp15 control register */
374         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
375         jtag_execute_queue();
376         
377         if (mmu)
378         {
379                 /* invalidate TLB */
380                 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
381                 
382                 cp15_control &= ~0x1U;
383         }
384         
385         if (d_u_cache)
386         {
387                 u32 debug_override;
388                 /* read-modify-write CP15 debug override register 
389                  * to enable "test and clean all" */
390                 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
391                 debug_override |= 0x80000;
392                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
393                 
394                 /* clean and invalidate DCache */
395                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
396
397                 /* write CP15 debug override register 
398                  * to disable "test and clean all" */
399                 debug_override &= ~0x80000;
400                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
401                 
402                 cp15_control &= ~0x4U;
403         }
404         
405         if (i_cache)
406         {
407                 /* invalidate ICache */
408                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
409                 
410                 cp15_control &= ~0x1000U;
411         }
412         
413         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
414 }
415
416 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
417 {
418         armv4_5_common_t *armv4_5 = target->arch_info;
419         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
420         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
421         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
422         u32 cp15_control;
423
424         /* read cp15 control register */
425         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
426         jtag_execute_queue();
427                 
428         if (mmu)
429                 cp15_control |= 0x1U;
430         
431         if (d_u_cache)
432                 cp15_control |= 0x4U;
433         
434         if (i_cache)
435                 cp15_control |= 0x1000U;
436         
437         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
438 }
439
440 void arm926ejs_post_debug_entry(target_t *target)
441 {
442         armv4_5_common_t *armv4_5 = target->arch_info;
443         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
444         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
445         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
446
447         /* examine cp15 control reg */
448         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
449         jtag_execute_queue();
450         LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
451
452         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
453         {
454                 u32 cache_type_reg;
455                 /* identify caches */
456                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
457                 jtag_execute_queue();
458                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
459         }
460
461         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
462         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
463         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
464
465         /* save i/d fault status and address register */
466         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
467         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
468         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
469         
470         LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
471                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);  
472
473
474         u32 cache_dbg_ctrl;
475         
476         /* read-modify-write CP15 cache debug control register 
477          * to disable I/D-cache linefills and force WT */
478         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
479         cache_dbg_ctrl |= 0x7;
480         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
481 }
482
483 void arm926ejs_pre_restore_context(target_t *target)
484 {
485         armv4_5_common_t *armv4_5 = target->arch_info;
486         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
487         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
488         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
489
490         /* restore i/d fault status and address register */
491         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
492         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
493         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
494         
495         u32 cache_dbg_ctrl;
496         
497         /* read-modify-write CP15 cache debug control register 
498          * to reenable I/D-cache linefills and disable WT */
499         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
500         cache_dbg_ctrl &= ~0x7;
501         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
502 }
503
504 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
505 {
506         armv4_5_common_t *armv4_5 = target->arch_info;
507         arm7_9_common_t *arm7_9;
508         arm9tdmi_common_t *arm9tdmi;
509         arm926ejs_common_t *arm926ejs;
510         
511         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
512         {
513                 return -1;
514         }
515         
516         arm7_9 = armv4_5->arch_info;
517         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
518         {
519                 return -1;
520         }
521         
522         arm9tdmi = arm7_9->arch_info;
523         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
524         {
525                 return -1;
526         }
527         
528         arm926ejs = arm9tdmi->arch_info;
529         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
530         {
531                 return -1;
532         }
533         
534         *armv4_5_p = armv4_5;
535         *arm7_9_p = arm7_9;
536         *arm9tdmi_p = arm9tdmi;
537         *arm926ejs_p = arm926ejs;
538         
539         return ERROR_OK;
540 }
541
542 int arm926ejs_arch_state(struct target_s *target)
543 {
544         armv4_5_common_t *armv4_5 = target->arch_info;
545         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
546         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
547         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
548         
549         char *state[] = 
550         {
551                 "disabled", "enabled"
552         };
553         
554         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
555         {
556                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
557                 exit(-1);
558         }
559         
560         LOG_USER(
561                         "target halted in %s state due to %s, current mode: %s\n"
562                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
563                         "MMU: %s, D-Cache: %s, I-Cache: %s",
564                          armv4_5_state_strings[armv4_5->core_state],
565                          Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
566                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
567                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
568                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
569                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
570                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], 
571                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
572         
573         return ERROR_OK;
574 }
575
576 int arm926ejs_soft_reset_halt(struct target_s *target)
577 {
578         armv4_5_common_t *armv4_5 = target->arch_info;
579         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
580         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
581         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
582         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
583         
584         target_halt(target);
585         
586         long long then=timeval_ms();
587         int timeout;
588         while (!(timeout=((timeval_ms()-then)>1000)))
589         {
590                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
591                 {
592                         embeddedice_read_reg(dbg_stat);
593                         jtag_execute_queue();
594                 }  else
595                 {
596                         break;
597                 }
598                 if (debug_level>=1)
599                 {
600                         /* do not eat all CPU, time out after 1 se*/
601                         alive_sleep(100);
602                 } else
603                 {
604                         keep_alive();
605                 }
606         }
607         if (timeout)
608         {
609                 LOG_ERROR("Failed to halt CPU after 1 sec");
610                 return ERROR_TARGET_TIMEOUT;
611         }
612         
613         target->state = TARGET_HALTED;
614         
615         /* SVC, ARM state, IRQ and FIQ disabled */
616         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
617         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
618         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
619         
620         /* start fetching from 0x0 */
621         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
622         armv4_5->core_cache->reg_list[15].dirty = 1;
623         armv4_5->core_cache->reg_list[15].valid = 1;
624         
625         armv4_5->core_mode = ARMV4_5_MODE_SVC;
626         armv4_5->core_state = ARMV4_5_STATE_ARM;
627         
628         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
629         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
630         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
631         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
632
633         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
634         
635         return ERROR_OK;
636 }
637
638 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
639 {
640         int retval;
641         armv4_5_common_t *armv4_5 = target->arch_info;
642         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
643         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
644         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
645         
646         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
647                 return retval;
648
649         /* If ICache is enabled, we have to invalidate affected ICache lines
650          * the DCache is forced to write-through, so we don't have to clean it here
651          */
652         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
653         {
654                 if (count <= 1)
655                 {
656                         /* invalidate ICache single entry with MVA */
657                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
658                 }
659                 else
660                 {
661                         /* invalidate ICache */
662                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
663                 }
664         }
665
666         return retval;
667 }
668
669 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
670 {
671         arm9tdmi_init_target(cmd_ctx, target);
672                 
673         return ERROR_OK;
674         
675 }
676
677 int arm926ejs_quit(void)
678 {
679         
680         return ERROR_OK;
681 }
682
683 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant)
684 {
685         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
686         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
687         
688         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
689          */
690         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
691
692         arm9tdmi->arch_info = arm926ejs;
693         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
694         
695         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
696         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
697         
698         arm926ejs->read_cp15 = arm926ejs_cp15_read;
699         arm926ejs->write_cp15 = arm926ejs_cp15_write;
700         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
701         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
702         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
703         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
704         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
705         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
706         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
707         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
708         
709         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
710         
711         /* The ARM926EJ-S implements the ARMv5TE architecture which
712          * has the BKPT instruction, so we don't have to use a watchpoint comparator
713          */
714         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
715         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
716         
717         return ERROR_OK;
718 }
719
720 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
721 {
722         arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
723         
724         arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
725
726         return ERROR_OK;
727 }
728
729 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
730 {
731         int retval;
732         command_t *arm926ejs_cmd;
733         
734                 
735         retval = arm9tdmi_register_commands(cmd_ctx);
736         
737         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
738
739         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
740         
741         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
742         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
743
744         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
745         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
746         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
747
748         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
749         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
750         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
751
752         return ERROR_OK;
753 }
754
755 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
756 {
757         int retval;
758         target_t *target = get_current_target(cmd_ctx);
759         armv4_5_common_t *armv4_5;
760         arm7_9_common_t *arm7_9;
761         arm9tdmi_common_t *arm9tdmi;
762         arm926ejs_common_t *arm926ejs;
763         int opcode_1;
764         int opcode_2;
765         int CRn;
766         int CRm;
767
768         if ((argc < 4) || (argc > 5))
769         {
770                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
771                 return ERROR_OK;
772         }
773         
774         opcode_1 = strtoul(args[0], NULL, 0);
775         opcode_2 = strtoul(args[1], NULL, 0);
776         CRn = strtoul(args[2], NULL, 0);
777         CRm = strtoul(args[3], NULL, 0);
778
779         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
780         {
781                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
782                 return ERROR_OK;
783         }
784         
785         if (target->state != TARGET_HALTED)
786         {
787                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
788                 return ERROR_OK;
789         }
790         
791         if (argc == 4)
792         {
793                 u32 value;
794                 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
795                 {
796                         command_print(cmd_ctx, "couldn't access register");
797                         return ERROR_OK;
798                 }
799                 jtag_execute_queue();
800                 
801                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
802         }
803         else
804         {
805                 u32 value = strtoul(args[4], NULL, 0);
806                 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
807                 {
808                         command_print(cmd_ctx, "couldn't access register");
809                         return ERROR_OK;
810                 }
811                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
812         }
813
814         return ERROR_OK;
815 }
816
817 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
818 {
819         target_t *target = get_current_target(cmd_ctx);
820         armv4_5_common_t *armv4_5;
821         arm7_9_common_t *arm7_9;
822         arm9tdmi_common_t *arm9tdmi;
823         arm926ejs_common_t *arm926ejs;
824         
825         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
826         {
827                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
828                 return ERROR_OK;
829         }
830         
831         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
832 }
833
834 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
835 {       
836         target_t *target = get_current_target(cmd_ctx);
837         armv4_5_common_t *armv4_5;
838         arm7_9_common_t *arm7_9;
839         arm9tdmi_common_t *arm9tdmi;
840         arm926ejs_common_t *arm926ejs;
841         arm_jtag_t *jtag_info;
842
843         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
844         {
845                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
846                 return ERROR_OK;
847         }
848         
849         jtag_info = &arm7_9->jtag_info;
850         
851         if (target->state != TARGET_HALTED)
852         {
853                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
854                 return ERROR_OK;
855         }
856                 
857         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
858 }
859
860 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
861 {       
862         target_t *target = get_current_target(cmd_ctx);
863         armv4_5_common_t *armv4_5;
864         arm7_9_common_t *arm7_9;
865         arm9tdmi_common_t *arm9tdmi;
866         arm926ejs_common_t *arm926ejs;
867         arm_jtag_t *jtag_info;
868
869         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
870         {
871                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
872                 return ERROR_OK;
873         }
874         
875         jtag_info = &arm7_9->jtag_info;
876         
877         if (target->state != TARGET_HALTED)
878         {
879                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
880                 return ERROR_OK;
881         }
882         
883         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
884 }
885
886 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
887 {       
888         target_t *target = get_current_target(cmd_ctx);
889         armv4_5_common_t *armv4_5;
890         arm7_9_common_t *arm7_9;
891         arm9tdmi_common_t *arm9tdmi;
892         arm926ejs_common_t *arm926ejs;
893         arm_jtag_t *jtag_info;
894
895         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
896         {
897                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
898                 return ERROR_OK;
899         }
900         
901         jtag_info = &arm7_9->jtag_info;
902         
903         if (target->state != TARGET_HALTED)
904         {
905                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
906                 return ERROR_OK;
907         }
908         
909         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
910 }
911 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
912 {
913         int retval;
914         int type;
915         u32 cb;
916         int domain;
917         u32 ap;
918         
919         armv4_5_common_t *armv4_5;
920         arm7_9_common_t *arm7_9;
921         arm9tdmi_common_t *arm9tdmi;
922         arm926ejs_common_t *arm926ejs;
923         retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
924         if (retval != ERROR_OK)
925         {
926                 return retval;
927         }
928         u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
929         if (type == -1)
930         {
931                 return ret;
932         }
933         *physical = ret;
934         return ERROR_OK;
935 }
936
937 static int arm926ejs_mmu(struct target_s *target, int *enabled)
938 {
939         armv4_5_common_t *armv4_5 = target->arch_info;
940         arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
941         
942         if (target->state != TARGET_HALTED)
943         {
944                 LOG_ERROR("Target not halted");
945                 return ERROR_TARGET_INVALID;
946         }
947         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
948         return ERROR_OK;
949 }