1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2007,2008,2009 by Øyvind Harboe *
6 * oyvind.harboe@zylin.com *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "arm926ejs.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
31 #include "arm_opcodes.h"
35 * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
36 * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
37 * the ARM926 manual (ARM DDI 0198E). The scan chains are:
39 * 1 ... core debugging
41 * 3 ... external boundary scan (SoC-specific, unused here)
43 * 15 ... coprocessor 15
47 #define _DEBUG_INSTRUCTION_EXECUTION_
50 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
52 static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2,
53 uint32_t CRn, uint32_t CRm, uint32_t *value)
55 int retval = ERROR_OK;
56 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
57 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
58 uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
59 struct scan_field fields[4];
60 uint8_t address_buf[2] = {0, 0};
64 buf_set_u32(address_buf, 0, 14, address);
66 jtag_set_end_state(TAP_IDLE);
67 if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
71 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
73 fields[0].tap = jtag_info->tap;
74 fields[0].num_bits = 32;
75 fields[0].out_value = NULL;
76 fields[0].in_value = (uint8_t *)value;
79 fields[1].tap = jtag_info->tap;
80 fields[1].num_bits = 1;
81 fields[1].out_value = &access;
82 fields[1].in_value = &access;
84 fields[2].tap = jtag_info->tap;
85 fields[2].num_bits = 14;
86 fields[2].out_value = address_buf;
87 fields[2].in_value = NULL;
89 fields[3].tap = jtag_info->tap;
90 fields[3].num_bits = 1;
91 fields[3].out_value = &nr_w_buf;
92 fields[3].in_value = NULL;
94 jtag_add_dr_scan(4, fields, jtag_get_end_state());
96 long long then = timeval_ms();
100 /* rescan with NOP, to wait for the access to complete */
103 jtag_add_dr_scan(4, fields, jtag_get_end_state());
105 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
107 if ((retval = jtag_execute_queue()) != ERROR_OK)
112 if (buf_get_u32(&access, 0, 1) == 1)
118 if ((timeval_ms()-then)>10)
120 LOG_ERROR("cp15 read operation timed out");
125 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
126 LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
129 arm_jtag_set_instr(jtag_info, 0xc, NULL);
134 static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1,
135 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
138 LOG_ERROR("Only cp15 is supported");
141 return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
144 static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2,
145 uint32_t CRn, uint32_t CRm, uint32_t value)
147 int retval = ERROR_OK;
148 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
149 struct arm_jtag *jtag_info = &arm7_9->jtag_info;
150 uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
151 struct scan_field fields[4];
152 uint8_t value_buf[4];
153 uint8_t address_buf[2] = {0, 0};
154 uint8_t nr_w_buf = 1;
157 buf_set_u32(address_buf, 0, 14, address);
158 buf_set_u32(value_buf, 0, 32, value);
160 jtag_set_end_state(TAP_IDLE);
161 if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
165 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
167 fields[0].tap = jtag_info->tap;
168 fields[0].num_bits = 32;
169 fields[0].out_value = value_buf;
170 fields[0].in_value = NULL;
172 fields[1].tap = jtag_info->tap;
173 fields[1].num_bits = 1;
174 fields[1].out_value = &access;
175 fields[1].in_value = &access;
177 fields[2].tap = jtag_info->tap;
178 fields[2].num_bits = 14;
179 fields[2].out_value = address_buf;
180 fields[2].in_value = NULL;
182 fields[3].tap = jtag_info->tap;
183 fields[3].num_bits = 1;
184 fields[3].out_value = &nr_w_buf;
185 fields[3].in_value = NULL;
187 jtag_add_dr_scan(4, fields, jtag_get_end_state());
189 long long then = timeval_ms();
193 /* rescan with NOP, to wait for the access to complete */
196 jtag_add_dr_scan(4, fields, jtag_get_end_state());
197 if ((retval = jtag_execute_queue()) != ERROR_OK)
202 if (buf_get_u32(&access, 0, 1) == 1)
208 if ((timeval_ms()-then)>10)
210 LOG_ERROR("cp15 write operation timed out");
215 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
216 LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
219 arm_jtag_set_instr(jtag_info, 0xf, NULL);
224 static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1,
225 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
228 LOG_ERROR("Only cp15 is supported");
231 return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
234 static int arm926ejs_examine_debug_reason(struct target *target)
236 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
237 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
241 embeddedice_read_reg(dbg_stat);
242 if ((retval = jtag_execute_queue()) != ERROR_OK)
245 /* Method-Of-Entry (MOE) field */
246 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
248 switch (debug_reason)
251 LOG_DEBUG("no *NEW* debug entry (?missed one?)");
252 /* ... since last restart or debug reset ... */
253 target->debug_reason = DBG_REASON_DBGRQ;
256 LOG_DEBUG("breakpoint from EICE unit 0");
257 target->debug_reason = DBG_REASON_BREAKPOINT;
260 LOG_DEBUG("breakpoint from EICE unit 1");
261 target->debug_reason = DBG_REASON_BREAKPOINT;
264 LOG_DEBUG("soft breakpoint (BKPT instruction)");
265 target->debug_reason = DBG_REASON_BREAKPOINT;
268 LOG_DEBUG("vector catch breakpoint");
269 target->debug_reason = DBG_REASON_BREAKPOINT;
272 LOG_DEBUG("external breakpoint");
273 target->debug_reason = DBG_REASON_BREAKPOINT;
276 LOG_DEBUG("watchpoint from EICE unit 0");
277 target->debug_reason = DBG_REASON_WATCHPOINT;
280 LOG_DEBUG("watchpoint from EICE unit 1");
281 target->debug_reason = DBG_REASON_WATCHPOINT;
284 LOG_DEBUG("external watchpoint");
285 target->debug_reason = DBG_REASON_WATCHPOINT;
288 LOG_DEBUG("internal debug request");
289 target->debug_reason = DBG_REASON_DBGRQ;
292 LOG_DEBUG("external debug request");
293 target->debug_reason = DBG_REASON_DBGRQ;
296 LOG_DEBUG("debug re-entry from system speed access");
297 /* This is normal when connecting to something that's
298 * already halted, or in some related code paths, but
299 * otherwise is surprising (and presumably wrong).
301 switch (target->debug_reason) {
302 case DBG_REASON_DBGRQ:
305 LOG_ERROR("unexpected -- debug re-entry");
307 case DBG_REASON_UNDEFINED:
308 target->debug_reason = DBG_REASON_DBGRQ;
313 /* FIX!!!! here be dragons!!! We need to fail here so
314 * the target will interpreted as halted but we won't
315 * try to talk to it right now... a resume + halt seems
316 * to sync things up again. Please send an email to
317 * openocd development mailing list if you have hardware
318 * to donate to look into this problem....
320 LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
321 target->debug_reason = DBG_REASON_DBGRQ;
324 LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
325 /* Oh agony! should we interpret this as a halt request or
326 * that the target stopped on it's own accord?
328 target->debug_reason = DBG_REASON_DBGRQ;
329 /* if we fail here, we won't talk to the target and it will
330 * be reported to be in the halted state */
337 static uint32_t arm926ejs_get_ttb(struct target *target)
339 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
343 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
349 static void arm926ejs_disable_mmu_caches(struct target *target, int mmu,
350 int d_u_cache, int i_cache)
352 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
353 uint32_t cp15_control;
355 /* read cp15 control register */
356 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
357 jtag_execute_queue();
362 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
364 cp15_control &= ~0x1U;
369 uint32_t debug_override;
370 /* read-modify-write CP15 debug override register
371 * to enable "test and clean all" */
372 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
373 debug_override |= 0x80000;
374 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
376 /* clean and invalidate DCache */
377 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
379 /* write CP15 debug override register
380 * to disable "test and clean all" */
381 debug_override &= ~0x80000;
382 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
384 cp15_control &= ~0x4U;
389 /* invalidate ICache */
390 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
392 cp15_control &= ~0x1000U;
395 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
398 static void arm926ejs_enable_mmu_caches(struct target *target, int mmu,
399 int d_u_cache, int i_cache)
401 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
402 uint32_t cp15_control;
404 /* read cp15 control register */
405 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
406 jtag_execute_queue();
409 cp15_control |= 0x1U;
412 cp15_control |= 0x4U;
415 cp15_control |= 0x1000U;
417 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
420 static void arm926ejs_post_debug_entry(struct target *target)
422 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
424 /* examine cp15 control reg */
425 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
426 jtag_execute_queue();
427 LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
429 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
431 uint32_t cache_type_reg;
432 /* identify caches */
433 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
434 jtag_execute_queue();
435 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
438 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
439 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
440 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
442 /* save i/d fault status and address register */
443 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
444 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
445 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
447 LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
448 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
450 uint32_t cache_dbg_ctrl;
452 /* read-modify-write CP15 cache debug control register
453 * to disable I/D-cache linefills and force WT */
454 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
455 cache_dbg_ctrl |= 0x7;
456 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
459 static void arm926ejs_pre_restore_context(struct target *target)
461 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
463 /* restore i/d fault status and address register */
464 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
465 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
466 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
468 uint32_t cache_dbg_ctrl;
470 /* read-modify-write CP15 cache debug control register
471 * to reenable I/D-cache linefills and disable WT */
472 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
473 cache_dbg_ctrl &= ~0x7;
474 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
477 static const char arm926_not[] = "target is not an ARM926";
479 static int arm926ejs_verify_pointer(struct command_context *cmd_ctx,
480 struct arm926ejs_common *arm926)
482 if (arm926->common_magic != ARM926EJS_COMMON_MAGIC) {
483 command_print(cmd_ctx, arm926_not);
484 return ERROR_TARGET_INVALID;
489 /** Logs summary of ARM926 state for a halted target. */
490 int arm926ejs_arch_state(struct target *target)
492 static const char *state[] =
494 "disabled", "enabled"
497 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
500 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
502 LOG_ERROR("BUG: %s", arm926_not);
503 return ERROR_TARGET_INVALID;
506 armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
508 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
509 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
510 "MMU: %s, D-Cache: %s, I-Cache: %s",
511 arm_state_strings[armv4_5->core_state],
512 Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
513 arm_mode_name(armv4_5->core_mode),
514 buf_get_u32(armv4_5->cpsr->value, 0, 32),
515 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
516 state[arm926ejs->armv4_5_mmu.mmu_enabled],
517 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
518 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
523 int arm926ejs_soft_reset_halt(struct target *target)
525 int retval = ERROR_OK;
526 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
527 struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
528 struct arm *armv4_5 = &arm7_9->armv4_5_common;
529 struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
531 if ((retval = target_halt(target)) != ERROR_OK)
536 long long then = timeval_ms();
538 while (!(timeout = ((timeval_ms()-then) > 1000)))
540 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
542 embeddedice_read_reg(dbg_stat);
543 if ((retval = jtag_execute_queue()) != ERROR_OK)
551 if (debug_level >= 1)
553 /* do not eat all CPU, time out after 1 se*/
562 LOG_ERROR("Failed to halt CPU after 1 sec");
563 return ERROR_TARGET_TIMEOUT;
566 target->state = TARGET_HALTED;
568 /* SVC, ARM state, IRQ and FIQ disabled */
571 cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
574 arm_set_cpsr(armv4_5, cpsr);
575 armv4_5->cpsr->dirty = 1;
577 /* start fetching from 0x0 */
578 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
579 armv4_5->core_cache->reg_list[15].dirty = 1;
580 armv4_5->core_cache->reg_list[15].valid = 1;
582 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
583 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
584 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
585 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
587 return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
590 /** Writes a buffer, in the specified word size, with current MMU settings. */
591 int arm926ejs_write_memory(struct target *target, uint32_t address,
592 uint32_t size, uint32_t count, uint8_t *buffer)
595 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
597 /* FIX!!!! this should be cleaned up and made much more general. The
598 * plan is to write up and test on arm926ejs specifically and
599 * then generalize and clean up afterwards. */
600 if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
602 /* special case the handling of single word writes to bypass MMU
603 * to allow implementation of breakpoints in memory marked read only
605 if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
607 /* flush and invalidate data cache
609 * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
612 retval = arm926ejs->write_cp15(target, 0, 1, 7, 10, address&~0x3);
613 if (retval != ERROR_OK)
618 retval = target->type->virt2phys(target, address, &pa);
619 if (retval != ERROR_OK)
622 /* write directly to physical memory bypassing any read only MMU bits, etc. */
623 retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
624 if (retval != ERROR_OK)
628 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
632 /* If ICache is enabled, we have to invalidate affected ICache lines
633 * the DCache is forced to write-through, so we don't have to clean it here
635 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
639 /* invalidate ICache single entry with MVA */
640 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
644 /* invalidate ICache */
645 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
652 static int arm926ejs_write_phys_memory(struct target *target,
653 uint32_t address, uint32_t size,
654 uint32_t count, uint8_t *buffer)
656 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
658 return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu,
659 address, size, count, buffer);
662 static int arm926ejs_read_phys_memory(struct target *target,
663 uint32_t address, uint32_t size,
664 uint32_t count, uint8_t *buffer)
666 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
668 return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu,
669 address, size, count, buffer);
672 int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs,
673 struct jtag_tap *tap)
675 struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
677 arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
678 arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
680 /* initialize arm7/arm9 specific info (including armv4_5) */
681 arm9tdmi_init_arch_info(target, arm7_9, tap);
683 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
685 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
686 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
688 arm926ejs->read_cp15 = arm926ejs_cp15_read;
689 arm926ejs->write_cp15 = arm926ejs_cp15_write;
690 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
691 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
692 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
693 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
694 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
695 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
696 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
697 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
699 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
701 /* The ARM926EJ-S implements the ARMv5TE architecture which
702 * has the BKPT instruction, so we don't have to use a watchpoint comparator
704 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
705 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
710 static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
712 struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
714 /* ARM9EJ-S core always reports 0x1 in Capture-IR */
715 target->tap->ir_capture_mask = 0x0f;
717 return arm926ejs_init_arch_info(target, arm926ejs, target->tap);
720 COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
723 struct target *target = get_current_target(CMD_CTX);
724 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
726 retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs);
727 if (retval != ERROR_OK)
730 return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache);
733 static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical)
739 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
741 uint32_t ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
750 static int arm926ejs_mmu(struct target *target, int *enabled)
752 struct arm926ejs_common *arm926ejs = target_to_arm926(target);
754 if (target->state != TARGET_HALTED)
756 LOG_ERROR("Target not halted");
757 return ERROR_TARGET_INVALID;
759 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
763 static const struct command_registration arm926ejs_exec_command_handlers[] = {
765 .name = "cache_info",
766 .handler = &arm926ejs_handle_cache_info_command,
767 .mode = COMMAND_EXEC,
768 .help = "display information about target caches",
771 COMMAND_REGISTRATION_DONE
773 const struct command_registration arm926ejs_command_handlers[] = {
775 .chain = arm9tdmi_command_handlers,
780 .help = "arm926ejs command group",
781 .chain = arm926ejs_exec_command_handlers,
783 COMMAND_REGISTRATION_DONE
786 /** Holds methods for ARM926 targets. */
787 struct target_type arm926ejs_target =
792 .arch_state = arm926ejs_arch_state,
794 .target_request_data = arm7_9_target_request_data,
797 .resume = arm7_9_resume,
800 .assert_reset = arm7_9_assert_reset,
801 .deassert_reset = arm7_9_deassert_reset,
802 .soft_reset_halt = arm926ejs_soft_reset_halt,
804 .get_gdb_reg_list = arm_get_gdb_reg_list,
806 .read_memory = arm7_9_read_memory,
807 .write_memory = arm926ejs_write_memory,
808 .bulk_write_memory = arm7_9_bulk_write_memory,
810 .checksum_memory = arm_checksum_memory,
811 .blank_check_memory = arm_blank_check_memory,
813 .run_algorithm = armv4_5_run_algorithm,
815 .add_breakpoint = arm7_9_add_breakpoint,
816 .remove_breakpoint = arm7_9_remove_breakpoint,
817 .add_watchpoint = arm7_9_add_watchpoint,
818 .remove_watchpoint = arm7_9_remove_watchpoint,
820 .commands = arm926ejs_command_handlers,
821 .target_create = arm926ejs_target_create,
822 .init_target = arm9tdmi_init_target,
823 .examine = arm7_9_examine,
824 .virt2phys = arm926ejs_virt2phys,
825 .mmu = arm926ejs_mmu,
827 .read_phys_memory = arm926ejs_read_phys_memory,
828 .write_phys_memory = arm926ejs_write_phys_memory,