git.sur5r.net Git - openocd/blob - src/target/arm926ejs.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm926ejs.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27 #include "time_support.h"
  28
  29 #include <stdlib.h>
  30 #include <string.h>
  31
  32 #if 0
  33 #define _DEBUG_INSTRUCTION_EXECUTION_
  34 #endif
  35
  36 /* cli handling */
  37 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46
  47 /* forward declarations */
  48 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
  49 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  50 int arm926ejs_quit(void);
  51 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  52
  53 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
  54 static int arm926ejs_mmu(struct target_s *target, int *enabled);
  55
  56 target_type_t arm926ejs_target =
  57 {
  58         .name = "arm926ejs",
  59
  60         .poll = arm7_9_poll,
  61         .arch_state = arm926ejs_arch_state,
  62
  63         .target_request_data = arm7_9_target_request_data,
  64
  65         .halt = arm7_9_halt,
  66         .resume = arm7_9_resume,
  67         .step = arm7_9_step,
  68
  69         .assert_reset = arm7_9_assert_reset,
  70         .deassert_reset = arm7_9_deassert_reset,
  71         .soft_reset_halt = arm926ejs_soft_reset_halt,
  72
  73         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  74
  75         .read_memory = arm7_9_read_memory,
  76         .write_memory = arm926ejs_write_memory,
  77         .bulk_write_memory = arm7_9_bulk_write_memory,
  78         .checksum_memory = arm7_9_checksum_memory,
  79         .blank_check_memory = arm7_9_blank_check_memory,
  80
  81         .run_algorithm = armv4_5_run_algorithm,
  82
  83         .add_breakpoint = arm7_9_add_breakpoint,
  84         .remove_breakpoint = arm7_9_remove_breakpoint,
  85         .add_watchpoint = arm7_9_add_watchpoint,
  86         .remove_watchpoint = arm7_9_remove_watchpoint,
  87
  88         .register_commands = arm926ejs_register_commands,
  89         .target_create = arm926ejs_target_create,
  90         .init_target = arm926ejs_init_target,
  91         .examine = arm9tdmi_examine,
  92         .quit = arm926ejs_quit,
  93         .virt2phys = arm926ejs_virt2phys,
  94         .mmu = arm926ejs_mmu
  95 };
  96
  97 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
  98 {
  99         /* FIX!!!! this code should be reenabled. For now it does not check
 100          * the queue...*/
 101         return 0;
 102 #if 0
 103         /* The ARM926EJ-S' instruction register is 4 bits wide */
 104         u8 t = *captured & 0xf;
 105         u8 t2 = *field->in_check_value & 0xf;
 106         if (t == t2)
 107         {
 108                 return ERROR_OK;
 109         }
 110         else if ((t == 0x0f) || (t == 0x00))
 111         {
 112                 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 113                 return ERROR_OK;
 114         }
 115         return ERROR_JTAG_QUEUE_FAILED;;
 116 #endif
 117 }
 118
 119 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
 120
 121 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
 122 {
 123         int retval = ERROR_OK;
 124         armv4_5_common_t *armv4_5 = target->arch_info;
 125         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 126         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 127         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 128         scan_field_t fields[4];
 129         u8 address_buf[2];
 130         u8 nr_w_buf = 0;
 131         u8 access = 1;
 132
 133         buf_set_u32(address_buf, 0, 14, address);
 134
 135         jtag_add_end_state(TAP_IDLE);
 136         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 137         {
 138                 return retval;
 139         }
 140         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 141
 142         fields[0].tap = jtag_info->tap;
 143         fields[0].num_bits = 32;
 144         fields[0].out_value = NULL;
 145         u8 tmp[4];
 146         fields[0].in_value = tmp;
 147
 148
 149         fields[1].tap = jtag_info->tap;
 150         fields[1].num_bits = 1;
 151         fields[1].out_value = &access;
 152         fields[1].in_value = &access;
 153
 154         fields[2].tap = jtag_info->tap;
 155         fields[2].num_bits = 14;
 156         fields[2].out_value = address_buf;
 157         fields[2].in_value = NULL;
 158
 159         fields[3].tap = jtag_info->tap;
 160         fields[3].num_bits = 1;
 161         fields[3].out_value = &nr_w_buf;
 162         fields[3].in_value = NULL;
 163
 164         jtag_add_dr_scan(4, fields, TAP_INVALID);
 165
 166         /*TODO: add timeout*/
 167         do
 168         {
 169                 /* rescan with NOP, to wait for the access to complete */
 170                 access = 0;
 171                 nr_w_buf = 0;
 172                 jtag_add_dr_scan_now(4, fields, TAP_INVALID);
 173
 174                 *value=le_to_h_u32(tmp);
 175
 176                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 177                 {
 178                         return retval;
 179                 }
 180         } while (buf_get_u32(&access, 0, 1) != 1);
 181
 182 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 183         LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 184 #endif
 185
 186         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 187
 188         return ERROR_OK;
 189 }
 190
 191 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
 192 {
 193         int retval = ERROR_OK;
 194         armv4_5_common_t *armv4_5 = target->arch_info;
 195         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 196         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 197         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 198         scan_field_t fields[4];
 199         u8 value_buf[4];
 200         u8 address_buf[2];
 201         u8 nr_w_buf = 1;
 202         u8 access = 1;
 203
 204         buf_set_u32(address_buf, 0, 14, address);
 205         buf_set_u32(value_buf, 0, 32, value);
 206
 207         jtag_add_end_state(TAP_IDLE);
 208         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 209         {
 210                 return retval;
 211         }
 212         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 213
 214         fields[0].tap = jtag_info->tap;
 215         fields[0].num_bits = 32;
 216         fields[0].out_value = value_buf;
 217         fields[0].in_value = NULL;
 218
 219         fields[1].tap = jtag_info->tap;
 220         fields[1].num_bits = 1;
 221         fields[1].out_value = &access;
 222         fields[1].in_value = &access;
 223
 224         fields[2].tap = jtag_info->tap;
 225         fields[2].num_bits = 14;
 226         fields[2].out_value = address_buf;
 227         fields[2].in_value = NULL;
 228
 229         fields[3].tap = jtag_info->tap;
 230         fields[3].num_bits = 1;
 231         fields[3].out_value = &nr_w_buf;
 232         fields[3].in_value = NULL;
 233
 234         jtag_add_dr_scan(4, fields, TAP_INVALID);
 235         /*TODO: add timeout*/
 236         do
 237         {
 238                 /* rescan with NOP, to wait for the access to complete */
 239                 access = 0;
 240                 nr_w_buf = 0;
 241                 jtag_add_dr_scan(4, fields, TAP_INVALID);
 242                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 243                 {
 244                         return retval;
 245                 }
 246         } while (buf_get_u32(&access, 0, 1) != 1);
 247
 248 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 249         LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 250 #endif
 251
 252         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 253
 254         return ERROR_OK;
 255 }
 256
 257 int arm926ejs_examine_debug_reason(target_t *target)
 258 {
 259         armv4_5_common_t *armv4_5 = target->arch_info;
 260         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 261         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 262         int debug_reason;
 263         int retval;
 264
 265         embeddedice_read_reg(dbg_stat);
 266         if ((retval = jtag_execute_queue()) != ERROR_OK)
 267                 return retval;
 268
 269         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 270
 271         switch (debug_reason)
 272         {
 273                 case 1:
 274                         LOG_DEBUG("breakpoint from EICE unit 0");
 275                         target->debug_reason = DBG_REASON_BREAKPOINT;
 276                         break;
 277                 case 2:
 278                         LOG_DEBUG("breakpoint from EICE unit 1");
 279                         target->debug_reason = DBG_REASON_BREAKPOINT;
 280                         break;
 281                 case 3:
 282                         LOG_DEBUG("soft breakpoint (BKPT instruction)");
 283                         target->debug_reason = DBG_REASON_BREAKPOINT;
 284                         break;
 285                 case 4:
 286                         LOG_DEBUG("vector catch breakpoint");
 287                         target->debug_reason = DBG_REASON_BREAKPOINT;
 288                         break;
 289                 case 5:
 290                         LOG_DEBUG("external breakpoint");
 291                         target->debug_reason = DBG_REASON_BREAKPOINT;
 292                         break;
 293                 case 6:
 294                         LOG_DEBUG("watchpoint from EICE unit 0");
 295                         target->debug_reason = DBG_REASON_WATCHPOINT;
 296                         break;
 297                 case 7:
 298                         LOG_DEBUG("watchpoint from EICE unit 1");
 299                         target->debug_reason = DBG_REASON_WATCHPOINT;
 300                         break;
 301                 case 8:
 302                         LOG_DEBUG("external watchpoint");
 303                         target->debug_reason = DBG_REASON_WATCHPOINT;
 304                         break;
 305                 case 9:
 306                         LOG_DEBUG("internal debug request");
 307                         target->debug_reason = DBG_REASON_DBGRQ;
 308                         break;
 309                 case 10:
 310                         LOG_DEBUG("external debug request");
 311                         target->debug_reason = DBG_REASON_DBGRQ;
 312                         break;
 313                 case 11:
 314                         LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
 315                         break;
 316                 case 12:
 317                         /* FIX!!!! here be dragons!!! We need to fail here so
 318                          * the target will interpreted as halted but we won't
 319                          * try to talk to it right now... a resume + halt seems
 320                          * to sync things up again. Please send an email to
 321                          * openocd development mailing list if you have hardware
 322                          * to donate to look into this problem....
 323                          */
 324                         LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
 325                         target->debug_reason = DBG_REASON_DBGRQ;
 326                         retval = ERROR_TARGET_FAILURE;
 327                         break;
 328                 default:
 329                         LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 330                         target->debug_reason = DBG_REASON_DBGRQ;
 331                         /* if we fail here, we won't talk to the target and it will
 332                          * be reported to be in the halted state */
 333                         retval = ERROR_TARGET_FAILURE;
 334                         break;
 335         }
 336
 337         return retval;
 338 }
 339
 340 u32 arm926ejs_get_ttb(target_t *target)
 341 {
 342         armv4_5_common_t *armv4_5 = target->arch_info;
 343         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 344         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 345         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 346         int retval;
 347         u32 ttb = 0x0;
 348
 349         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
 350                 return retval;
 351
 352         return ttb;
 353 }
 354
 355 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 356 {
 357         armv4_5_common_t *armv4_5 = target->arch_info;
 358         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 359         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 360         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 361         u32 cp15_control;
 362
 363         /* read cp15 control register */
 364         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 365         jtag_execute_queue();
 366
 367         if (mmu)
 368         {
 369                 /* invalidate TLB */
 370                 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
 371
 372                 cp15_control &= ~0x1U;
 373         }
 374
 375         if (d_u_cache)
 376         {
 377                 u32 debug_override;
 378                 /* read-modify-write CP15 debug override register
 379                  * to enable "test and clean all" */
 380                 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
 381                 debug_override |= 0x80000;
 382                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 383
 384                 /* clean and invalidate DCache */
 385                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 386
 387                 /* write CP15 debug override register
 388                  * to disable "test and clean all" */
 389                 debug_override &= ~0x80000;
 390                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 391
 392                 cp15_control &= ~0x4U;
 393         }
 394
 395         if (i_cache)
 396         {
 397                 /* invalidate ICache */
 398                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 399
 400                 cp15_control &= ~0x1000U;
 401         }
 402
 403         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 404 }
 405
 406 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 407 {
 408         armv4_5_common_t *armv4_5 = target->arch_info;
 409         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 410         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 411         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 412         u32 cp15_control;
 413
 414         /* read cp15 control register */
 415         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 416         jtag_execute_queue();
 417
 418         if (mmu)
 419                 cp15_control |= 0x1U;
 420
 421         if (d_u_cache)
 422                 cp15_control |= 0x4U;
 423
 424         if (i_cache)
 425                 cp15_control |= 0x1000U;
 426
 427         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 428 }
 429
 430 void arm926ejs_post_debug_entry(target_t *target)
 431 {
 432         armv4_5_common_t *armv4_5 = target->arch_info;
 433         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 434         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 435         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 436
 437         /* examine cp15 control reg */
 438         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
 439         jtag_execute_queue();
 440         LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
 441
 442         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 443         {
 444                 u32 cache_type_reg;
 445                 /* identify caches */
 446                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
 447                 jtag_execute_queue();
 448                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 449         }
 450
 451         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
 452         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 453         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 454
 455         /* save i/d fault status and address register */
 456         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
 457         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
 458         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
 459
 460         LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 461                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 462
 463         u32 cache_dbg_ctrl;
 464
 465         /* read-modify-write CP15 cache debug control register
 466          * to disable I/D-cache linefills and force WT */
 467         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 468         cache_dbg_ctrl |= 0x7;
 469         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 470 }
 471
 472 void arm926ejs_pre_restore_context(target_t *target)
 473 {
 474         armv4_5_common_t *armv4_5 = target->arch_info;
 475         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 476         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 477         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 478
 479         /* restore i/d fault status and address register */
 480         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
 481         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
 482         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
 483
 484         u32 cache_dbg_ctrl;
 485
 486         /* read-modify-write CP15 cache debug control register
 487          * to reenable I/D-cache linefills and disable WT */
 488         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 489         cache_dbg_ctrl &= ~0x7;
 490         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 491 }
 492
 493 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 494 {
 495         armv4_5_common_t *armv4_5 = target->arch_info;
 496         arm7_9_common_t *arm7_9;
 497         arm9tdmi_common_t *arm9tdmi;
 498         arm926ejs_common_t *arm926ejs;
 499
 500         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 501         {
 502                 return -1;
 503         }
 504
 505         arm7_9 = armv4_5->arch_info;
 506         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 507         {
 508                 return -1;
 509         }
 510
 511         arm9tdmi = arm7_9->arch_info;
 512         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 513         {
 514                 return -1;
 515         }
 516
 517         arm926ejs = arm9tdmi->arch_info;
 518         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 519         {
 520                 return -1;
 521         }
 522
 523         *armv4_5_p = armv4_5;
 524         *arm7_9_p = arm7_9;
 525         *arm9tdmi_p = arm9tdmi;
 526         *arm926ejs_p = arm926ejs;
 527
 528         return ERROR_OK;
 529 }
 530
 531 int arm926ejs_arch_state(struct target_s *target)
 532 {
 533         armv4_5_common_t *armv4_5 = target->arch_info;
 534         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 535         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 536         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 537
 538         char *state[] =
 539         {
 540                 "disabled", "enabled"
 541         };
 542
 543         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 544         {
 545                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 546                 exit(-1);
 547         }
 548
 549         LOG_USER(
 550                         "target halted in %s state due to %s, current mode: %s\n"
 551                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 552                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 553                          armv4_5_state_strings[armv4_5->core_state],
 554                          Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 555                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 556                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 557                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 558                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
 559                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 560                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 561
 562         return ERROR_OK;
 563 }
 564
 565 int arm926ejs_soft_reset_halt(struct target_s *target)
 566 {
 567         int retval = ERROR_OK;
 568         armv4_5_common_t *armv4_5 = target->arch_info;
 569         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 570         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 571         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 572         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 573
 574         if ((retval = target_halt(target)) != ERROR_OK)
 575         {
 576                 return retval;
 577         }
 578
 579         long long then=timeval_ms();
 580         int timeout;
 581         while (!(timeout=((timeval_ms()-then)>1000)))
 582         {
 583                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 584                 {
 585                         embeddedice_read_reg(dbg_stat);
 586                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 587                         {
 588                                 return retval;
 589                         }
 590                 }  else
 591                 {
 592                         break;
 593                 }
 594                 if (debug_level>=1)
 595                 {
 596                         /* do not eat all CPU, time out after 1 se*/
 597                         alive_sleep(100);
 598                 } else
 599                 {
 600                         keep_alive();
 601                 }
 602         }
 603         if (timeout)
 604         {
 605                 LOG_ERROR("Failed to halt CPU after 1 sec");
 606                 return ERROR_TARGET_TIMEOUT;
 607         }
 608
 609         target->state = TARGET_HALTED;
 610
 611         /* SVC, ARM state, IRQ and FIQ disabled */
 612         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 613         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 614         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 615
 616         /* start fetching from 0x0 */
 617         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 618         armv4_5->core_cache->reg_list[15].dirty = 1;
 619         armv4_5->core_cache->reg_list[15].valid = 1;
 620
 621         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 622         armv4_5->core_state = ARMV4_5_STATE_ARM;
 623
 624         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 625         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 626         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 627         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 628
 629         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 630 }
 631
 632 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 633 {
 634         int retval;
 635         armv4_5_common_t *armv4_5 = target->arch_info;
 636         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 637         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 638         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 639
 640         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 641                 return retval;
 642
 643         /* If ICache is enabled, we have to invalidate affected ICache lines
 644          * the DCache is forced to write-through, so we don't have to clean it here
 645          */
 646         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 647         {
 648                 if (count <= 1)
 649                 {
 650                         /* invalidate ICache single entry with MVA */
 651                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
 652                 }
 653                 else
 654                 {
 655                         /* invalidate ICache */
 656                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
 657                 }
 658         }
 659
 660         return retval;
 661 }
 662
 663 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 664 {
 665         arm9tdmi_init_target(cmd_ctx, target);
 666
 667         return ERROR_OK;
 668 }
 669
 670 int arm926ejs_quit(void)
 671 {
 672         return ERROR_OK;
 673 }
 674
 675 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 676 {
 677         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 678         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 679
 680         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 681          */
 682         arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 683
 684         arm9tdmi->arch_info = arm926ejs;
 685         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
 686
 687         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 688         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
 689
 690         arm926ejs->read_cp15 = arm926ejs_cp15_read;
 691         arm926ejs->write_cp15 = arm926ejs_cp15_write;
 692         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
 693         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
 694         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
 695         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
 696         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 697         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 698         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
 699         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 700
 701         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 702
 703         /* The ARM926EJ-S implements the ARMv5TE architecture which
 704          * has the BKPT instruction, so we don't have to use a watchpoint comparator
 705          */
 706         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
 707         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 708
 709         return ERROR_OK;
 710 }
 711
 712 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 713 {
 714         arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 715
 716         arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 717
 718         return ERROR_OK;
 719 }
 720
 721 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 722 {
 723         int retval;
 724         command_t *arm926ejs_cmd;
 725
 726
 727         retval = arm9tdmi_register_commands(cmd_ctx);
 728
 729         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
 730
 731         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 732
 733         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 734         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 735
 736         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 737         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 738         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 739
 740         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 741         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 742         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 743
 744         return retval;
 745 }
 746
 747 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 748 {
 749         int retval;
 750         target_t *target = get_current_target(cmd_ctx);
 751         armv4_5_common_t *armv4_5;
 752         arm7_9_common_t *arm7_9;
 753         arm9tdmi_common_t *arm9tdmi;
 754         arm926ejs_common_t *arm926ejs;
 755         int opcode_1;
 756         int opcode_2;
 757         int CRn;
 758         int CRm;
 759
 760         if ((argc < 4) || (argc > 5))
 761         {
 762                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 763                 return ERROR_OK;
 764         }
 765
 766         opcode_1 = strtoul(args[0], NULL, 0);
 767         opcode_2 = strtoul(args[1], NULL, 0);
 768         CRn = strtoul(args[2], NULL, 0);
 769         CRm = strtoul(args[3], NULL, 0);
 770
 771         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 772         {
 773                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 774                 return ERROR_OK;
 775         }
 776
 777         if (target->state != TARGET_HALTED)
 778         {
 779                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 780                 return ERROR_OK;
 781         }
 782
 783         if (argc == 4)
 784         {
 785                 u32 value;
 786                 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
 787                 {
 788                         command_print(cmd_ctx, "couldn't access register");
 789                         return ERROR_OK;
 790                 }
 791                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 792                 {
 793                         return retval;
 794                 }
 795
 796                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 797         }
 798         else
 799         {
 800                 u32 value = strtoul(args[4], NULL, 0);
 801                 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
 802                 {
 803                         command_print(cmd_ctx, "couldn't access register");
 804                         return ERROR_OK;
 805                 }
 806                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 807         }
 808
 809         return ERROR_OK;
 810 }
 811
 812 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 813 {
 814         target_t *target = get_current_target(cmd_ctx);
 815         armv4_5_common_t *armv4_5;
 816         arm7_9_common_t *arm7_9;
 817         arm9tdmi_common_t *arm9tdmi;
 818         arm926ejs_common_t *arm926ejs;
 819
 820         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 821         {
 822                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 823                 return ERROR_OK;
 824         }
 825
 826         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 827 }
 828
 829 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 830 {
 831         target_t *target = get_current_target(cmd_ctx);
 832         armv4_5_common_t *armv4_5;
 833         arm7_9_common_t *arm7_9;
 834         arm9tdmi_common_t *arm9tdmi;
 835         arm926ejs_common_t *arm926ejs;
 836         arm_jtag_t *jtag_info;
 837
 838         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 839         {
 840                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 841                 return ERROR_OK;
 842         }
 843
 844         jtag_info = &arm7_9->jtag_info;
 845
 846         if (target->state != TARGET_HALTED)
 847         {
 848                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 849                 return ERROR_OK;
 850         }
 851
 852         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 853 }
 854
 855 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 856 {
 857         target_t *target = get_current_target(cmd_ctx);
 858         armv4_5_common_t *armv4_5;
 859         arm7_9_common_t *arm7_9;
 860         arm9tdmi_common_t *arm9tdmi;
 861         arm926ejs_common_t *arm926ejs;
 862         arm_jtag_t *jtag_info;
 863
 864         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 865         {
 866                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 867                 return ERROR_OK;
 868         }
 869
 870         jtag_info = &arm7_9->jtag_info;
 871
 872         if (target->state != TARGET_HALTED)
 873         {
 874                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 875                 return ERROR_OK;
 876         }
 877
 878         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 879 }
 880
 881 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 882 {
 883         target_t *target = get_current_target(cmd_ctx);
 884         armv4_5_common_t *armv4_5;
 885         arm7_9_common_t *arm7_9;
 886         arm9tdmi_common_t *arm9tdmi;
 887         arm926ejs_common_t *arm926ejs;
 888         arm_jtag_t *jtag_info;
 889
 890         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 891         {
 892                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 893                 return ERROR_OK;
 894         }
 895
 896         jtag_info = &arm7_9->jtag_info;
 897
 898         if (target->state != TARGET_HALTED)
 899         {
 900                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 901                 return ERROR_OK;
 902         }
 903
 904         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 905 }
 906
 907 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 908 {
 909         int retval;
 910         int type;
 911         u32 cb;
 912         int domain;
 913         u32 ap;
 914
 915         armv4_5_common_t *armv4_5;
 916         arm7_9_common_t *arm7_9;
 917         arm9tdmi_common_t *arm9tdmi;
 918         arm926ejs_common_t *arm926ejs;
 919         retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
 920         if (retval != ERROR_OK)
 921         {
 922                 return retval;
 923         }
 924         u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
 925         if (type == -1)
 926         {
 927                 return ret;
 928         }
 929         *physical = ret;
 930         return ERROR_OK;
 931 }
 932
 933 static int arm926ejs_mmu(struct target_s *target, int *enabled)
 934 {
 935         armv4_5_common_t *armv4_5 = target->arch_info;
 936         arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
 937
 938         if (target->state != TARGET_HALTED)
 939         {
 940                 LOG_ERROR("Target not halted");
 941                 return ERROR_TARGET_INVALID;
 942         }
 943         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
 944         return ERROR_OK;
 945 }