1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
27 #include "time_support.h"
33 #define _DEBUG_INSTRUCTION_EXECUTION_
37 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 /* forward declarations */
48 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
49 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
50 int arm926ejs_quit(void);
51 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
53 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
54 static int arm926ejs_mmu(struct target_s *target, int *enabled);
56 target_type_t arm926ejs_target =
61 .arch_state = arm926ejs_arch_state,
63 .target_request_data = arm7_9_target_request_data,
66 .resume = arm7_9_resume,
69 .assert_reset = arm7_9_assert_reset,
70 .deassert_reset = arm7_9_deassert_reset,
71 .soft_reset_halt = arm926ejs_soft_reset_halt,
73 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
75 .read_memory = arm7_9_read_memory,
76 .write_memory = arm926ejs_write_memory,
77 .bulk_write_memory = arm7_9_bulk_write_memory,
78 .checksum_memory = arm7_9_checksum_memory,
79 .blank_check_memory = arm7_9_blank_check_memory,
81 .run_algorithm = armv4_5_run_algorithm,
83 .add_breakpoint = arm7_9_add_breakpoint,
84 .remove_breakpoint = arm7_9_remove_breakpoint,
85 .add_watchpoint = arm7_9_add_watchpoint,
86 .remove_watchpoint = arm7_9_remove_watchpoint,
88 .register_commands = arm926ejs_register_commands,
89 .target_create = arm926ejs_target_create,
90 .init_target = arm926ejs_init_target,
91 .examine = arm9tdmi_examine,
92 .quit = arm926ejs_quit,
93 .virt2phys = arm926ejs_virt2phys,
97 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
99 /* FIX!!!! this code should be reenabled. For now it does not check
103 /* The ARM926EJ-S' instruction register is 4 bits wide */
104 u8 t = *captured & 0xf;
105 u8 t2 = *field->in_check_value & 0xf;
110 else if ((t == 0x0f) || (t == 0x00))
112 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
115 return ERROR_JTAG_QUEUE_FAILED;;
119 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
121 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
123 int retval = ERROR_OK;
124 armv4_5_common_t *armv4_5 = target->arch_info;
125 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
126 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
127 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
128 scan_field_t fields[4];
133 buf_set_u32(address_buf, 0, 14, address);
135 jtag_add_end_state(TAP_IDLE);
136 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
140 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
142 fields[0].tap = jtag_info->tap;
143 fields[0].num_bits = 32;
144 fields[0].out_value = NULL;
146 fields[0].in_value = tmp;
149 fields[1].tap = jtag_info->tap;
150 fields[1].num_bits = 1;
151 fields[1].out_value = &access;
152 fields[1].in_value = &access;
155 fields[2].tap = jtag_info->tap;
156 fields[2].num_bits = 14;
157 fields[2].out_value = address_buf;
158 fields[2].in_value = NULL;
162 fields[3].tap = jtag_info->tap;
163 fields[3].num_bits = 1;
164 fields[3].out_value = &nr_w_buf;
165 fields[3].in_value = NULL;
168 jtag_add_dr_scan(4, fields, TAP_INVALID);
170 /*TODO: add timeout*/
173 /* rescan with NOP, to wait for the access to complete */
176 jtag_add_dr_scan_now(4, fields, TAP_INVALID);
178 *value=le_to_h_u32(tmp);
180 if((retval = jtag_execute_queue()) != ERROR_OK)
184 } while (buf_get_u32(&access, 0, 1) != 1);
186 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
187 LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
190 arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
195 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
197 int retval = ERROR_OK;
198 armv4_5_common_t *armv4_5 = target->arch_info;
199 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
200 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
201 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
202 scan_field_t fields[4];
208 buf_set_u32(address_buf, 0, 14, address);
209 buf_set_u32(value_buf, 0, 32, value);
211 jtag_add_end_state(TAP_IDLE);
212 if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
216 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
218 fields[0].tap = jtag_info->tap;
219 fields[0].num_bits = 32;
220 fields[0].out_value = value_buf;
222 fields[0].in_value = NULL;
228 fields[1].tap = jtag_info->tap;
229 fields[1].num_bits = 1;
230 fields[1].out_value = &access;
232 fields[1].in_value = &access;
238 fields[2].tap = jtag_info->tap;
239 fields[2].num_bits = 14;
240 fields[2].out_value = address_buf;
242 fields[2].in_value = NULL;
248 fields[3].tap = jtag_info->tap;
249 fields[3].num_bits = 1;
250 fields[3].out_value = &nr_w_buf;
252 fields[3].in_value = NULL;
258 jtag_add_dr_scan(4, fields, TAP_INVALID);
259 /*TODO: add timeout*/
262 /* rescan with NOP, to wait for the access to complete */
265 jtag_add_dr_scan(4, fields, TAP_INVALID);
266 if((retval = jtag_execute_queue()) != ERROR_OK)
270 } while (buf_get_u32(&access, 0, 1) != 1);
272 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
273 LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
276 arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
281 int arm926ejs_examine_debug_reason(target_t *target)
283 armv4_5_common_t *armv4_5 = target->arch_info;
284 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
285 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
289 embeddedice_read_reg(dbg_stat);
290 if ((retval = jtag_execute_queue()) != ERROR_OK)
293 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
295 switch (debug_reason)
298 LOG_DEBUG("breakpoint from EICE unit 0");
299 target->debug_reason = DBG_REASON_BREAKPOINT;
302 LOG_DEBUG("breakpoint from EICE unit 1");
303 target->debug_reason = DBG_REASON_BREAKPOINT;
306 LOG_DEBUG("soft breakpoint (BKPT instruction)");
307 target->debug_reason = DBG_REASON_BREAKPOINT;
310 LOG_DEBUG("vector catch breakpoint");
311 target->debug_reason = DBG_REASON_BREAKPOINT;
314 LOG_DEBUG("external breakpoint");
315 target->debug_reason = DBG_REASON_BREAKPOINT;
318 LOG_DEBUG("watchpoint from EICE unit 0");
319 target->debug_reason = DBG_REASON_WATCHPOINT;
322 LOG_DEBUG("watchpoint from EICE unit 1");
323 target->debug_reason = DBG_REASON_WATCHPOINT;
326 LOG_DEBUG("external watchpoint");
327 target->debug_reason = DBG_REASON_WATCHPOINT;
330 LOG_DEBUG("internal debug request");
331 target->debug_reason = DBG_REASON_DBGRQ;
334 LOG_DEBUG("external debug request");
335 target->debug_reason = DBG_REASON_DBGRQ;
338 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
341 /* FIX!!!! here be dragons!!! We need to fail here so
342 * the target will interpreted as halted but we won't
343 * try to talk to it right now... a resume + halt seems
344 * to sync things up again. Please send an email to
345 * openocd development mailing list if you have hardware
346 * to donate to look into this problem....
348 LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
349 target->debug_reason = DBG_REASON_DBGRQ;
350 retval = ERROR_TARGET_FAILURE;
353 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
354 target->debug_reason = DBG_REASON_DBGRQ;
355 /* if we fail here, we won't talk to the target and it will
356 * be reported to be in the halted state */
357 retval = ERROR_TARGET_FAILURE;
364 u32 arm926ejs_get_ttb(target_t *target)
366 armv4_5_common_t *armv4_5 = target->arch_info;
367 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
368 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
369 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
373 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
379 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
381 armv4_5_common_t *armv4_5 = target->arch_info;
382 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
383 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
384 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
387 /* read cp15 control register */
388 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
389 jtag_execute_queue();
394 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
396 cp15_control &= ~0x1U;
402 /* read-modify-write CP15 debug override register
403 * to enable "test and clean all" */
404 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
405 debug_override |= 0x80000;
406 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
408 /* clean and invalidate DCache */
409 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
411 /* write CP15 debug override register
412 * to disable "test and clean all" */
413 debug_override &= ~0x80000;
414 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
416 cp15_control &= ~0x4U;
421 /* invalidate ICache */
422 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
424 cp15_control &= ~0x1000U;
427 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
430 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
432 armv4_5_common_t *armv4_5 = target->arch_info;
433 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
434 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
435 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
438 /* read cp15 control register */
439 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
440 jtag_execute_queue();
443 cp15_control |= 0x1U;
446 cp15_control |= 0x4U;
449 cp15_control |= 0x1000U;
451 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
454 void arm926ejs_post_debug_entry(target_t *target)
456 armv4_5_common_t *armv4_5 = target->arch_info;
457 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
458 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
459 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
461 /* examine cp15 control reg */
462 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
463 jtag_execute_queue();
464 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
466 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
469 /* identify caches */
470 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
471 jtag_execute_queue();
472 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
475 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
476 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
477 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
479 /* save i/d fault status and address register */
480 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
481 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
482 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
484 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
485 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
489 /* read-modify-write CP15 cache debug control register
490 * to disable I/D-cache linefills and force WT */
491 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
492 cache_dbg_ctrl |= 0x7;
493 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
496 void arm926ejs_pre_restore_context(target_t *target)
498 armv4_5_common_t *armv4_5 = target->arch_info;
499 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
500 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
501 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
503 /* restore i/d fault status and address register */
504 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
505 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
506 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
510 /* read-modify-write CP15 cache debug control register
511 * to reenable I/D-cache linefills and disable WT */
512 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
513 cache_dbg_ctrl &= ~0x7;
514 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
517 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
519 armv4_5_common_t *armv4_5 = target->arch_info;
520 arm7_9_common_t *arm7_9;
521 arm9tdmi_common_t *arm9tdmi;
522 arm926ejs_common_t *arm926ejs;
524 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
529 arm7_9 = armv4_5->arch_info;
530 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
535 arm9tdmi = arm7_9->arch_info;
536 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
541 arm926ejs = arm9tdmi->arch_info;
542 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
547 *armv4_5_p = armv4_5;
549 *arm9tdmi_p = arm9tdmi;
550 *arm926ejs_p = arm926ejs;
555 int arm926ejs_arch_state(struct target_s *target)
557 armv4_5_common_t *armv4_5 = target->arch_info;
558 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
559 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
560 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
564 "disabled", "enabled"
567 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
569 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
574 "target halted in %s state due to %s, current mode: %s\n"
575 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
576 "MMU: %s, D-Cache: %s, I-Cache: %s",
577 armv4_5_state_strings[armv4_5->core_state],
578 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
579 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
580 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
581 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
582 state[arm926ejs->armv4_5_mmu.mmu_enabled],
583 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
584 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
589 int arm926ejs_soft_reset_halt(struct target_s *target)
591 int retval = ERROR_OK;
592 armv4_5_common_t *armv4_5 = target->arch_info;
593 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
594 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
595 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
596 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
598 if((retval = target_halt(target)) != ERROR_OK)
603 long long then=timeval_ms();
605 while (!(timeout=((timeval_ms()-then)>1000)))
607 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
609 embeddedice_read_reg(dbg_stat);
610 if((retval = jtag_execute_queue()) != ERROR_OK)
620 /* do not eat all CPU, time out after 1 se*/
629 LOG_ERROR("Failed to halt CPU after 1 sec");
630 return ERROR_TARGET_TIMEOUT;
633 target->state = TARGET_HALTED;
635 /* SVC, ARM state, IRQ and FIQ disabled */
636 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
637 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
638 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
640 /* start fetching from 0x0 */
641 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
642 armv4_5->core_cache->reg_list[15].dirty = 1;
643 armv4_5->core_cache->reg_list[15].valid = 1;
645 armv4_5->core_mode = ARMV4_5_MODE_SVC;
646 armv4_5->core_state = ARMV4_5_STATE_ARM;
648 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
649 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
650 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
651 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
653 return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
656 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
659 armv4_5_common_t *armv4_5 = target->arch_info;
660 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
661 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
662 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
664 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
667 /* If ICache is enabled, we have to invalidate affected ICache lines
668 * the DCache is forced to write-through, so we don't have to clean it here
670 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
674 /* invalidate ICache single entry with MVA */
675 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
679 /* invalidate ICache */
680 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
687 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
689 arm9tdmi_init_target(cmd_ctx, target);
694 int arm926ejs_quit(void)
699 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
701 arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
702 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
704 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
706 arm9tdmi_init_arch_info(target, arm9tdmi, tap);
708 arm9tdmi->arch_info = arm926ejs;
709 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
711 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
712 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
714 arm926ejs->read_cp15 = arm926ejs_cp15_read;
715 arm926ejs->write_cp15 = arm926ejs_cp15_write;
716 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
717 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
718 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
719 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
720 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
721 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
722 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
723 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
725 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
727 /* The ARM926EJ-S implements the ARMv5TE architecture which
728 * has the BKPT instruction, so we don't have to use a watchpoint comparator
730 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
731 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
736 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
738 arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
740 arm926ejs_init_arch_info(target, arm926ejs, target->tap);
745 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
748 command_t *arm926ejs_cmd;
751 retval = arm9tdmi_register_commands(cmd_ctx);
753 arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
755 register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
757 register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
758 register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
760 register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
761 register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
762 register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
764 register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
765 register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
766 register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
771 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
774 target_t *target = get_current_target(cmd_ctx);
775 armv4_5_common_t *armv4_5;
776 arm7_9_common_t *arm7_9;
777 arm9tdmi_common_t *arm9tdmi;
778 arm926ejs_common_t *arm926ejs;
784 if ((argc < 4) || (argc > 5))
786 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
790 opcode_1 = strtoul(args[0], NULL, 0);
791 opcode_2 = strtoul(args[1], NULL, 0);
792 CRn = strtoul(args[2], NULL, 0);
793 CRm = strtoul(args[3], NULL, 0);
795 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
797 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
801 if (target->state != TARGET_HALTED)
803 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
810 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
812 command_print(cmd_ctx, "couldn't access register");
815 if((retval = jtag_execute_queue()) != ERROR_OK)
820 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
824 u32 value = strtoul(args[4], NULL, 0);
825 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
827 command_print(cmd_ctx, "couldn't access register");
830 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
836 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
838 target_t *target = get_current_target(cmd_ctx);
839 armv4_5_common_t *armv4_5;
840 arm7_9_common_t *arm7_9;
841 arm9tdmi_common_t *arm9tdmi;
842 arm926ejs_common_t *arm926ejs;
844 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
846 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
850 return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
853 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
855 target_t *target = get_current_target(cmd_ctx);
856 armv4_5_common_t *armv4_5;
857 arm7_9_common_t *arm7_9;
858 arm9tdmi_common_t *arm9tdmi;
859 arm926ejs_common_t *arm926ejs;
860 arm_jtag_t *jtag_info;
862 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
864 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
868 jtag_info = &arm7_9->jtag_info;
870 if (target->state != TARGET_HALTED)
872 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
876 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
879 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
881 target_t *target = get_current_target(cmd_ctx);
882 armv4_5_common_t *armv4_5;
883 arm7_9_common_t *arm7_9;
884 arm9tdmi_common_t *arm9tdmi;
885 arm926ejs_common_t *arm926ejs;
886 arm_jtag_t *jtag_info;
888 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
890 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
894 jtag_info = &arm7_9->jtag_info;
896 if (target->state != TARGET_HALTED)
898 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
902 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
905 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
907 target_t *target = get_current_target(cmd_ctx);
908 armv4_5_common_t *armv4_5;
909 arm7_9_common_t *arm7_9;
910 arm9tdmi_common_t *arm9tdmi;
911 arm926ejs_common_t *arm926ejs;
912 arm_jtag_t *jtag_info;
914 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
916 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
920 jtag_info = &arm7_9->jtag_info;
922 if (target->state != TARGET_HALTED)
924 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
928 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
931 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
939 armv4_5_common_t *armv4_5;
940 arm7_9_common_t *arm7_9;
941 arm9tdmi_common_t *arm9tdmi;
942 arm926ejs_common_t *arm926ejs;
943 retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
944 if (retval != ERROR_OK)
948 u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
957 static int arm926ejs_mmu(struct target_s *target, int *enabled)
959 armv4_5_common_t *armv4_5 = target->arch_info;
960 arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
962 if (target->state != TARGET_HALTED)
964 LOG_ERROR("Target not halted");
965 return ERROR_TARGET_INVALID;
967 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;