1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 /* forward declarations */
49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 int arm926ejs_arch_state(struct target_s *target);
53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm926ejs_soft_reset_halt(struct target_s *target);
56 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
57 static int arm926ejs_mmu(struct target_s *target, int *enabled);
59 target_type_t arm926ejs_target =
64 .arch_state = arm926ejs_arch_state,
66 .target_request_data = arm7_9_target_request_data,
69 .resume = arm7_9_resume,
72 .assert_reset = arm7_9_assert_reset,
73 .deassert_reset = arm7_9_deassert_reset,
74 .soft_reset_halt = arm926ejs_soft_reset_halt,
76 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
78 .read_memory = arm7_9_read_memory,
79 .write_memory = arm926ejs_write_memory,
80 .bulk_write_memory = arm7_9_bulk_write_memory,
81 .checksum_memory = arm7_9_checksum_memory,
83 .run_algorithm = armv4_5_run_algorithm,
85 .add_breakpoint = arm7_9_add_breakpoint,
86 .remove_breakpoint = arm7_9_remove_breakpoint,
87 .add_watchpoint = arm7_9_add_watchpoint,
88 .remove_watchpoint = arm7_9_remove_watchpoint,
90 .register_commands = arm926ejs_register_commands,
91 .target_command = arm926ejs_target_command,
92 .init_target = arm926ejs_init_target,
93 .examine = arm9tdmi_examine,
94 .quit = arm926ejs_quit,
95 .virt2phys = arm926ejs_virt2phys,
100 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
102 /* The ARM926EJ-S' instruction register is 4 bits wide */
103 u8 t = *captured & 0xf;
104 u8 t2 = *field->in_check_value & 0xf;
109 else if ((t == 0x0f) || (t == 0x00))
111 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
114 return ERROR_JTAG_QUEUE_FAILED;;
117 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
119 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
121 armv4_5_common_t *armv4_5 = target->arch_info;
122 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
123 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
124 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
125 scan_field_t fields[4];
130 buf_set_u32(address_buf, 0, 14, address);
132 jtag_add_end_state(TAP_RTI);
133 arm_jtag_scann(jtag_info, 0xf);
134 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
136 fields[0].device = jtag_info->chain_pos;
137 fields[0].num_bits = 32;
138 fields[0].out_value = NULL;
139 fields[0].out_mask = NULL;
140 fields[0].in_value = NULL;
141 fields[0].in_check_value = NULL;
142 fields[0].in_check_mask = NULL;
143 fields[0].in_handler = NULL;
144 fields[0].in_handler_priv = NULL;
146 fields[1].device = jtag_info->chain_pos;
147 fields[1].num_bits = 1;
148 fields[1].out_value = &access;
149 fields[1].out_mask = NULL;
150 fields[1].in_value = &access;
151 fields[1].in_check_value = NULL;
152 fields[1].in_check_mask = NULL;
153 fields[1].in_handler = NULL;
154 fields[1].in_handler_priv = NULL;
156 fields[2].device = jtag_info->chain_pos;
157 fields[2].num_bits = 14;
158 fields[2].out_value = address_buf;
159 fields[2].out_mask = NULL;
160 fields[2].in_value = NULL;
161 fields[2].in_check_value = NULL;
162 fields[2].in_check_mask = NULL;
163 fields[2].in_handler = NULL;
164 fields[2].in_handler_priv = NULL;
166 fields[3].device = jtag_info->chain_pos;
167 fields[3].num_bits = 1;
168 fields[3].out_value = &nr_w_buf;
169 fields[3].out_mask = NULL;
170 fields[3].in_value = NULL;
171 fields[3].in_check_value = NULL;
172 fields[3].in_check_mask = NULL;
173 fields[3].in_handler = NULL;
174 fields[3].in_handler_priv = NULL;
176 jtag_add_dr_scan(4, fields, -1);
178 fields[0].in_handler_priv = value;
179 fields[0].in_handler = arm_jtag_buf_to_u32;
181 /*TODO: add timeout*/
184 /* rescan with NOP, to wait for the access to complete */
187 jtag_add_dr_scan(4, fields, -1);
188 jtag_execute_queue();
189 } while (buf_get_u32(&access, 0, 1) != 1);
191 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
192 LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
195 arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
200 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
202 armv4_5_common_t *armv4_5 = target->arch_info;
203 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
204 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
205 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
206 scan_field_t fields[4];
212 buf_set_u32(address_buf, 0, 14, address);
213 buf_set_u32(value_buf, 0, 32, value);
215 jtag_add_end_state(TAP_RTI);
216 arm_jtag_scann(jtag_info, 0xf);
217 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
219 fields[0].device = jtag_info->chain_pos;
220 fields[0].num_bits = 32;
221 fields[0].out_value = value_buf;
222 fields[0].out_mask = NULL;
223 fields[0].in_value = NULL;
224 fields[0].in_check_value = NULL;
225 fields[0].in_check_mask = NULL;
226 fields[0].in_handler = NULL;
227 fields[0].in_handler_priv = NULL;
229 fields[1].device = jtag_info->chain_pos;
230 fields[1].num_bits = 1;
231 fields[1].out_value = &access;
232 fields[1].out_mask = NULL;
233 fields[1].in_value = &access;
234 fields[1].in_check_value = NULL;
235 fields[1].in_check_mask = NULL;
236 fields[1].in_handler = NULL;
237 fields[1].in_handler_priv = NULL;
239 fields[2].device = jtag_info->chain_pos;
240 fields[2].num_bits = 14;
241 fields[2].out_value = address_buf;
242 fields[2].out_mask = NULL;
243 fields[2].in_value = NULL;
244 fields[2].in_check_value = NULL;
245 fields[2].in_check_mask = NULL;
246 fields[2].in_handler = NULL;
247 fields[2].in_handler_priv = NULL;
249 fields[3].device = jtag_info->chain_pos;
250 fields[3].num_bits = 1;
251 fields[3].out_value = &nr_w_buf;
252 fields[3].out_mask = NULL;
253 fields[3].in_value = NULL;
254 fields[3].in_check_value = NULL;
255 fields[3].in_check_mask = NULL;
256 fields[3].in_handler = NULL;
257 fields[3].in_handler_priv = NULL;
259 jtag_add_dr_scan(4, fields, -1);
260 /*TODO: add timeout*/
263 /* rescan with NOP, to wait for the access to complete */
266 jtag_add_dr_scan(4, fields, -1);
267 jtag_execute_queue();
268 } while (buf_get_u32(&access, 0, 1) != 1);
270 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
271 LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
274 arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
279 int arm926ejs_examine_debug_reason(target_t *target)
281 armv4_5_common_t *armv4_5 = target->arch_info;
282 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
283 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
287 embeddedice_read_reg(dbg_stat);
288 if ((retval = jtag_execute_queue()) != ERROR_OK)
291 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
293 switch (debug_reason)
296 LOG_DEBUG("breakpoint from EICE unit 0");
297 target->debug_reason = DBG_REASON_BREAKPOINT;
300 LOG_DEBUG("breakpoint from EICE unit 1");
301 target->debug_reason = DBG_REASON_BREAKPOINT;
304 LOG_DEBUG("soft breakpoint (BKPT instruction)");
305 target->debug_reason = DBG_REASON_BREAKPOINT;
308 LOG_DEBUG("vector catch breakpoint");
309 target->debug_reason = DBG_REASON_BREAKPOINT;
312 LOG_DEBUG("external breakpoint");
313 target->debug_reason = DBG_REASON_BREAKPOINT;
316 LOG_DEBUG("watchpoint from EICE unit 0");
317 target->debug_reason = DBG_REASON_WATCHPOINT;
320 LOG_DEBUG("watchpoint from EICE unit 1");
321 target->debug_reason = DBG_REASON_WATCHPOINT;
324 LOG_DEBUG("external watchpoint");
325 target->debug_reason = DBG_REASON_WATCHPOINT;
328 LOG_DEBUG("internal debug request");
329 target->debug_reason = DBG_REASON_DBGRQ;
332 LOG_DEBUG("external debug request");
333 target->debug_reason = DBG_REASON_DBGRQ;
336 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
339 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
340 target->debug_reason = DBG_REASON_DBGRQ;
341 retval = ERROR_TARGET_FAILURE;
348 u32 arm926ejs_get_ttb(target_t *target)
350 armv4_5_common_t *armv4_5 = target->arch_info;
351 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
352 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
353 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
357 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
363 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
365 armv4_5_common_t *armv4_5 = target->arch_info;
366 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
367 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
368 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
371 /* read cp15 control register */
372 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
373 jtag_execute_queue();
378 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
380 cp15_control &= ~0x1U;
386 /* read-modify-write CP15 debug override register
387 * to enable "test and clean all" */
388 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
389 debug_override |= 0x80000;
390 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
392 /* clean and invalidate DCache */
393 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
395 /* write CP15 debug override register
396 * to disable "test and clean all" */
397 debug_override &= ~0x80000;
398 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
400 cp15_control &= ~0x4U;
405 /* invalidate ICache */
406 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
408 cp15_control &= ~0x1000U;
411 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
414 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
416 armv4_5_common_t *armv4_5 = target->arch_info;
417 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
418 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
419 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
422 /* read cp15 control register */
423 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
424 jtag_execute_queue();
427 cp15_control |= 0x1U;
430 cp15_control |= 0x4U;
433 cp15_control |= 0x1000U;
435 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
438 void arm926ejs_post_debug_entry(target_t *target)
440 armv4_5_common_t *armv4_5 = target->arch_info;
441 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
442 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
443 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
445 /* examine cp15 control reg */
446 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
447 jtag_execute_queue();
448 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
450 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
453 /* identify caches */
454 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
455 jtag_execute_queue();
456 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
459 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
460 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
461 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
463 /* save i/d fault status and address register */
464 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
465 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
466 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
468 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
469 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
474 /* read-modify-write CP15 cache debug control register
475 * to disable I/D-cache linefills and force WT */
476 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
477 cache_dbg_ctrl |= 0x7;
478 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
481 void arm926ejs_pre_restore_context(target_t *target)
483 armv4_5_common_t *armv4_5 = target->arch_info;
484 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
485 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
486 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
488 /* restore i/d fault status and address register */
489 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
490 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
491 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
495 /* read-modify-write CP15 cache debug control register
496 * to reenable I/D-cache linefills and disable WT */
497 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
498 cache_dbg_ctrl &= ~0x7;
499 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
502 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
504 armv4_5_common_t *armv4_5 = target->arch_info;
505 arm7_9_common_t *arm7_9;
506 arm9tdmi_common_t *arm9tdmi;
507 arm926ejs_common_t *arm926ejs;
509 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
514 arm7_9 = armv4_5->arch_info;
515 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
520 arm9tdmi = arm7_9->arch_info;
521 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
526 arm926ejs = arm9tdmi->arch_info;
527 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
532 *armv4_5_p = armv4_5;
534 *arm9tdmi_p = arm9tdmi;
535 *arm926ejs_p = arm926ejs;
540 int arm926ejs_arch_state(struct target_s *target)
542 armv4_5_common_t *armv4_5 = target->arch_info;
543 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
544 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
545 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
549 "disabled", "enabled"
552 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
554 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
559 "target halted in %s state due to %s, current mode: %s\n"
560 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
561 "MMU: %s, D-Cache: %s, I-Cache: %s",
562 armv4_5_state_strings[armv4_5->core_state],
563 target_debug_reason_strings[target->debug_reason],
564 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
565 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
566 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
567 state[arm926ejs->armv4_5_mmu.mmu_enabled],
568 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
569 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
574 int arm926ejs_soft_reset_halt(struct target_s *target)
576 armv4_5_common_t *armv4_5 = target->arch_info;
577 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
578 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
579 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
580 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
587 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
589 embeddedice_read_reg(dbg_stat);
590 jtag_execute_queue();
595 /* do not eat all CPU, time out after 1 se*/
600 LOG_ERROR("Failed to halt CPU after 1 sec");
601 return ERROR_TARGET_TIMEOUT;
604 target->state = TARGET_HALTED;
606 /* SVC, ARM state, IRQ and FIQ disabled */
607 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
608 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
609 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
611 /* start fetching from 0x0 */
612 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
613 armv4_5->core_cache->reg_list[15].dirty = 1;
614 armv4_5->core_cache->reg_list[15].valid = 1;
616 armv4_5->core_mode = ARMV4_5_MODE_SVC;
617 armv4_5->core_state = ARMV4_5_STATE_ARM;
619 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
620 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
621 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
622 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
624 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
629 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
632 armv4_5_common_t *armv4_5 = target->arch_info;
633 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
634 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
635 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
637 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
640 /* If ICache is enabled, we have to invalidate affected ICache lines
641 * the DCache is forced to write-through, so we don't have to clean it here
643 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
647 /* invalidate ICache single entry with MVA */
648 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
652 /* invalidate ICache */
653 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
660 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
662 arm9tdmi_init_target(cmd_ctx, target);
674 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
676 arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
677 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
679 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
681 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
683 arm9tdmi->arch_info = arm926ejs;
684 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
686 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
687 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
689 arm926ejs->read_cp15 = arm926ejs_cp15_read;
690 arm926ejs->write_cp15 = arm926ejs_cp15_write;
691 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
692 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
693 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
694 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
695 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
696 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
697 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
698 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
700 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
702 /* The ARM926EJ-S implements the ARMv5TE architecture which
703 * has the BKPT instruction, so we don't have to use a watchpoint comparator
705 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
706 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
708 arm7_9->sw_bkpts_use_wp = 0;
709 arm7_9->sw_bkpts_enabled = 1;
714 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
717 char *variant = NULL;
718 arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
719 memset(arm926ejs, 0, sizeof(*arm926ejs));
723 LOG_ERROR("'target arm926ejs' requires at least one additional argument");
727 chain_pos = strtoul(args[3], NULL, 0);
732 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
734 arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
739 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
742 command_t *arm926ejs_cmd;
745 retval = arm9tdmi_register_commands(cmd_ctx);
747 arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
749 register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
751 register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
752 register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
754 register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
755 register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
756 register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
758 register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
759 register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
760 register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
765 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
768 target_t *target = get_current_target(cmd_ctx);
769 armv4_5_common_t *armv4_5;
770 arm7_9_common_t *arm7_9;
771 arm9tdmi_common_t *arm9tdmi;
772 arm926ejs_common_t *arm926ejs;
778 if ((argc < 4) || (argc > 5))
780 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
784 opcode_1 = strtoul(args[0], NULL, 0);
785 opcode_2 = strtoul(args[1], NULL, 0);
786 CRn = strtoul(args[2], NULL, 0);
787 CRm = strtoul(args[3], NULL, 0);
789 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
791 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
795 if (target->state != TARGET_HALTED)
797 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
804 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
806 command_print(cmd_ctx, "couldn't access register");
809 jtag_execute_queue();
811 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
815 u32 value = strtoul(args[4], NULL, 0);
816 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
818 command_print(cmd_ctx, "couldn't access register");
821 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
827 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
829 target_t *target = get_current_target(cmd_ctx);
830 armv4_5_common_t *armv4_5;
831 arm7_9_common_t *arm7_9;
832 arm9tdmi_common_t *arm9tdmi;
833 arm926ejs_common_t *arm926ejs;
835 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
837 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
841 return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
844 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
846 target_t *target = get_current_target(cmd_ctx);
847 armv4_5_common_t *armv4_5;
848 arm7_9_common_t *arm7_9;
849 arm9tdmi_common_t *arm9tdmi;
850 arm926ejs_common_t *arm926ejs;
851 arm_jtag_t *jtag_info;
853 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
855 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
859 jtag_info = &arm7_9->jtag_info;
861 if (target->state != TARGET_HALTED)
863 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
867 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
870 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
872 target_t *target = get_current_target(cmd_ctx);
873 armv4_5_common_t *armv4_5;
874 arm7_9_common_t *arm7_9;
875 arm9tdmi_common_t *arm9tdmi;
876 arm926ejs_common_t *arm926ejs;
877 arm_jtag_t *jtag_info;
879 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
881 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
885 jtag_info = &arm7_9->jtag_info;
887 if (target->state != TARGET_HALTED)
889 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
893 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
896 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
898 target_t *target = get_current_target(cmd_ctx);
899 armv4_5_common_t *armv4_5;
900 arm7_9_common_t *arm7_9;
901 arm9tdmi_common_t *arm9tdmi;
902 arm926ejs_common_t *arm926ejs;
903 arm_jtag_t *jtag_info;
905 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
907 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
911 jtag_info = &arm7_9->jtag_info;
913 if (target->state != TARGET_HALTED)
915 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
919 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
921 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
929 armv4_5_common_t *armv4_5;
930 arm7_9_common_t *arm7_9;
931 arm9tdmi_common_t *arm9tdmi;
932 arm926ejs_common_t *arm926ejs;
933 retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
934 if (retval != ERROR_OK)
938 u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
947 static int arm926ejs_mmu(struct target_s *target, int *enabled)
949 armv4_5_common_t *armv4_5 = target->arch_info;
950 arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
952 if (target->state != TARGET_HALTED)
954 LOG_ERROR("Target not halted");
955 return ERROR_TARGET_INVALID;
957 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;