1 /***************************************************************************
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2 * Copyright (C) 2007 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * This program is free software; you can redistribute it and/or modify *
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6 * it under the terms of the GNU General Public License as published by *
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7 * the Free Software Foundation; either version 2 of the License, or *
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8 * (at your option) any later version. *
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10 * This program is distributed in the hope that it will be useful, *
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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13 * GNU General Public License for more details. *
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15 * You should have received a copy of the GNU General Public License *
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16 * along with this program; if not, write to the *
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17 * Free Software Foundation, Inc., *
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18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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19 ***************************************************************************/
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20 #ifdef HAVE_CONFIG_H
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24 #include "arm926ejs.h"
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32 #define _DEBUG_INSTRUCTION_EXECUTION_
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36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
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38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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48 /* forward declarations */
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49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
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50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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51 int arm926ejs_quit();
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52 int arm926ejs_arch_state(struct target_s *target);
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53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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55 int arm926ejs_soft_reset_halt(struct target_s *target);
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56 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
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57 static int arm926ejs_mmu(struct target_s *target, int *enabled);
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59 target_type_t arm926ejs_target =
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61 .name = "arm926ejs",
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63 .poll = arm7_9_poll,
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64 .arch_state = arm926ejs_arch_state,
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66 .target_request_data = arm7_9_target_request_data,
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68 .halt = arm7_9_halt,
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69 .resume = arm7_9_resume,
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70 .step = arm7_9_step,
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72 .assert_reset = arm7_9_assert_reset,
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73 .deassert_reset = arm7_9_deassert_reset,
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74 .soft_reset_halt = arm926ejs_soft_reset_halt,
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75 .prepare_reset_halt = arm7_9_prepare_reset_halt,
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77 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
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79 .read_memory = arm7_9_read_memory,
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80 .write_memory = arm926ejs_write_memory,
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81 .bulk_write_memory = arm7_9_bulk_write_memory,
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82 .checksum_memory = arm7_9_checksum_memory,
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84 .run_algorithm = armv4_5_run_algorithm,
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86 .add_breakpoint = arm7_9_add_breakpoint,
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87 .remove_breakpoint = arm7_9_remove_breakpoint,
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88 .add_watchpoint = arm7_9_add_watchpoint,
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89 .remove_watchpoint = arm7_9_remove_watchpoint,
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91 .register_commands = arm926ejs_register_commands,
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92 .target_command = arm926ejs_target_command,
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93 .init_target = arm926ejs_init_target,
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94 .quit = arm926ejs_quit,
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95 .virt2phys = arm926ejs_virt2phys,
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96 .mmu = arm926ejs_mmu
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100 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
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102 /* The ARM926EJ-S' instruction register is 4 bits wide */
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103 u8 t = *captured & 0xf;
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104 u8 t2 = *field->in_check_value & 0xf;
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109 else if ((t == 0x0f) || (t == 0x00))
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111 DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
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114 return ERROR_JTAG_QUEUE_FAILED;;
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117 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
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119 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
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121 armv4_5_common_t *armv4_5 = target->arch_info;
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122 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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123 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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124 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
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125 scan_field_t fields[4];
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130 buf_set_u32(address_buf, 0, 14, address);
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132 jtag_add_end_state(TAP_RTI);
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133 arm_jtag_scann(jtag_info, 0xf);
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134 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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136 fields[0].device = jtag_info->chain_pos;
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137 fields[0].num_bits = 32;
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138 fields[0].out_value = NULL;
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139 fields[0].out_mask = NULL;
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140 fields[0].in_value = NULL;
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141 fields[0].in_check_value = NULL;
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142 fields[0].in_check_mask = NULL;
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143 fields[0].in_handler = NULL;
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144 fields[0].in_handler_priv = NULL;
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146 fields[1].device = jtag_info->chain_pos;
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147 fields[1].num_bits = 1;
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148 fields[1].out_value = &access;
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149 fields[1].out_mask = NULL;
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150 fields[1].in_value = &access;
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151 fields[1].in_check_value = NULL;
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152 fields[1].in_check_mask = NULL;
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153 fields[1].in_handler = NULL;
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154 fields[1].in_handler_priv = NULL;
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156 fields[2].device = jtag_info->chain_pos;
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157 fields[2].num_bits = 14;
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158 fields[2].out_value = address_buf;
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159 fields[2].out_mask = NULL;
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160 fields[2].in_value = NULL;
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161 fields[2].in_check_value = NULL;
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162 fields[2].in_check_mask = NULL;
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163 fields[2].in_handler = NULL;
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164 fields[2].in_handler_priv = NULL;
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166 fields[3].device = jtag_info->chain_pos;
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167 fields[3].num_bits = 1;
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168 fields[3].out_value = &nr_w_buf;
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169 fields[3].out_mask = NULL;
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170 fields[3].in_value = NULL;
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171 fields[3].in_check_value = NULL;
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172 fields[3].in_check_mask = NULL;
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173 fields[3].in_handler = NULL;
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174 fields[3].in_handler_priv = NULL;
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176 jtag_add_dr_scan(4, fields, -1);
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178 fields[0].in_handler_priv = value;
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179 fields[0].in_handler = arm_jtag_buf_to_u32;
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183 /* rescan with NOP, to wait for the access to complete */
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186 jtag_add_dr_scan(4, fields, -1);
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187 jtag_execute_queue();
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188 } while (buf_get_u32(&access, 0, 1) != 1);
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190 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
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191 DEBUG("addr: 0x%x value: %8.8x", address, *value);
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194 arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
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199 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
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201 armv4_5_common_t *armv4_5 = target->arch_info;
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202 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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203 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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204 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
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205 scan_field_t fields[4];
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211 buf_set_u32(address_buf, 0, 14, address);
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212 buf_set_u32(value_buf, 0, 32, value);
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214 jtag_add_end_state(TAP_RTI);
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215 arm_jtag_scann(jtag_info, 0xf);
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216 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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218 fields[0].device = jtag_info->chain_pos;
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219 fields[0].num_bits = 32;
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220 fields[0].out_value = value_buf;
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221 fields[0].out_mask = NULL;
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222 fields[0].in_value = NULL;
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223 fields[0].in_check_value = NULL;
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224 fields[0].in_check_mask = NULL;
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225 fields[0].in_handler = NULL;
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226 fields[0].in_handler_priv = NULL;
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228 fields[1].device = jtag_info->chain_pos;
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229 fields[1].num_bits = 1;
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230 fields[1].out_value = &access;
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231 fields[1].out_mask = NULL;
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232 fields[1].in_value = &access;
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233 fields[1].in_check_value = NULL;
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234 fields[1].in_check_mask = NULL;
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235 fields[1].in_handler = NULL;
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236 fields[1].in_handler_priv = NULL;
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238 fields[2].device = jtag_info->chain_pos;
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239 fields[2].num_bits = 14;
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240 fields[2].out_value = address_buf;
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241 fields[2].out_mask = NULL;
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242 fields[2].in_value = NULL;
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243 fields[2].in_check_value = NULL;
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244 fields[2].in_check_mask = NULL;
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245 fields[2].in_handler = NULL;
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246 fields[2].in_handler_priv = NULL;
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248 fields[3].device = jtag_info->chain_pos;
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249 fields[3].num_bits = 1;
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250 fields[3].out_value = &nr_w_buf;
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251 fields[3].out_mask = NULL;
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252 fields[3].in_value = NULL;
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253 fields[3].in_check_value = NULL;
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254 fields[3].in_check_mask = NULL;
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255 fields[3].in_handler = NULL;
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256 fields[3].in_handler_priv = NULL;
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258 jtag_add_dr_scan(4, fields, -1);
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262 /* rescan with NOP, to wait for the access to complete */
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265 jtag_add_dr_scan(4, fields, -1);
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266 jtag_execute_queue();
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267 } while (buf_get_u32(&access, 0, 1) != 1);
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269 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
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270 DEBUG("addr: 0x%x value: %8.8x", address, value);
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273 arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
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278 int arm926ejs_examine_debug_reason(target_t *target)
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280 armv4_5_common_t *armv4_5 = target->arch_info;
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281 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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282 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
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286 embeddedice_read_reg(dbg_stat);
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287 if ((retval = jtag_execute_queue()) != ERROR_OK)
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290 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
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292 switch (debug_reason)
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295 DEBUG("breakpoint from EICE unit 0");
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296 target->debug_reason = DBG_REASON_BREAKPOINT;
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299 DEBUG("breakpoint from EICE unit 1");
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300 target->debug_reason = DBG_REASON_BREAKPOINT;
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303 DEBUG("soft breakpoint (BKPT instruction)");
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304 target->debug_reason = DBG_REASON_BREAKPOINT;
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307 DEBUG("vector catch breakpoint");
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308 target->debug_reason = DBG_REASON_BREAKPOINT;
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311 DEBUG("external breakpoint");
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312 target->debug_reason = DBG_REASON_BREAKPOINT;
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315 DEBUG("watchpoint from EICE unit 0");
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316 target->debug_reason = DBG_REASON_WATCHPOINT;
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319 DEBUG("watchpoint from EICE unit 1");
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320 target->debug_reason = DBG_REASON_WATCHPOINT;
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323 DEBUG("external watchpoint");
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324 target->debug_reason = DBG_REASON_WATCHPOINT;
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327 DEBUG("internal debug request");
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328 target->debug_reason = DBG_REASON_DBGRQ;
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331 DEBUG("external debug request");
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332 target->debug_reason = DBG_REASON_DBGRQ;
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335 ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
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338 ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
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339 target->debug_reason = DBG_REASON_DBGRQ;
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345 u32 arm926ejs_get_ttb(target_t *target)
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347 armv4_5_common_t *armv4_5 = target->arch_info;
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348 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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349 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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350 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
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354 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
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360 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
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362 armv4_5_common_t *armv4_5 = target->arch_info;
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363 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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364 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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365 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
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368 /* read cp15 control register */
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369 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
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370 jtag_execute_queue();
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374 /* invalidate TLB */
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375 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
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377 cp15_control &= ~0x1U;
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382 u32 debug_override;
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383 /* read-modify-write CP15 debug override register
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384 * to enable "test and clean all" */
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385 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
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386 debug_override |= 0x80000;
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387 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
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389 /* clean and invalidate DCache */
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390 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
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392 /* write CP15 debug override register
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393 * to disable "test and clean all" */
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394 debug_override &= ~0x80000;
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395 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
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397 cp15_control &= ~0x4U;
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402 /* invalidate ICache */
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403 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
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405 cp15_control &= ~0x1000U;
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408 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
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411 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
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413 armv4_5_common_t *armv4_5 = target->arch_info;
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414 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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415 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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416 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
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419 /* read cp15 control register */
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420 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
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421 jtag_execute_queue();
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424 cp15_control |= 0x1U;
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427 cp15_control |= 0x4U;
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430 cp15_control |= 0x1000U;
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432 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
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435 void arm926ejs_post_debug_entry(target_t *target)
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437 armv4_5_common_t *armv4_5 = target->arch_info;
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438 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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439 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
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440 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
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442 /* examine cp15 control reg */
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443 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
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444 jtag_execute_queue();
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445 DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
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447 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
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449 u32 cache_type_reg;
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450 /* identify caches */
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451 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
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452 jtag_execute_queue();
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453 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
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456 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
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457 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
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458 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
\r
460 /* save i/d fault status and address register */
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461 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
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462 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
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463 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
\r
465 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
\r
466 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
\r
469 u32 cache_dbg_ctrl;
\r
471 /* read-modify-write CP15 cache debug control register
\r
472 * to disable I/D-cache linefills and force WT */
\r
473 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
\r
474 cache_dbg_ctrl |= 0x7;
\r
475 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
\r
478 void arm926ejs_pre_restore_context(target_t *target)
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480 armv4_5_common_t *armv4_5 = target->arch_info;
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481 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
482 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
\r
483 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
\r
485 /* restore i/d fault status and address register */
\r
486 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
\r
487 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
\r
488 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
\r
490 u32 cache_dbg_ctrl;
\r
492 /* read-modify-write CP15 cache debug control register
\r
493 * to reenable I/D-cache linefills and disable WT */
\r
494 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
\r
495 cache_dbg_ctrl &= ~0x7;
\r
496 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
\r
499 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
\r
501 armv4_5_common_t *armv4_5 = target->arch_info;
\r
502 arm7_9_common_t *arm7_9;
\r
503 arm9tdmi_common_t *arm9tdmi;
\r
504 arm926ejs_common_t *arm926ejs;
\r
506 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
\r
511 arm7_9 = armv4_5->arch_info;
\r
512 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
\r
517 arm9tdmi = arm7_9->arch_info;
\r
518 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
\r
523 arm926ejs = arm9tdmi->arch_info;
\r
524 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
\r
529 *armv4_5_p = armv4_5;
\r
530 *arm7_9_p = arm7_9;
\r
531 *arm9tdmi_p = arm9tdmi;
\r
532 *arm926ejs_p = arm926ejs;
\r
537 int arm926ejs_arch_state(struct target_s *target)
\r
539 armv4_5_common_t *armv4_5 = target->arch_info;
\r
540 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
541 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
\r
542 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
\r
546 "disabled", "enabled"
\r
549 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
\r
551 ERROR("BUG: called for a non-ARMv4/5 target");
\r
556 "target halted in %s state due to %s, current mode: %s\n"
\r
557 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
\r
558 "MMU: %s, D-Cache: %s, I-Cache: %s",
\r
559 armv4_5_state_strings[armv4_5->core_state],
\r
560 target_debug_reason_strings[target->debug_reason],
\r
561 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
\r
562 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
\r
563 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
\r
564 state[arm926ejs->armv4_5_mmu.mmu_enabled],
\r
565 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
\r
566 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
\r
571 int arm926ejs_soft_reset_halt(struct target_s *target)
\r
573 armv4_5_common_t *armv4_5 = target->arch_info;
\r
574 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
575 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
\r
576 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
\r
577 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
\r
579 if (target->state == TARGET_RUNNING)
\r
581 target->type->halt(target);
\r
584 while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
\r
586 embeddedice_read_reg(dbg_stat);
\r
587 jtag_execute_queue();
\r
590 target->state = TARGET_HALTED;
\r
592 /* SVC, ARM state, IRQ and FIQ disabled */
\r
593 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
\r
594 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
\r
595 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
\r
597 /* start fetching from 0x0 */
\r
598 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
\r
599 armv4_5->core_cache->reg_list[15].dirty = 1;
\r
600 armv4_5->core_cache->reg_list[15].valid = 1;
\r
602 armv4_5->core_mode = ARMV4_5_MODE_SVC;
\r
603 armv4_5->core_state = ARMV4_5_STATE_ARM;
\r
605 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
\r
606 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
\r
607 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
\r
608 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
\r
610 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
\r
615 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
\r
618 armv4_5_common_t *armv4_5 = target->arch_info;
\r
619 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
620 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
\r
621 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
\r
623 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
\r
626 /* If ICache is enabled, we have to invalidate affected ICache lines
\r
627 * the DCache is forced to write-through, so we don't have to clean it here
\r
629 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
\r
633 /* invalidate ICache single entry with MVA */
\r
634 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
\r
638 /* invalidate ICache */
\r
639 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
\r
646 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
\r
648 arm9tdmi_init_target(cmd_ctx, target);
\r
654 int arm926ejs_quit()
\r
660 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
\r
662 arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
\r
663 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
\r
665 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
\r
667 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
\r
669 arm9tdmi->arch_info = arm926ejs;
\r
670 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
\r
672 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
\r
673 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
\r
675 arm926ejs->read_cp15 = arm926ejs_cp15_read;
\r
676 arm926ejs->write_cp15 = arm926ejs_cp15_write;
\r
677 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
\r
678 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
\r
679 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
\r
680 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
\r
681 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
\r
682 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
\r
683 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
\r
684 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
\r
686 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
\r
688 /* The ARM926EJ-S implements the ARMv5TE architecture which
\r
689 * has the BKPT instruction, so we don't have to use a watchpoint comparator
\r
691 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
\r
692 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
\r
694 arm7_9->sw_bkpts_use_wp = 0;
\r
695 arm7_9->sw_bkpts_enabled = 1;
\r
700 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
\r
703 char *variant = NULL;
\r
704 arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
\r
708 ERROR("'target arm926ejs' requires at least one additional argument");
\r
712 chain_pos = strtoul(args[3], NULL, 0);
\r
717 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
\r
719 arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
\r
724 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
\r
727 command_t *arm926ejs_cmd;
\r
730 retval = arm9tdmi_register_commands(cmd_ctx);
\r
732 arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
\r
734 register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
\r
736 register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
\r
737 register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
\r
739 register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
\r
740 register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
\r
741 register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
\r
743 register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
\r
744 register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
\r
745 register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
\r
750 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
753 target_t *target = get_current_target(cmd_ctx);
\r
754 armv4_5_common_t *armv4_5;
\r
755 arm7_9_common_t *arm7_9;
\r
756 arm9tdmi_common_t *arm9tdmi;
\r
757 arm926ejs_common_t *arm926ejs;
\r
763 if ((argc < 4) || (argc > 5))
\r
765 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
\r
769 opcode_1 = strtoul(args[0], NULL, 0);
\r
770 opcode_2 = strtoul(args[1], NULL, 0);
\r
771 CRn = strtoul(args[2], NULL, 0);
\r
772 CRm = strtoul(args[3], NULL, 0);
\r
774 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
\r
776 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
\r
780 if (target->state != TARGET_HALTED)
\r
782 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
\r
789 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
\r
791 command_print(cmd_ctx, "couldn't access register");
\r
794 jtag_execute_queue();
\r
796 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
\r
800 u32 value = strtoul(args[4], NULL, 0);
\r
801 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
\r
803 command_print(cmd_ctx, "couldn't access register");
\r
806 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
\r
812 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
814 target_t *target = get_current_target(cmd_ctx);
\r
815 armv4_5_common_t *armv4_5;
\r
816 arm7_9_common_t *arm7_9;
\r
817 arm9tdmi_common_t *arm9tdmi;
\r
818 arm926ejs_common_t *arm926ejs;
\r
820 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
\r
822 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
\r
826 return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
\r
829 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
\r
831 target_t *target = get_current_target(cmd_ctx);
\r
832 armv4_5_common_t *armv4_5;
\r
833 arm7_9_common_t *arm7_9;
\r
834 arm9tdmi_common_t *arm9tdmi;
\r
835 arm926ejs_common_t *arm926ejs;
\r
836 arm_jtag_t *jtag_info;
\r
838 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
\r
840 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
\r
844 jtag_info = &arm7_9->jtag_info;
\r
846 if (target->state != TARGET_HALTED)
\r
848 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
\r
852 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
\r
855 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
\r
857 target_t *target = get_current_target(cmd_ctx);
\r
858 armv4_5_common_t *armv4_5;
\r
859 arm7_9_common_t *arm7_9;
\r
860 arm9tdmi_common_t *arm9tdmi;
\r
861 arm926ejs_common_t *arm926ejs;
\r
862 arm_jtag_t *jtag_info;
\r
864 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
\r
866 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
\r
870 jtag_info = &arm7_9->jtag_info;
\r
872 if (target->state != TARGET_HALTED)
\r
874 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
\r
878 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
\r
881 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
\r
883 target_t *target = get_current_target(cmd_ctx);
\r
884 armv4_5_common_t *armv4_5;
\r
885 arm7_9_common_t *arm7_9;
\r
886 arm9tdmi_common_t *arm9tdmi;
\r
887 arm926ejs_common_t *arm926ejs;
\r
888 arm_jtag_t *jtag_info;
\r
890 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
\r
892 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
\r
896 jtag_info = &arm7_9->jtag_info;
\r
898 if (target->state != TARGET_HALTED)
\r
900 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
\r
904 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
\r
906 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
\r
914 armv4_5_common_t *armv4_5;
\r
915 arm7_9_common_t *arm7_9;
\r
916 arm9tdmi_common_t *arm9tdmi;
\r
917 arm926ejs_common_t *arm926ejs;
\r
918 retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
\r
919 if (retval != ERROR_OK)
\r
923 u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
\r
932 static int arm926ejs_mmu(struct target_s *target, int *enabled)
\r
934 armv4_5_common_t *armv4_5 = target->arch_info;
\r
935 arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
\r
937 if (target->state != TARGET_HALTED)
\r
939 ERROR("Target not halted");
\r
940 return ERROR_TARGET_INVALID;
\r
942 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
\r