1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
39 #define _DEBUG_INSTRUCTION_EXECUTION_
43 int arm966e_register_commands(struct command_context_s *cmd_ctx);
45 /* forward declarations */
46 int arm966e_deassert_reset(target_t *target);
47 int arm966e_assert_reset(target_t *target);
48 int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
49 int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
50 int arm966e_quit(void);
52 target_type_t arm966e_target =
57 .arch_state = armv4_5_arch_state,
60 .resume = arm7_9_resume,
63 .assert_reset = arm966e_assert_reset,
64 .deassert_reset = arm966e_deassert_reset,
65 .soft_reset_halt = arm7_9_soft_reset_halt,
67 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
69 .read_memory = arm7_9_read_memory,
70 .write_memory = arm7_9_write_memory,
71 .bulk_write_memory = arm7_9_bulk_write_memory,
73 .run_algorithm = armv4_5_run_algorithm,
75 .add_breakpoint = arm7_9_add_breakpoint,
76 .remove_breakpoint = arm7_9_remove_breakpoint,
77 .add_watchpoint = arm7_9_add_watchpoint,
78 .remove_watchpoint = arm7_9_remove_watchpoint,
80 .register_commands = arm966e_register_commands,
81 .target_command = arm966e_target_command,
82 .init_target = arm966e_init_target,
86 int arm966e_assert_reset(target_t *target)
88 armv4_5_common_t *armv4_5 = target->arch_info;
89 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
90 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
91 arm966e_common_t *arm966e = arm9tdmi->arch_info;
92 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
95 DEBUG("target->state: %s", target_state_strings[target->state]);
97 if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
99 /* assert SRST and TRST */
100 /* system would get ouf sync if we didn't reset test-logic, too */
101 if ((retval = jtag_add_reset(1, 1)) != ERROR_OK)
103 if (retval == ERROR_JTAG_RESET_CANT_SRST)
105 WARNING("can't assert srst");
110 ERROR("unknown error");
114 jtag_add_sleep(5000);
115 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
117 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
119 WARNING("srst resets test logic, too");
120 retval = jtag_add_reset(1, 1);
126 if ((retval = jtag_add_reset(0, 1)) != ERROR_OK)
128 if (retval == ERROR_JTAG_RESET_WOULD_ASSERT_TRST)
130 WARNING("srst resets test logic, too");
131 retval = jtag_add_reset(1, 1);
134 if (retval == ERROR_JTAG_RESET_CANT_SRST)
136 WARNING("can't assert srst");
139 else if (retval != ERROR_OK)
141 ERROR("unknown error");
147 target->state = TARGET_RESET;
148 jtag_add_sleep(50000);
150 armv4_5_invalidate_core_regs(target);
155 int arm966e_deassert_reset(target_t *target)
157 armv4_5_common_t *armv4_5 = target->arch_info;
158 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
159 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
160 arm966e_common_t *arm966e = arm9tdmi->arch_info;
161 reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
163 arm7_9_deassert_reset( target );
168 int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
170 arm9tdmi_init_target(cmd_ctx, target);
175 int arm966e_quit(void)
181 int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chain_pos, char *variant)
183 arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
185 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
187 arm9tdmi->arch_info = arm966e;
188 arm966e->common_magic = ARM966E_COMMON_MAGIC;
193 int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
196 char *variant = NULL;
197 arm966e_common_t *arm966e = malloc(sizeof(arm966e_common_t));
201 ERROR("'target arm966e' requires at least one additional argument");
205 chain_pos = strtoul(args[3], NULL, 0);
210 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
212 arm966e_init_arch_info(target, arm966e, chain_pos, variant);
217 int arm966e_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm966e_common_t **arm966e_p)
219 armv4_5_common_t *armv4_5 = target->arch_info;
220 arm7_9_common_t *arm7_9;
221 arm9tdmi_common_t *arm9tdmi;
222 arm966e_common_t *arm966e;
224 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
229 arm7_9 = armv4_5->arch_info;
230 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
235 arm9tdmi = arm7_9->arch_info;
236 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
241 arm966e = arm9tdmi->arch_info;
242 if (arm966e->common_magic != ARM966E_COMMON_MAGIC)
247 *armv4_5_p = armv4_5;
249 *arm9tdmi_p = arm9tdmi;
250 *arm966e_p = arm966e;
255 int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
257 armv4_5_common_t *armv4_5 = target->arch_info;
258 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
259 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
260 scan_field_t fields[3];
261 u8 reg_addr_buf = reg_addr & 0x3f;
264 jtag_add_end_state(TAP_RTI);
265 arm_jtag_scann(jtag_info, 0xf);
266 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
268 fields[0].device = jtag_info->chain_pos;
269 fields[0].num_bits = 32;
270 fields[0].out_value = NULL;
271 fields[0].out_mask = NULL;
272 fields[0].in_value = NULL;
273 fields[0].in_check_value = NULL;
274 fields[0].in_check_mask = NULL;
275 fields[0].in_handler = NULL;
276 fields[0].in_handler_priv = NULL;
278 fields[1].device = jtag_info->chain_pos;
279 fields[1].num_bits = 6;
280 fields[1].out_value = ®_addr_buf;
281 fields[1].out_mask = NULL;
282 fields[1].in_value = NULL;
283 fields[1].in_check_value = NULL;
284 fields[1].in_check_mask = NULL;
285 fields[1].in_handler = NULL;
286 fields[1].in_handler_priv = NULL;
288 fields[2].device = jtag_info->chain_pos;
289 fields[2].num_bits = 1;
290 fields[2].out_value = &nr_w_buf;
291 fields[2].out_mask = NULL;
292 fields[2].in_value = NULL;
293 fields[2].in_check_value = NULL;
294 fields[2].in_check_mask = NULL;
295 fields[2].in_handler = NULL;
296 fields[2].in_handler_priv = NULL;
298 jtag_add_dr_scan(3, fields, -1);
300 fields[0].in_value = (u8*)value;
302 jtag_add_dr_scan(3, fields, -1);
307 int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
309 armv4_5_common_t *armv4_5 = target->arch_info;
310 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
311 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
312 scan_field_t fields[3];
313 u8 reg_addr_buf = reg_addr & 0x3f;
316 jtag_add_end_state(TAP_RTI);
317 arm_jtag_scann(jtag_info, 0xf);
318 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
320 fields[0].device = jtag_info->chain_pos;
321 fields[0].num_bits = 32;
322 fields[0].out_value = (u8*)&value;
323 fields[0].out_mask = NULL;
324 fields[0].in_value = NULL;
325 fields[0].in_check_value = NULL;
326 fields[0].in_check_mask = NULL;
327 fields[0].in_handler = NULL;
328 fields[0].in_handler_priv = NULL;
330 fields[1].device = jtag_info->chain_pos;
331 fields[1].num_bits = 6;
332 fields[1].out_value = ®_addr_buf;
333 fields[1].out_mask = NULL;
334 fields[1].in_value = NULL;
335 fields[1].in_check_value = NULL;
336 fields[1].in_check_mask = NULL;
337 fields[1].in_handler = NULL;
338 fields[1].in_handler_priv = NULL;
340 fields[2].device = jtag_info->chain_pos;
341 fields[2].num_bits = 1;
342 fields[2].out_value = &nr_w_buf;
343 fields[2].out_mask = NULL;
344 fields[2].in_value = NULL;
345 fields[2].in_check_value = NULL;
346 fields[2].in_check_mask = NULL;
347 fields[2].in_handler = NULL;
348 fields[2].in_handler_priv = NULL;
350 jtag_add_dr_scan(3, fields, -1);
355 int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
358 target_t *target = get_current_target(cmd_ctx);
359 armv4_5_common_t *armv4_5;
360 arm7_9_common_t *arm7_9;
361 arm9tdmi_common_t *arm9tdmi;
362 arm966e_common_t *arm966e;
363 arm_jtag_t *jtag_info;
365 if (arm966e_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm966e) != ERROR_OK)
367 command_print(cmd_ctx, "current target isn't an ARM966e target");
371 jtag_info = &arm7_9->jtag_info;
373 if (target->state != TARGET_HALTED)
375 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
379 /* one or more argument, access a single register (write if second argument is given */
382 int address = strtoul(args[0], NULL, 0);
387 if ((retval = arm966e_read_cp15(target, address, &value)) != ERROR_OK)
389 command_print(cmd_ctx, "couldn't access reg %i", address);
392 jtag_execute_queue();
394 command_print(cmd_ctx, "%i: %8.8x", address, value);
398 u32 value = strtoul(args[1], NULL, 0);
399 if ((retval = arm966e_write_cp15(target, address, value)) != ERROR_OK)
401 command_print(cmd_ctx, "couldn't access reg %i", address);
404 command_print(cmd_ctx, "%i: %8.8x", address, value);
411 int arm966e_register_commands(struct command_context_s *cmd_ctx)
414 command_t *arm966e_cmd;
416 retval = arm7_9_register_commands(cmd_ctx);
417 arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands");
418 register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");