1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2008 by Hongtao Zheng *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include "arm7_9_common.h"
36 #include "embeddedice.h"
47 #define _DEBUG_INSTRUCTION_EXECUTION_
51 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
53 /* forward declarations */
54 int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
56 int arm9tdmi_quit(void);
58 target_type_t arm9tdmi_target =
63 .arch_state = armv4_5_arch_state,
65 .target_request_data = arm7_9_target_request_data,
68 .resume = arm7_9_resume,
71 .assert_reset = arm7_9_assert_reset,
72 .deassert_reset = arm7_9_deassert_reset,
73 .soft_reset_halt = arm7_9_soft_reset_halt,
75 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
77 .read_memory = arm7_9_read_memory,
78 .write_memory = arm7_9_write_memory,
79 .bulk_write_memory = arm7_9_bulk_write_memory,
80 .checksum_memory = arm7_9_checksum_memory,
81 .blank_check_memory = arm7_9_blank_check_memory,
83 .run_algorithm = armv4_5_run_algorithm,
85 .add_breakpoint = arm7_9_add_breakpoint,
86 .remove_breakpoint = arm7_9_remove_breakpoint,
87 .add_watchpoint = arm7_9_add_watchpoint,
88 .remove_watchpoint = arm7_9_remove_watchpoint,
90 .register_commands = arm9tdmi_register_commands,
91 .target_create = arm9tdmi_target_create,
92 .init_target = arm9tdmi_init_target,
93 .examine = arm9tdmi_examine,
97 arm9tdmi_vector_t arm9tdmi_vectors[] =
99 {"reset", ARM9TDMI_RESET_VECTOR},
100 {"undef", ARM9TDMI_UNDEF_VECTOR},
101 {"swi", ARM9TDMI_SWI_VECTOR},
102 {"pabt", ARM9TDMI_PABT_VECTOR},
103 {"dabt", ARM9TDMI_DABT_VECTOR},
104 {"reserved", ARM9TDMI_RESERVED_VECTOR},
105 {"irq", ARM9TDMI_IRQ_VECTOR},
106 {"fiq", ARM9TDMI_FIQ_VECTOR},
110 int arm9tdmi_examine_debug_reason(target_t *target)
112 int retval = ERROR_OK;
113 /* get pointers to arch-specific information */
114 armv4_5_common_t *armv4_5 = target->arch_info;
115 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
117 /* only check the debug reason if we don't know it already */
118 if ((target->debug_reason != DBG_REASON_DBGRQ)
119 && (target->debug_reason != DBG_REASON_SINGLESTEP))
121 scan_field_t fields[3];
123 u8 instructionbus[4];
126 jtag_add_end_state(TAP_DRPAUSE);
128 fields[0].tap = arm7_9->jtag_info.tap;
129 fields[0].num_bits = 32;
130 fields[0].out_value = NULL;
131 fields[0].in_value = databus;
133 fields[1].tap = arm7_9->jtag_info.tap;
134 fields[1].num_bits = 3;
135 fields[1].out_value = NULL;
136 fields[1].in_value = &debug_reason;
138 fields[2].tap = arm7_9->jtag_info.tap;
139 fields[2].num_bits = 32;
140 fields[2].out_value = NULL;
141 fields[2].in_value = instructionbus;
143 if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
147 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
149 jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
150 if ((retval = jtag_execute_queue()) != ERROR_OK)
155 fields[0].in_value = NULL;
156 fields[0].out_value = databus;
157 fields[1].in_value = NULL;
158 fields[1].out_value = &debug_reason;
159 fields[2].in_value = NULL;
160 fields[2].out_value = instructionbus;
162 jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
164 if (debug_reason & 0x4)
165 if (debug_reason & 0x2)
166 target->debug_reason = DBG_REASON_WPTANDBKPT;
168 target->debug_reason = DBG_REASON_WATCHPOINT;
170 target->debug_reason = DBG_REASON_BREAKPOINT;
176 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
177 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
179 int retval = ERROR_OK;
180 scan_field_t fields[3];
183 u8 sysspeed_buf = 0x0;
186 buf_set_u32(out_buf, 0, 32, out);
188 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
191 buf_set_u32(&sysspeed_buf, 2, 1, 1);
193 jtag_add_end_state(TAP_DRPAUSE);
194 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
199 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
201 fields[0].tap = jtag_info->tap;
202 fields[0].num_bits = 32;
203 fields[0].out_value = out_buf;
204 fields[0].in_value = NULL;
206 fields[1].tap = jtag_info->tap;
207 fields[1].num_bits = 3;
208 fields[1].out_value = &sysspeed_buf;
209 fields[1].in_value = NULL;
211 fields[2].tap = jtag_info->tap;
212 fields[2].num_bits = 32;
213 fields[2].out_value = instr_buf;
214 fields[2].in_value = NULL;
219 fields[0].in_value=tmp;
220 jtag_add_dr_scan_now(3, fields, TAP_INVALID);
222 *in=le_to_h_u32(tmp);
226 jtag_add_dr_scan(3, fields, TAP_INVALID);
229 jtag_add_runtest(0, TAP_INVALID);
231 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
233 if ((retval = jtag_execute_queue()) != ERROR_OK)
240 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
243 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
250 /* just read data (instruction and data-out = don't care) */
251 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
253 int retval = ERROR_OK;;
254 scan_field_t fields[3];
256 jtag_add_end_state(TAP_DRPAUSE);
257 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
262 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
264 fields[0].tap = jtag_info->tap;
265 fields[0].num_bits = 32;
266 fields[0].out_value = NULL;
268 fields[0].in_value = tmp;
270 fields[1].tap = jtag_info->tap;
271 fields[1].num_bits = 3;
272 fields[1].out_value = NULL;
273 fields[1].in_value = NULL;
275 fields[2].tap = jtag_info->tap;
276 fields[2].num_bits = 32;
277 fields[2].out_value = NULL;
278 fields[2].in_value = NULL;
280 jtag_add_dr_scan_now(3, fields, TAP_INVALID);
282 *in=le_to_h_u32(tmp);
284 jtag_add_runtest(0, TAP_INVALID);
286 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
288 if ((retval = jtag_execute_queue()) != ERROR_OK)
295 LOG_DEBUG("in: 0x%8.8x", *in);
299 LOG_ERROR("BUG: called with in == NULL");
307 extern void arm_endianness(u8 *tmp, void *in, int size, int be, int flip);
309 /* clock the target, and read the databus
310 * the *in pointer points to a buffer where elements of 'size' bytes
311 * are stored in big (be==1) or little (be==0) endianness
313 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
315 int retval = ERROR_OK;
316 scan_field_t fields[3];
318 jtag_add_end_state(TAP_DRPAUSE);
319 if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
324 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
326 fields[0].tap = jtag_info->tap;
327 fields[0].num_bits = 32;
328 fields[0].out_value = NULL;
330 fields[0].in_value = tmp;
332 fields[1].tap = jtag_info->tap;
333 fields[1].num_bits = 3;
334 fields[1].out_value = NULL;
335 fields[1].in_value = NULL;
337 fields[2].tap = jtag_info->tap;
338 fields[2].num_bits = 32;
339 fields[2].out_value = NULL;
340 fields[2].in_value = NULL;
342 jtag_add_dr_scan_now(3, fields, TAP_INVALID);
344 arm_endianness(tmp, in, size, be, 0);
347 jtag_add_runtest(0, TAP_INVALID);
349 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
351 if ((retval = jtag_execute_queue()) != ERROR_OK)
358 LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
362 LOG_ERROR("BUG: called with in == NULL");
370 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
372 int retval = ERROR_OK;
373 /* get pointers to arch-specific information */
374 armv4_5_common_t *armv4_5 = target->arch_info;
375 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
376 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
378 /* save r0 before using it and put system in ARM state
379 * to allow common handling of ARM and THUMB debugging */
381 /* fetch STR r0, [r0] */
382 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
383 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
384 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
385 /* STR r0, [r0] in Memory */
386 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
388 /* MOV r0, r15 fetched, STR in Decode */
389 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
390 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
391 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
392 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
394 /* nothing fetched, STR r0, [r0] in Memory */
395 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
397 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
398 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
400 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
402 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
403 /* LDR in Memory (to account for interlock) */
404 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
407 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
408 /* NOP fetched, BX in Decode, MOV in Execute */
409 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
410 /* NOP fetched, BX in Execute (1) */
411 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
413 if ((retval = jtag_execute_queue()) != ERROR_OK)
418 /* fix program counter:
419 * MOV r0, r15 was the 5th instruction (+8)
420 * reading PC in Thumb state gives address of instruction + 4
425 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
428 /* get pointers to arch-specific information */
429 armv4_5_common_t *armv4_5 = target->arch_info;
430 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
431 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
433 /* STMIA r0-15, [r0] at debug speed
434 * register values will start to appear on 4th DCLK
436 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
438 /* fetch NOP, STM in DECODE stage */
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
440 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
441 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
443 for (i = 0; i <= 15; i++)
446 /* nothing fetched, STM in MEMORY (i'th cycle) */
447 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
451 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
454 /* get pointers to arch-specific information */
455 armv4_5_common_t *armv4_5 = target->arch_info;
456 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
457 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
458 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
459 u32 *buf_u32 = buffer;
460 u16 *buf_u16 = buffer;
463 /* STMIA r0-15, [r0] at debug speed
464 * register values will start to appear on 4th DCLK
466 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
468 /* fetch NOP, STM in DECODE stage */
469 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
470 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
471 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
473 for (i = 0; i <= 15; i++)
476 /* nothing fetched, STM in MEMORY (i'th cycle) */
480 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
483 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
486 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
492 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
494 /* get pointers to arch-specific information */
495 armv4_5_common_t *armv4_5 = target->arch_info;
496 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
497 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
500 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
501 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
503 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
504 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
507 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
508 /* fetch NOP, STR in DECODE stage */
509 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
510 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
511 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
512 /* nothing fetched, STR in MEMORY */
513 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
516 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
518 /* get pointers to arch-specific information */
519 armv4_5_common_t *armv4_5 = target->arch_info;
520 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
521 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
523 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
526 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
527 /* MSR2 fetched, MSR1 in DECODE */
528 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
529 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
530 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
531 /* nothing fetched, MSR1 in EXECUTE (2) */
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
533 /* nothing fetched, MSR1 in EXECUTE (3) */
534 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
535 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
537 /* nothing fetched, MSR2 in EXECUTE (2) */
538 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
539 /* nothing fetched, MSR2 in EXECUTE (3) */
540 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
541 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
542 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
543 /* nothing fetched, MSR3 in EXECUTE (2) */
544 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
545 /* nothing fetched, MSR3 in EXECUTE (3) */
546 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
547 /* NOP fetched, MSR4 in EXECUTE (1) */
548 /* last MSR writes flags, which takes only one cycle */
549 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
552 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
554 /* get pointers to arch-specific information */
555 armv4_5_common_t *armv4_5 = target->arch_info;
556 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
557 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
559 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
563 /* NOP fetched, MSR in DECODE */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
565 /* NOP fetched, MSR in EXECUTE (1) */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
568 /* rot == 4 writes flags, which takes only one cycle */
571 /* nothing fetched, MSR in EXECUTE (2) */
572 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
573 /* nothing fetched, MSR in EXECUTE (3) */
574 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
578 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
581 /* get pointers to arch-specific information */
582 armv4_5_common_t *armv4_5 = target->arch_info;
583 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
584 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
586 /* LDMIA r0-15, [r0] at debug speed
587 * register values will start to appear on 4th DCLK
589 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
591 /* fetch NOP, LDM in DECODE stage */
592 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
593 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
594 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
596 for (i = 0; i <= 15; i++)
599 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
600 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
602 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
605 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
607 /* get pointers to arch-specific information */
608 armv4_5_common_t *armv4_5 = target->arch_info;
609 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
610 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
612 /* put system-speed load-multiple into the pipeline */
613 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
614 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
617 void arm9tdmi_load_hword_reg(target_t *target, int num)
619 /* get pointers to arch-specific information */
620 armv4_5_common_t *armv4_5 = target->arch_info;
621 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
622 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
624 /* put system-speed load half-word into the pipeline */
625 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
626 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
629 void arm9tdmi_load_byte_reg(target_t *target, int num)
631 /* get pointers to arch-specific information */
632 armv4_5_common_t *armv4_5 = target->arch_info;
633 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
634 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
636 /* put system-speed load byte into the pipeline */
637 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
638 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
641 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
643 /* get pointers to arch-specific information */
644 armv4_5_common_t *armv4_5 = target->arch_info;
645 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
646 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
648 /* put system-speed store-multiple into the pipeline */
649 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
650 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
653 void arm9tdmi_store_hword_reg(target_t *target, int num)
655 /* get pointers to arch-specific information */
656 armv4_5_common_t *armv4_5 = target->arch_info;
657 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
658 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
660 /* put system-speed store half-word into the pipeline */
661 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
662 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
665 void arm9tdmi_store_byte_reg(target_t *target, int num)
667 /* get pointers to arch-specific information */
668 armv4_5_common_t *armv4_5 = target->arch_info;
669 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
670 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
672 /* put system-speed store byte into the pipeline */
673 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
674 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
677 void arm9tdmi_write_pc(target_t *target, u32 pc)
679 /* get pointers to arch-specific information */
680 armv4_5_common_t *armv4_5 = target->arch_info;
681 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
682 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
684 /* LDMIA r0-15, [r0] at debug speed
685 * register values will start to appear on 4th DCLK
687 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
689 /* fetch NOP, LDM in DECODE stage */
690 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
691 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
692 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
693 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
694 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
695 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
696 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
697 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
698 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
699 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
700 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
703 void arm9tdmi_branch_resume(target_t *target)
705 /* get pointers to arch-specific information */
706 armv4_5_common_t *armv4_5 = target->arch_info;
707 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
708 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
710 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
711 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
714 void arm9tdmi_branch_resume_thumb(target_t *target)
718 /* get pointers to arch-specific information */
719 armv4_5_common_t *armv4_5 = target->arch_info;
720 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
721 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
722 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
724 /* LDMIA r0-15, [r0] at debug speed
725 * register values will start to appear on 4th DCLK
727 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
729 /* fetch NOP, LDM in DECODE stage */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
731 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
732 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
733 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
734 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
735 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
736 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
738 /* Branch and eXchange */
739 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
741 embeddedice_read_reg(dbg_stat);
743 /* fetch NOP, BX in DECODE stage */
744 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
746 embeddedice_read_reg(dbg_stat);
748 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
749 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
751 /* target is now in Thumb state */
752 embeddedice_read_reg(dbg_stat);
754 /* load r0 value, MOV_IM in Decode*/
755 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
756 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
757 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
758 /* fetch NOP, LDR in Execute */
759 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
760 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
761 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
762 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
763 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
765 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
768 embeddedice_read_reg(dbg_stat);
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
771 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
774 void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
776 /* get pointers to arch-specific information */
777 armv4_5_common_t *armv4_5 = target->arch_info;
778 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
780 if (arm7_9->has_single_step)
782 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
783 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
787 arm7_9_enable_eice_step(target, next_pc);
791 void arm9tdmi_disable_single_step(target_t *target)
793 /* get pointers to arch-specific information */
794 armv4_5_common_t *armv4_5 = target->arch_info;
795 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
797 if (arm7_9->has_single_step)
799 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
800 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
804 arm7_9_disable_eice_step(target);
808 void arm9tdmi_build_reg_cache(target_t *target)
810 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
811 /* get pointers to arch-specific information */
812 armv4_5_common_t *armv4_5 = target->arch_info;
814 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
815 armv4_5->core_cache = (*cache_p);
818 int arm9tdmi_examine(struct target_s *target)
820 /* get pointers to arch-specific information */
822 armv4_5_common_t *armv4_5 = target->arch_info;
823 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
824 if (!target->type->examined)
826 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
828 /* one extra register (vector catch) */
829 t=embeddedice_build_reg_cache(target, arm7_9);
833 arm7_9->eice_cache = (*cache_p);
837 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
838 (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
839 arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
841 target->type->examined = 1;
843 if ((retval=embeddedice_setup(target))!=ERROR_OK)
845 if ((retval=arm7_9_setup(target))!=ERROR_OK)
849 if ((retval=etm_setup(target))!=ERROR_OK)
855 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
858 arm9tdmi_build_reg_cache(target);
863 int arm9tdmi_quit(void)
868 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
870 armv4_5_common_t *armv4_5;
871 arm7_9_common_t *arm7_9;
873 arm7_9 = &arm9tdmi->arm7_9_common;
874 armv4_5 = &arm7_9->armv4_5_common;
876 /* prepare JTAG information for the new target */
877 arm7_9->jtag_info.tap = tap;
878 arm7_9->jtag_info.scann_size = 5;
880 /* register arch-specific functions */
881 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
882 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
883 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
884 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
885 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
887 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
888 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
889 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
891 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
892 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
893 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
895 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
896 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
897 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
899 arm7_9->write_pc = arm9tdmi_write_pc;
900 arm7_9->branch_resume = arm9tdmi_branch_resume;
901 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
903 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
904 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
906 arm7_9->pre_debug_entry = NULL;
907 arm7_9->post_debug_entry = NULL;
909 arm7_9->pre_restore_context = NULL;
910 arm7_9->post_restore_context = NULL;
912 /* initialize arch-specific breakpoint handling */
913 arm7_9->arm_bkpt = 0xdeeedeee;
914 arm7_9->thumb_bkpt = 0xdeee;
916 arm7_9->dbgreq_adjust_pc = 3;
917 arm7_9->arch_info = arm9tdmi;
919 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
920 arm9tdmi->arch_info = NULL;
922 arm7_9_init_arch_info(target, arm7_9);
924 /* override use of DBGRQ, this is safe on ARM9TDMI */
925 arm7_9->use_dbgrq = 1;
927 /* all ARM9s have the vector catch register */
928 arm7_9->has_vector_catch = 1;
933 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
935 armv4_5_common_t *armv4_5 = target->arch_info;
936 arm7_9_common_t *arm7_9;
937 arm9tdmi_common_t *arm9tdmi;
939 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
944 arm7_9 = armv4_5->arch_info;
945 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
950 arm9tdmi = arm7_9->arch_info;
951 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
956 *armv4_5_p = armv4_5;
958 *arm9tdmi_p = arm9tdmi;
963 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
965 arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
967 arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
972 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
975 command_t *arm9tdmi_cmd;
977 retval = arm7_9_register_commands(cmd_ctx);
978 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
979 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
984 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
986 target_t *target = get_current_target(cmd_ctx);
987 armv4_5_common_t *armv4_5;
988 arm7_9_common_t *arm7_9;
989 arm9tdmi_common_t *arm9tdmi;
991 u32 vector_catch_value;
994 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
996 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1000 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1002 /* read the vector catch register if necessary */
1003 if (!vector_catch->valid)
1004 embeddedice_read_reg(vector_catch);
1006 /* get the current setting */
1007 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1011 vector_catch_value = 0x0;
1012 if (strcmp(args[0], "all") == 0)
1014 vector_catch_value = 0xdf;
1016 else if (strcmp(args[0], "none") == 0)
1022 for (i = 0; i < argc; i++)
1024 /* go through list of vectors */
1025 for (j = 0; arm9tdmi_vectors[j].name; j++)
1027 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1029 vector_catch_value |= arm9tdmi_vectors[j].value;
1034 /* complain if vector wasn't found */
1035 if (!arm9tdmi_vectors[j].name)
1037 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1039 /* reread current setting */
1040 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1047 /* store new settings */
1048 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1049 embeddedice_store_reg(vector_catch);
1052 /* output current settings (skip RESERVED vector) */
1053 for (i = 0; i < 8; i++)
1057 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1058 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");