1 /***************************************************************************
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2 * Copyright (C) 2005 by Dominic Rath *
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3 * Dominic.Rath@gmx.de *
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5 * This program is free software; you can redistribute it and/or modify *
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6 * it under the terms of the GNU General Public License as published by *
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7 * the Free Software Foundation; either version 2 of the License, or *
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8 * (at your option) any later version. *
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10 * This program is distributed in the hope that it will be useful, *
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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13 * GNU General Public License for more details. *
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15 * You should have received a copy of the GNU General Public License *
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16 * along with this program; if not, write to the *
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17 * Free Software Foundation, Inc., *
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18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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19 ***************************************************************************/
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20 #ifdef HAVE_CONFIG_H
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24 #include "arm9tdmi.h"
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26 #include "arm7_9_common.h"
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27 #include "register.h"
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29 #include "armv4_5.h"
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30 #include "embeddedice.h"
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35 #include "arm_jtag.h"
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41 #define _DEBUG_INSTRUCTION_EXECUTION_
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45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
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46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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48 /* forward declarations */
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49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
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50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
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51 int arm9tdmi_quit();
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53 target_type_t arm9tdmi_target =
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57 .poll = arm7_9_poll,
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58 .arch_state = armv4_5_arch_state,
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60 .target_request_data = arm7_9_target_request_data,
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62 .halt = arm7_9_halt,
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63 .resume = arm7_9_resume,
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64 .step = arm7_9_step,
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66 .assert_reset = arm7_9_assert_reset,
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67 .deassert_reset = arm7_9_deassert_reset,
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68 .soft_reset_halt = arm7_9_soft_reset_halt,
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69 .prepare_reset_halt = arm7_9_prepare_reset_halt,
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71 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
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73 .read_memory = arm7_9_read_memory,
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74 .write_memory = arm7_9_write_memory,
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75 .bulk_write_memory = arm7_9_bulk_write_memory,
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76 .checksum_memory = arm7_9_checksum_memory,
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78 .run_algorithm = armv4_5_run_algorithm,
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80 .add_breakpoint = arm7_9_add_breakpoint,
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81 .remove_breakpoint = arm7_9_remove_breakpoint,
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82 .add_watchpoint = arm7_9_add_watchpoint,
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83 .remove_watchpoint = arm7_9_remove_watchpoint,
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85 .register_commands = arm9tdmi_register_commands,
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86 .target_command = arm9tdmi_target_command,
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87 .init_target = arm9tdmi_init_target,
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88 .quit = arm9tdmi_quit
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91 arm9tdmi_vector_t arm9tdmi_vectors[] =
\r
93 {"reset", ARM9TDMI_RESET_VECTOR},
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94 {"undef", ARM9TDMI_UNDEF_VECTOR},
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95 {"swi", ARM9TDMI_SWI_VECTOR},
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96 {"pabt", ARM9TDMI_PABT_VECTOR},
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97 {"dabt", ARM9TDMI_DABT_VECTOR},
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98 {"reserved", ARM9TDMI_RESERVED_VECTOR},
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99 {"irq", ARM9TDMI_IRQ_VECTOR},
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100 {"fiq", ARM9TDMI_FIQ_VECTOR},
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104 int arm9tdmi_examine_debug_reason(target_t *target)
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106 /* get pointers to arch-specific information */
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107 armv4_5_common_t *armv4_5 = target->arch_info;
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108 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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110 /* only check the debug reason if we don't know it already */
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111 if ((target->debug_reason != DBG_REASON_DBGRQ)
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112 && (target->debug_reason != DBG_REASON_SINGLESTEP))
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114 scan_field_t fields[3];
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116 u8 instructionbus[4];
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119 jtag_add_end_state(TAP_PD);
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121 fields[0].device = arm7_9->jtag_info.chain_pos;
\r
122 fields[0].num_bits = 32;
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123 fields[0].out_value = NULL;
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124 fields[0].out_mask = NULL;
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125 fields[0].in_value = databus;
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126 fields[0].in_check_value = NULL;
\r
127 fields[0].in_check_mask = NULL;
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128 fields[0].in_handler = NULL;
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129 fields[0].in_handler_priv = NULL;
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131 fields[1].device = arm7_9->jtag_info.chain_pos;
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132 fields[1].num_bits = 3;
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133 fields[1].out_value = NULL;
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134 fields[1].out_mask = NULL;
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135 fields[1].in_value = &debug_reason;
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136 fields[1].in_check_value = NULL;
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137 fields[1].in_check_mask = NULL;
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138 fields[1].in_handler = NULL;
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139 fields[1].in_handler_priv = NULL;
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141 fields[2].device = arm7_9->jtag_info.chain_pos;
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142 fields[2].num_bits = 32;
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143 fields[2].out_value = NULL;
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144 fields[2].out_mask = NULL;
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145 fields[2].in_value = instructionbus;
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146 fields[2].in_check_value = NULL;
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147 fields[2].in_check_mask = NULL;
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148 fields[2].in_handler = NULL;
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149 fields[2].in_handler_priv = NULL;
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151 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
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152 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
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154 jtag_add_dr_scan(3, fields, TAP_PD);
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155 jtag_execute_queue();
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157 fields[0].in_value = NULL;
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158 fields[0].out_value = databus;
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159 fields[1].in_value = NULL;
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160 fields[1].out_value = &debug_reason;
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161 fields[2].in_value = NULL;
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162 fields[2].out_value = instructionbus;
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164 jtag_add_dr_scan(3, fields, TAP_PD);
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166 if (debug_reason & 0x4)
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167 if (debug_reason & 0x2)
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168 target->debug_reason = DBG_REASON_WPTANDBKPT;
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170 target->debug_reason = DBG_REASON_WATCHPOINT;
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172 target->debug_reason = DBG_REASON_BREAKPOINT;
\r
178 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
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179 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
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181 scan_field_t fields[3];
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184 u8 sysspeed_buf = 0x0;
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186 /* prepare buffer */
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187 buf_set_u32(out_buf, 0, 32, out);
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189 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
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192 buf_set_u32(&sysspeed_buf, 2, 1, 1);
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194 jtag_add_end_state(TAP_PD);
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195 arm_jtag_scann(jtag_info, 0x1);
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197 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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199 fields[0].device = jtag_info->chain_pos;
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200 fields[0].num_bits = 32;
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201 fields[0].out_value = out_buf;
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202 fields[0].out_mask = NULL;
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203 fields[0].in_value = NULL;
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206 fields[0].in_handler = arm_jtag_buf_to_u32;
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207 fields[0].in_handler_priv = in;
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211 fields[0].in_handler = NULL;
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212 fields[0].in_handler_priv = NULL;
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214 fields[0].in_check_value = NULL;
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215 fields[0].in_check_mask = NULL;
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217 fields[1].device = jtag_info->chain_pos;
\r
218 fields[1].num_bits = 3;
\r
219 fields[1].out_value = &sysspeed_buf;
\r
220 fields[1].out_mask = NULL;
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221 fields[1].in_value = NULL;
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222 fields[1].in_check_value = NULL;
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223 fields[1].in_check_mask = NULL;
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224 fields[1].in_handler = NULL;
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225 fields[1].in_handler_priv = NULL;
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227 fields[2].device = jtag_info->chain_pos;
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228 fields[2].num_bits = 32;
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229 fields[2].out_value = instr_buf;
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230 fields[2].out_mask = NULL;
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231 fields[2].in_value = NULL;
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232 fields[2].in_check_value = NULL;
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233 fields[2].in_check_mask = NULL;
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234 fields[2].in_handler = NULL;
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235 fields[2].in_handler_priv = NULL;
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237 jtag_add_dr_scan(3, fields, -1);
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239 jtag_add_runtest(0, -1);
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241 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
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243 jtag_execute_queue();
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247 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
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250 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
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257 /* just read data (instruction and data-out = don't care) */
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258 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
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260 scan_field_t fields[3];
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262 jtag_add_end_state(TAP_PD);
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263 arm_jtag_scann(jtag_info, 0x1);
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265 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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267 fields[0].device = jtag_info->chain_pos;
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268 fields[0].num_bits = 32;
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269 fields[0].out_value = NULL;
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270 fields[0].out_mask = NULL;
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271 fields[0].in_value = NULL;
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272 fields[0].in_handler = arm_jtag_buf_to_u32;
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273 fields[0].in_handler_priv = in;
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274 fields[0].in_check_value = NULL;
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275 fields[0].in_check_mask = NULL;
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277 fields[1].device = jtag_info->chain_pos;
\r
278 fields[1].num_bits = 3;
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279 fields[1].out_value = NULL;
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280 fields[1].out_mask = NULL;
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281 fields[1].in_value = NULL;
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282 fields[1].in_handler = NULL;
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283 fields[1].in_handler_priv = NULL;
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284 fields[1].in_check_value = NULL;
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285 fields[1].in_check_mask = NULL;
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287 fields[2].device = jtag_info->chain_pos;
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288 fields[2].num_bits = 32;
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289 fields[2].out_value = NULL;
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290 fields[2].out_mask = NULL;
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291 fields[2].in_value = NULL;
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292 fields[2].in_check_value = NULL;
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293 fields[2].in_check_mask = NULL;
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294 fields[2].in_handler = NULL;
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295 fields[2].in_handler_priv = NULL;
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297 jtag_add_dr_scan(3, fields, -1);
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299 jtag_add_runtest(0, -1);
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301 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
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303 jtag_execute_queue();
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307 DEBUG("in: 0x%8.8x", *in);
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311 ERROR("BUG: called with in == NULL");
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319 /* clock the target, and read the databus
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320 * the *in pointer points to a buffer where elements of 'size' bytes
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321 * are stored in big (be==1) or little (be==0) endianness
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323 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
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325 scan_field_t fields[3];
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327 jtag_add_end_state(TAP_PD);
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328 arm_jtag_scann(jtag_info, 0x1);
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330 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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332 fields[0].device = jtag_info->chain_pos;
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333 fields[0].num_bits = 32;
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334 fields[0].out_value = NULL;
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335 fields[0].out_mask = NULL;
\r
336 fields[0].in_value = NULL;
\r
340 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
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343 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
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346 fields[0].in_handler = arm_jtag_buf_to_8;
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349 fields[0].in_handler_priv = in;
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350 fields[0].in_check_value = NULL;
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351 fields[0].in_check_mask = NULL;
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353 fields[1].device = jtag_info->chain_pos;
\r
354 fields[1].num_bits = 3;
\r
355 fields[1].out_value = NULL;
\r
356 fields[1].out_mask = NULL;
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357 fields[1].in_value = NULL;
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358 fields[1].in_handler = NULL;
\r
359 fields[1].in_handler_priv = NULL;
\r
360 fields[1].in_check_value = NULL;
\r
361 fields[1].in_check_mask = NULL;
\r
363 fields[2].device = jtag_info->chain_pos;
\r
364 fields[2].num_bits = 32;
\r
365 fields[2].out_value = NULL;
\r
366 fields[2].out_mask = NULL;
\r
367 fields[2].in_value = NULL;
\r
368 fields[2].in_check_value = NULL;
\r
369 fields[2].in_check_mask = NULL;
\r
370 fields[2].in_handler = NULL;
\r
371 fields[2].in_handler_priv = NULL;
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373 jtag_add_dr_scan(3, fields, -1);
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375 jtag_add_runtest(0, -1);
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377 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
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379 jtag_execute_queue();
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383 DEBUG("in: 0x%8.8x", *in);
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387 ERROR("BUG: called with in == NULL");
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395 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
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397 /* get pointers to arch-specific information */
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398 armv4_5_common_t *armv4_5 = target->arch_info;
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399 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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400 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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402 /* save r0 before using it and put system in ARM state
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403 * to allow common handling of ARM and THUMB debugging */
\r
405 /* fetch STR r0, [r0] */
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406 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
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407 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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408 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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409 /* STR r0, [r0] in Memory */
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410 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
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412 /* MOV r0, r15 fetched, STR in Decode */
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413 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
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414 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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415 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
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416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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417 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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418 /* nothing fetched, STR r0, [r0] in Memory */
\r
419 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
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421 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
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422 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
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423 /* LDR in Decode */
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424 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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425 /* LDR in Execute */
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426 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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427 /* LDR in Memory (to account for interlock) */
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428 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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431 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
\r
432 /* NOP fetched, BX in Decode, MOV in Execute */
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433 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
\r
434 /* NOP fetched, BX in Execute (1) */
\r
435 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
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437 jtag_execute_queue();
\r
439 /* fix program counter:
\r
440 * MOV r0, r15 was the 5th instruction (+8)
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441 * reading PC in Thumb state gives address of instruction + 4
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446 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
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449 /* get pointers to arch-specific information */
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450 armv4_5_common_t *armv4_5 = target->arch_info;
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451 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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452 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
454 /* STMIA r0-15, [r0] at debug speed
\r
455 * register values will start to appear on 4th DCLK
\r
457 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
\r
459 /* fetch NOP, STM in DECODE stage */
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460 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
461 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
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462 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
464 for (i = 0; i <= 15; i++)
\r
466 if (mask & (1 << i))
\r
467 /* nothing fetched, STM in MEMORY (i'th cycle) */
\r
468 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
\r
473 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
\r
476 /* get pointers to arch-specific information */
\r
477 armv4_5_common_t *armv4_5 = target->arch_info;
\r
478 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
479 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
480 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
\r
481 u32 *buf_u32 = buffer;
\r
482 u16 *buf_u16 = buffer;
\r
483 u8 *buf_u8 = buffer;
\r
485 /* STMIA r0-15, [r0] at debug speed
\r
486 * register values will start to appear on 4th DCLK
\r
488 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
\r
490 /* fetch NOP, STM in DECODE stage */
\r
491 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
492 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
\r
493 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
495 for (i = 0; i <= 15; i++)
\r
497 if (mask & (1 << i))
\r
498 /* nothing fetched, STM in MEMORY (i'th cycle) */
\r
502 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
\r
505 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
\r
508 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
\r
515 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
\r
517 /* get pointers to arch-specific information */
\r
518 armv4_5_common_t *armv4_5 = target->arch_info;
\r
519 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
520 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
523 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
\r
524 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
525 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
526 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
527 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
529 /* STR r0, [r15] */
\r
530 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
\r
531 /* fetch NOP, STR in DECODE stage */
\r
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
533 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
\r
534 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
535 /* nothing fetched, STR in MEMORY */
\r
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
\r
540 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
\r
542 /* get pointers to arch-specific information */
\r
543 armv4_5_common_t *armv4_5 = target->arch_info;
\r
544 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
545 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
547 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
\r
550 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
\r
551 /* MSR2 fetched, MSR1 in DECODE */
\r
552 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
\r
553 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
\r
554 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
\r
555 /* nothing fetched, MSR1 in EXECUTE (2) */
\r
556 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
557 /* nothing fetched, MSR1 in EXECUTE (3) */
\r
558 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
559 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
\r
560 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
\r
561 /* nothing fetched, MSR2 in EXECUTE (2) */
\r
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
563 /* nothing fetched, MSR2 in EXECUTE (3) */
\r
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
565 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
\r
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
567 /* nothing fetched, MSR3 in EXECUTE (2) */
\r
568 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
569 /* nothing fetched, MSR3 in EXECUTE (3) */
\r
570 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
571 /* NOP fetched, MSR4 in EXECUTE (1) */
\r
572 /* last MSR writes flags, which takes only one cycle */
\r
573 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
576 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
\r
578 /* get pointers to arch-specific information */
\r
579 armv4_5_common_t *armv4_5 = target->arch_info;
\r
580 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
581 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
583 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
\r
586 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
\r
587 /* NOP fetched, MSR in DECODE */
\r
588 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
589 /* NOP fetched, MSR in EXECUTE (1) */
\r
590 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
592 /* rot == 4 writes flags, which takes only one cycle */
\r
595 /* nothing fetched, MSR in EXECUTE (2) */
\r
596 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
597 /* nothing fetched, MSR in EXECUTE (3) */
\r
598 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
602 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
\r
605 /* get pointers to arch-specific information */
\r
606 armv4_5_common_t *armv4_5 = target->arch_info;
\r
607 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
608 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
610 /* LDMIA r0-15, [r0] at debug speed
\r
611 * register values will start to appear on 4th DCLK
\r
613 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
\r
615 /* fetch NOP, LDM in DECODE stage */
\r
616 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
617 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
\r
618 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
620 for (i = 0; i <= 15; i++)
\r
622 if (mask & (1 << i))
\r
623 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
\r
624 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
\r
626 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
630 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
\r
632 /* get pointers to arch-specific information */
\r
633 armv4_5_common_t *armv4_5 = target->arch_info;
\r
634 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
635 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
637 /* put system-speed load-multiple into the pipeline */
\r
638 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
\r
639 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
\r
643 void arm9tdmi_load_hword_reg(target_t *target, int num)
\r
645 /* get pointers to arch-specific information */
\r
646 armv4_5_common_t *armv4_5 = target->arch_info;
\r
647 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
648 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
650 /* put system-speed load half-word into the pipeline */
\r
651 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
\r
652 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
\r
655 void arm9tdmi_load_byte_reg(target_t *target, int num)
\r
657 /* get pointers to arch-specific information */
\r
658 armv4_5_common_t *armv4_5 = target->arch_info;
\r
659 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
660 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
662 /* put system-speed load byte into the pipeline */
\r
663 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
\r
664 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
\r
668 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
\r
670 /* get pointers to arch-specific information */
\r
671 armv4_5_common_t *armv4_5 = target->arch_info;
\r
672 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
673 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
675 /* put system-speed store-multiple into the pipeline */
\r
676 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
\r
677 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
\r
681 void arm9tdmi_store_hword_reg(target_t *target, int num)
\r
683 /* get pointers to arch-specific information */
\r
684 armv4_5_common_t *armv4_5 = target->arch_info;
\r
685 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
686 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
688 /* put system-speed store half-word into the pipeline */
\r
689 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
\r
690 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
\r
694 void arm9tdmi_store_byte_reg(target_t *target, int num)
\r
696 /* get pointers to arch-specific information */
\r
697 armv4_5_common_t *armv4_5 = target->arch_info;
\r
698 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
699 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
701 /* put system-speed store byte into the pipeline */
\r
702 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
\r
703 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
\r
707 void arm9tdmi_write_pc(target_t *target, u32 pc)
\r
709 /* get pointers to arch-specific information */
\r
710 armv4_5_common_t *armv4_5 = target->arch_info;
\r
711 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
712 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
714 /* LDMIA r0-15, [r0] at debug speed
\r
715 * register values will start to appear on 4th DCLK
\r
717 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
\r
719 /* fetch NOP, LDM in DECODE stage */
\r
720 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
721 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
\r
722 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
723 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
\r
724 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
\r
725 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
\r
726 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
727 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
\r
728 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
729 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
\r
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
734 void arm9tdmi_branch_resume(target_t *target)
\r
736 /* get pointers to arch-specific information */
\r
737 armv4_5_common_t *armv4_5 = target->arch_info;
\r
738 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
739 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
741 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
\r
742 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
\r
746 void arm9tdmi_branch_resume_thumb(target_t *target)
\r
750 /* get pointers to arch-specific information */
\r
751 armv4_5_common_t *armv4_5 = target->arch_info;
\r
752 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
753 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
754 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
\r
756 /* LDMIA r0-15, [r0] at debug speed
\r
757 * register values will start to appear on 4th DCLK
\r
759 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
\r
761 /* fetch NOP, LDM in DECODE stage */
\r
762 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
763 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
\r
764 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
765 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
\r
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
\r
767 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
\r
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
770 /* Branch and eXchange */
\r
771 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
\r
773 embeddedice_read_reg(dbg_stat);
\r
775 /* fetch NOP, BX in DECODE stage */
\r
776 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
778 embeddedice_read_reg(dbg_stat);
\r
780 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
\r
781 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
\r
783 /* target is now in Thumb state */
\r
784 embeddedice_read_reg(dbg_stat);
\r
786 /* load r0 value, MOV_IM in Decode*/
\r
787 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
\r
788 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
\r
789 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
\r
790 /* fetch NOP, LDR in Execute */
\r
791 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
\r
792 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
\r
793 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
\r
794 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
\r
795 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
\r
797 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
\r
798 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
\r
800 embeddedice_read_reg(dbg_stat);
\r
802 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
\r
803 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
\r
807 void arm9tdmi_enable_single_step(target_t *target)
\r
809 /* get pointers to arch-specific information */
\r
810 armv4_5_common_t *armv4_5 = target->arch_info;
\r
811 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
813 if (arm7_9->has_single_step)
\r
815 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
\r
816 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
\r
820 arm7_9_enable_eice_step(target);
\r
824 void arm9tdmi_disable_single_step(target_t *target)
\r
826 /* get pointers to arch-specific information */
\r
827 armv4_5_common_t *armv4_5 = target->arch_info;
\r
828 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
830 if (arm7_9->has_single_step)
\r
832 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
\r
833 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
\r
837 arm7_9_disable_eice_step(target);
\r
841 void arm9tdmi_build_reg_cache(target_t *target)
\r
843 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
\r
844 /* get pointers to arch-specific information */
\r
845 armv4_5_common_t *armv4_5 = target->arch_info;
\r
846 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
\r
847 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
\r
849 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
\r
850 armv4_5->core_cache = (*cache_p);
\r
852 /* one extra register (vector catch) */
\r
853 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
\r
854 arm7_9->eice_cache = (*cache_p)->next;
\r
856 if (arm7_9->etm_ctx)
\r
858 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
\r
859 arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
\r
863 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
\r
866 arm9tdmi_build_reg_cache(target);
\r
872 int arm9tdmi_quit()
\r
878 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
\r
880 armv4_5_common_t *armv4_5;
\r
881 arm7_9_common_t *arm7_9;
\r
883 arm7_9 = &arm9tdmi->arm7_9_common;
\r
884 armv4_5 = &arm7_9->armv4_5_common;
\r
886 /* prepare JTAG information for the new target */
\r
887 arm7_9->jtag_info.chain_pos = chain_pos;
\r
888 arm7_9->jtag_info.scann_size = 5;
\r
890 /* register arch-specific functions */
\r
891 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
\r
892 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
\r
893 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
\r
894 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
\r
895 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
\r
897 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
\r
898 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
\r
899 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
\r
901 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
\r
902 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
\r
903 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
\r
905 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
\r
906 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
\r
907 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
\r
909 arm7_9->write_pc = arm9tdmi_write_pc;
\r
910 arm7_9->branch_resume = arm9tdmi_branch_resume;
\r
911 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
\r
913 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
\r
914 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
\r
916 arm7_9->pre_debug_entry = NULL;
\r
917 arm7_9->post_debug_entry = NULL;
\r
919 arm7_9->pre_restore_context = NULL;
\r
920 arm7_9->post_restore_context = NULL;
\r
922 /* initialize arch-specific breakpoint handling */
\r
923 arm7_9->arm_bkpt = 0xdeeedeee;
\r
924 arm7_9->thumb_bkpt = 0xdeee;
\r
926 arm7_9->sw_bkpts_use_wp = 1;
\r
927 arm7_9->sw_bkpts_enabled = 0;
\r
928 arm7_9->dbgreq_adjust_pc = 3;
\r
929 arm7_9->arch_info = arm9tdmi;
\r
931 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
\r
932 arm9tdmi->arch_info = NULL;
\r
936 arm9tdmi->variant = strdup(variant);
\r
940 arm9tdmi->variant = strdup("");
\r
943 arm7_9_init_arch_info(target, arm7_9);
\r
945 /* override use of DBGRQ, this is safe on ARM9TDMI */
\r
946 arm7_9->use_dbgrq = 1;
\r
948 /* all ARM9s have the vector catch register */
\r
949 arm7_9->has_vector_catch = 1;
\r
954 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
\r
956 armv4_5_common_t *armv4_5 = target->arch_info;
\r
957 arm7_9_common_t *arm7_9;
\r
958 arm9tdmi_common_t *arm9tdmi;
\r
960 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
\r
965 arm7_9 = armv4_5->arch_info;
\r
966 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
\r
971 arm9tdmi = arm7_9->arch_info;
\r
972 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
\r
977 *armv4_5_p = armv4_5;
\r
978 *arm7_9_p = arm7_9;
\r
979 *arm9tdmi_p = arm9tdmi;
\r
985 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
\r
986 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
\r
989 char *variant = NULL;
\r
990 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
\r
994 ERROR("'target arm9tdmi' requires at least one additional argument");
\r
998 chain_pos = strtoul(args[3], NULL, 0);
\r
1001 variant = args[4];
\r
1003 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
\r
1008 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
\r
1012 command_t *arm9tdmi_cmd;
\r
1015 retval = arm7_9_register_commands(cmd_ctx);
\r
1017 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
\r
1019 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
\r
1026 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
\r
1028 target_t *target = get_current_target(cmd_ctx);
\r
1029 armv4_5_common_t *armv4_5;
\r
1030 arm7_9_common_t *arm7_9;
\r
1031 arm9tdmi_common_t *arm9tdmi;
\r
1032 reg_t *vector_catch;
\r
1033 u32 vector_catch_value;
\r
1036 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
\r
1038 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
\r
1042 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
\r
1044 /* read the vector catch register if necessary */
\r
1045 if (!vector_catch->valid)
\r
1046 embeddedice_read_reg(vector_catch);
\r
1048 /* get the current setting */
\r
1049 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
\r
1053 vector_catch_value = 0x0;
\r
1054 if (strcmp(args[0], "all") == 0)
\r
1056 vector_catch_value = 0xdf;
\r
1058 else if (strcmp(args[0], "none") == 0)
\r
1064 for (i = 0; i < argc; i++)
\r
1066 /* go through list of vectors */
\r
1067 for(j = 0; arm9tdmi_vectors[j].name; j++)
\r
1069 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
\r
1071 vector_catch_value |= arm9tdmi_vectors[j].value;
\r
1076 /* complain if vector wasn't found */
\r
1077 if (!arm9tdmi_vectors[j].name)
\r
1079 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
\r
1081 /* reread current setting */
\r
1082 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
\r
1089 /* store new settings */
\r
1090 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
\r
1091 embeddedice_store_reg(vector_catch);
\r
1094 /* output current settings (skip RESERVED vector) */
\r
1095 for (i = 0; i < 8; i++)
\r
1099 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
\r
1100 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
\r