git.sur5r.net Git - openocd/blob - src/target/arm9tdmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm9tdmi.h"
  25
  26 #include "arm7_9_common.h"
  27 #include "register.h"
  28 #include "target.h"
  29 #include "armv4_5.h"
  30 #include "embeddedice.h"
  31 #include "etm.h"
  32 #include "etb.h"
  33 #include "log.h"
  34 #include "jtag.h"
  35 #include "arm_jtag.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39
  40 #if 0
  41 #define _DEBUG_INSTRUCTION_EXECUTION_
  42 #endif
  43
  44 /* cli handling */
  45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
  46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm9tdmi_quit();
  52
  53 target_type_t arm9tdmi_target =
  54 {
  55         .name = "arm9tdmi",
  56
  57         .poll = arm7_9_poll,
  58         .arch_state = armv4_5_arch_state,
  59
  60         .halt = arm7_9_halt,
  61         .resume = arm7_9_resume,
  62         .step = arm7_9_step,
  63
  64         .assert_reset = arm7_9_assert_reset,
  65         .deassert_reset = arm7_9_deassert_reset,
  66         .soft_reset_halt = arm7_9_soft_reset_halt,
  67
  68         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  69
  70         .read_memory = arm7_9_read_memory,
  71         .write_memory = arm7_9_write_memory,
  72         .bulk_write_memory = arm7_9_bulk_write_memory,
  73
  74         .run_algorithm = armv4_5_run_algorithm,
  75
  76         .add_breakpoint = arm7_9_add_breakpoint,
  77         .remove_breakpoint = arm7_9_remove_breakpoint,
  78         .add_watchpoint = arm7_9_add_watchpoint,
  79         .remove_watchpoint = arm7_9_remove_watchpoint,
  80
  81         .register_commands = arm9tdmi_register_commands,
  82         .target_command = arm9tdmi_target_command,
  83         .init_target = arm9tdmi_init_target,
  84         .quit = arm9tdmi_quit
  85 };
  86
  87 arm9tdmi_vector_t arm9tdmi_vectors[] =
  88 {
  89         {"reset", ARM9TDMI_RESET_VECTOR},
  90         {"undef", ARM9TDMI_UNDEF_VECTOR},
  91         {"swi", ARM9TDMI_SWI_VECTOR},
  92         {"pabt", ARM9TDMI_PABT_VECTOR},
  93         {"dabt", ARM9TDMI_DABT_VECTOR},
  94         {"reserved", ARM9TDMI_RESERVED_VECTOR},
  95         {"irq", ARM9TDMI_IRQ_VECTOR},
  96         {"fiq", ARM9TDMI_FIQ_VECTOR},
  97         {0, 0},
  98 };
  99
 100 int arm9tdmi_examine_debug_reason(target_t *target)
 101 {
 102         /* get pointers to arch-specific information */
 103         armv4_5_common_t *armv4_5 = target->arch_info;
 104         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 105
 106         /* only check the debug reason if we don't know it already */
 107         if ((target->debug_reason != DBG_REASON_DBGRQ)
 108                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 109         {
 110                 scan_field_t fields[3];
 111                 u8 databus[4];
 112                 u8 instructionbus[4];
 113                 u8 debug_reason;
 114
 115                 jtag_add_end_state(TAP_PD);
 116
 117                 fields[0].device = arm7_9->jtag_info.chain_pos;
 118                 fields[0].num_bits = 32;
 119                 fields[0].out_value = NULL;
 120                 fields[0].out_mask = NULL;
 121                 fields[0].in_value = databus;
 122                 fields[0].in_check_value = NULL;
 123                 fields[0].in_check_mask = NULL;
 124                 fields[0].in_handler = NULL;
 125                 fields[0].in_handler_priv = NULL;
 126
 127                 fields[1].device = arm7_9->jtag_info.chain_pos;
 128                 fields[1].num_bits = 3;
 129                 fields[1].out_value = NULL;
 130                 fields[1].out_mask = NULL;
 131                 fields[1].in_value = &debug_reason;
 132                 fields[1].in_check_value = NULL;
 133                 fields[1].in_check_mask = NULL;
 134                 fields[1].in_handler = NULL;
 135                 fields[1].in_handler_priv = NULL;
 136
 137                 fields[2].device = arm7_9->jtag_info.chain_pos;
 138                 fields[2].num_bits = 32;
 139                 fields[2].out_value = NULL;
 140                 fields[2].out_mask = NULL;
 141                 fields[2].in_value = instructionbus;
 142                 fields[2].in_check_value = NULL;
 143                 fields[2].in_check_mask = NULL;
 144                 fields[2].in_handler = NULL;
 145                 fields[2].in_handler_priv = NULL;
 146
 147                 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
 148                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
 149
 150                 jtag_add_dr_scan(3, fields, TAP_PD);
 151                 jtag_execute_queue();
 152
 153                 fields[0].in_value = NULL;
 154                 fields[0].out_value = databus;
 155                 fields[1].in_value = NULL;
 156                 fields[1].out_value = &debug_reason;
 157                 fields[2].in_value = NULL;
 158                 fields[2].out_value = instructionbus;
 159
 160                 jtag_add_dr_scan(3, fields, TAP_PD);
 161
 162                 if (debug_reason & 0x4)
 163                         if (debug_reason & 0x2)
 164                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 165                 else
 166                         target->debug_reason = DBG_REASON_WATCHPOINT;
 167                 else
 168                         target->debug_reason = DBG_REASON_BREAKPOINT;
 169         }
 170
 171         return ERROR_OK;
 172 }
 173
 174 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 175 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 176 {
 177         scan_field_t fields[3];
 178         u8 out_buf[4];
 179         u8 instr_buf[4];
 180         u8 sysspeed_buf = 0x0;
 181
 182         /* prepare buffer */
 183         buf_set_u32(out_buf, 0, 32, out);
 184
 185         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 186
 187         if (sysspeed)
 188                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 189
 190         jtag_add_end_state(TAP_PD);
 191         arm_jtag_scann(jtag_info, 0x1);
 192         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 193
 194         fields[0].device = jtag_info->chain_pos;
 195         fields[0].num_bits = 32;
 196         fields[0].out_value = out_buf;
 197         fields[0].out_mask = NULL;
 198         fields[0].in_value = NULL;
 199         if (in)
 200         {
 201                 fields[0].in_handler = arm_jtag_buf_to_u32;
 202                 fields[0].in_handler_priv = in;
 203         }
 204         else
 205         {
 206                 fields[0].in_handler = NULL;
 207                 fields[0].in_handler_priv = NULL;
 208         }
 209         fields[0].in_check_value = NULL;
 210         fields[0].in_check_mask = NULL;
 211
 212         fields[1].device = jtag_info->chain_pos;
 213         fields[1].num_bits = 3;
 214         fields[1].out_value = &sysspeed_buf;
 215         fields[1].out_mask = NULL;
 216         fields[1].in_value = NULL;
 217         fields[1].in_check_value = NULL;
 218         fields[1].in_check_mask = NULL;
 219         fields[1].in_handler = NULL;
 220         fields[1].in_handler_priv = NULL;
 221
 222         fields[2].device = jtag_info->chain_pos;
 223         fields[2].num_bits = 32;
 224         fields[2].out_value = instr_buf;
 225         fields[2].out_mask = NULL;
 226         fields[2].in_value = NULL;
 227         fields[2].in_check_value = NULL;
 228         fields[2].in_check_mask = NULL;
 229         fields[2].in_handler = NULL;
 230         fields[2].in_handler_priv = NULL;
 231
 232         jtag_add_dr_scan(3, fields, -1);
 233
 234         jtag_add_runtest(0, -1);
 235
 236 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 237         {
 238                 jtag_execute_queue();
 239
 240                 if (in)
 241                 {
 242                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 243                 }
 244                 else
 245                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 246         }
 247 #endif
 248
 249         return ERROR_OK;
 250 }
 251
 252 /* just read data (instruction and data-out = don't care) */
 253 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 254 {
 255         scan_field_t fields[3];
 256
 257         jtag_add_end_state(TAP_PD);
 258         arm_jtag_scann(jtag_info, 0x1);
 259         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 260
 261         fields[0].device = jtag_info->chain_pos;
 262         fields[0].num_bits = 32;
 263         fields[0].out_value = NULL;
 264         fields[0].out_mask = NULL;
 265         fields[0].in_value = NULL;
 266         fields[0].in_handler = arm_jtag_buf_to_u32;
 267         fields[0].in_handler_priv = in;
 268         fields[0].in_check_value = NULL;
 269         fields[0].in_check_mask = NULL;
 270
 271         fields[1].device = jtag_info->chain_pos;
 272         fields[1].num_bits = 3;
 273         fields[1].out_value = NULL;
 274         fields[1].out_mask = NULL;
 275         fields[1].in_value = NULL;
 276         fields[1].in_handler = NULL;
 277         fields[1].in_handler_priv = NULL;
 278         fields[1].in_check_value = NULL;
 279         fields[1].in_check_mask = NULL;
 280
 281         fields[2].device = jtag_info->chain_pos;
 282         fields[2].num_bits = 32;
 283         fields[2].out_value = NULL;
 284         fields[2].out_mask = NULL;
 285         fields[2].in_value = NULL;
 286         fields[2].in_check_value = NULL;
 287         fields[2].in_check_mask = NULL;
 288         fields[2].in_handler = NULL;
 289         fields[2].in_handler_priv = NULL;
 290
 291         jtag_add_dr_scan(3, fields, -1);
 292
 293         jtag_add_runtest(0, -1);
 294
 295 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 296         {
 297                 jtag_execute_queue();
 298
 299                 if (in)
 300                 {
 301                         DEBUG("in: 0x%8.8x", *in);
 302                 }
 303                 else
 304                 {
 305                         ERROR("BUG: called with in == NULL");
 306                 }
 307         }
 308 #endif
 309
 310         return ERROR_OK;
 311 }
 312
 313 /* clock the target, and read the databus
 314  * the *in pointer points to a buffer where elements of 'size' bytes
 315  * are stored in big (be==1) or little (be==0) endianness
 316  */
 317 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 318 {
 319         scan_field_t fields[3];
 320
 321         jtag_add_end_state(TAP_PD);
 322         arm_jtag_scann(jtag_info, 0x1);
 323         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 324
 325         fields[0].device = jtag_info->chain_pos;
 326         fields[0].num_bits = 32;
 327         fields[0].out_value = NULL;
 328         fields[0].out_mask = NULL;
 329         fields[0].in_value = NULL;
 330         switch (size)
 331         {
 332                 case 4:
 333                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
 334                         break;
 335                 case 2:
 336                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
 337                         break;
 338                 case 1:
 339                         fields[0].in_handler = arm_jtag_buf_to_8;
 340                         break;
 341         }
 342         fields[0].in_handler_priv = in;
 343         fields[0].in_check_value = NULL;
 344         fields[0].in_check_mask = NULL;
 345
 346         fields[1].device = jtag_info->chain_pos;
 347         fields[1].num_bits = 3;
 348         fields[1].out_value = NULL;
 349         fields[1].out_mask = NULL;
 350         fields[1].in_value = NULL;
 351         fields[1].in_handler = NULL;
 352         fields[1].in_handler_priv = NULL;
 353         fields[1].in_check_value = NULL;
 354         fields[1].in_check_mask = NULL;
 355
 356         fields[2].device = jtag_info->chain_pos;
 357         fields[2].num_bits = 32;
 358         fields[2].out_value = NULL;
 359         fields[2].out_mask = NULL;
 360         fields[2].in_value = NULL;
 361         fields[2].in_check_value = NULL;
 362         fields[2].in_check_mask = NULL;
 363         fields[2].in_handler = NULL;
 364         fields[2].in_handler_priv = NULL;
 365
 366         jtag_add_dr_scan(3, fields, -1);
 367
 368         jtag_add_runtest(0, -1);
 369
 370 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 371         {
 372                 jtag_execute_queue();
 373
 374                 if (in)
 375                 {
 376                         DEBUG("in: 0x%8.8x", *in);
 377                 }
 378                 else
 379                 {
 380                         ERROR("BUG: called with in == NULL");
 381                 }
 382         }
 383 #endif
 384
 385         return ERROR_OK;
 386 }
 387
 388 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 389 {
 390         /* get pointers to arch-specific information */
 391         armv4_5_common_t *armv4_5 = target->arch_info;
 392         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 393         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 394
 395         /* save r0 before using it and put system in ARM state
 396          * to allow common handling of ARM and THUMB debugging */
 397
 398         /* fetch STR r0, [r0] */
 399         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 400         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 401         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 402         /* STR r0, [r0] in Memory */
 403         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 404
 405         /* MOV r0, r15 fetched, STR in Decode */
 406         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 407         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 408         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 409         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 410         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 411         /* nothing fetched, STR r0, [r0] in Memory */
 412         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 413
 414         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 415         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 416         /* LDR in Decode */
 417         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 418         /* LDR in Execute */
 419         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 420         /* LDR in Memory (to account for interlock) */
 421         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 422
 423         /* fetch BX */
 424         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 425         /* NOP fetched, BX in Decode, MOV in Execute */
 426         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 427         /* NOP fetched, BX in Execute (1) */
 428         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 429
 430         jtag_execute_queue();
 431
 432         /* fix program counter:
 433          * MOV r0, r15 was the 5th instruction (+8)
 434          * reading PC in Thumb state gives address of instruction + 4
 435          */
 436         *pc -= 0xc;
 437 }
 438
 439 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 440 {
 441         int i;
 442         /* get pointers to arch-specific information */
 443         armv4_5_common_t *armv4_5 = target->arch_info;
 444         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 445         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 446
 447         /* STMIA r0-15, [r0] at debug speed
 448          * register values will start to appear on 4th DCLK
 449          */
 450         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 451
 452         /* fetch NOP, STM in DECODE stage */
 453         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 454         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 455         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 456
 457         for (i = 0; i <= 15; i++)
 458         {
 459                 if (mask & (1 << i))
 460                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 461                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 462         }
 463
 464 }
 465
 466 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 467 {
 468         int i;
 469         /* get pointers to arch-specific information */
 470         armv4_5_common_t *armv4_5 = target->arch_info;
 471         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 472         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 473         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 474         u32 *buf_u32 = buffer;
 475         u16 *buf_u16 = buffer;
 476         u8 *buf_u8 = buffer;
 477
 478         /* STMIA r0-15, [r0] at debug speed
 479          * register values will start to appear on 4th DCLK
 480          */
 481         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 482
 483         /* fetch NOP, STM in DECODE stage */
 484         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 485         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 486         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 487
 488         for (i = 0; i <= 15; i++)
 489         {
 490                 if (mask & (1 << i))
 491                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 492                         switch (size)
 493                         {
 494                                 case 4:
 495                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 496                                         break;
 497                                 case 2:
 498                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 499                                         break;
 500                                 case 1:
 501                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 502                                         break;
 503                         }
 504         }
 505
 506 }
 507
 508 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 509 {
 510         /* get pointers to arch-specific information */
 511         armv4_5_common_t *armv4_5 = target->arch_info;
 512         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 513         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 514
 515         /* MRS r0, cpsr */
 516         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 517         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 518         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 519         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 520         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 521
 522         /* STR r0, [r15] */
 523         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 524         /* fetch NOP, STR in DECODE stage */
 525         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 526         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 527         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 528         /* nothing fetched, STR in MEMORY */
 529         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 530
 531 }
 532
 533 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 534 {
 535         /* get pointers to arch-specific information */
 536         armv4_5_common_t *armv4_5 = target->arch_info;
 537         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 538         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 539
 540         DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 541
 542         /* MSR1 fetched */
 543         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 544         /* MSR2 fetched, MSR1 in DECODE */
 545         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 546         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 547         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 548         /* nothing fetched, MSR1 in EXECUTE (2) */
 549         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 550         /* nothing fetched, MSR1 in EXECUTE (3) */
 551         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 552         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 553         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 554         /* nothing fetched, MSR2 in EXECUTE (2) */
 555         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 556         /* nothing fetched, MSR2 in EXECUTE (3) */
 557         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 558         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 559         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 560         /* nothing fetched, MSR3 in EXECUTE (2) */
 561         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 562         /* nothing fetched, MSR3 in EXECUTE (3) */
 563         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 564         /* NOP fetched, MSR4 in EXECUTE (1) */
 565         /* last MSR writes flags, which takes only one cycle */
 566         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 567 }
 568
 569 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 570 {
 571         /* get pointers to arch-specific information */
 572         armv4_5_common_t *armv4_5 = target->arch_info;
 573         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 574         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 575
 576         DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 577
 578         /* MSR fetched */
 579         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 580         /* NOP fetched, MSR in DECODE */
 581         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 582         /* NOP fetched, MSR in EXECUTE (1) */
 583         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 584
 585         /* rot == 4 writes flags, which takes only one cycle */
 586         if (rot != 4)
 587         {
 588                 /* nothing fetched, MSR in EXECUTE (2) */
 589                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 590                 /* nothing fetched, MSR in EXECUTE (3) */
 591                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 592         }
 593 }
 594
 595 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 596 {
 597         int i;
 598         /* get pointers to arch-specific information */
 599         armv4_5_common_t *armv4_5 = target->arch_info;
 600         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 601         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 602
 603         /* LDMIA r0-15, [r0] at debug speed
 604         * register values will start to appear on 4th DCLK
 605         */
 606         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 607
 608         /* fetch NOP, LDM in DECODE stage */
 609         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 610         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 611         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 612
 613         for (i = 0; i <= 15; i++)
 614         {
 615                 if (mask & (1 << i))
 616                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 617                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 618         }
 619         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 620
 621 }
 622
 623 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 624 {
 625         /* get pointers to arch-specific information */
 626         armv4_5_common_t *armv4_5 = target->arch_info;
 627         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 628         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 629
 630         /* put system-speed load-multiple into the pipeline */
 631         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 632         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 633
 634 }
 635
 636 void arm9tdmi_load_hword_reg(target_t *target, int num)
 637 {
 638         /* get pointers to arch-specific information */
 639         armv4_5_common_t *armv4_5 = target->arch_info;
 640         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 641         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 642
 643         /* put system-speed load half-word into the pipeline */
 644         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 645         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 646 }
 647
 648 void arm9tdmi_load_byte_reg(target_t *target, int num)
 649 {
 650         /* get pointers to arch-specific information */
 651         armv4_5_common_t *armv4_5 = target->arch_info;
 652         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 653         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 654
 655         /* put system-speed load byte into the pipeline */
 656         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 657         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 658
 659 }
 660
 661 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 662 {
 663         /* get pointers to arch-specific information */
 664         armv4_5_common_t *armv4_5 = target->arch_info;
 665         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 666         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 667
 668         /* put system-speed store-multiple into the pipeline */
 669         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 670         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 671
 672 }
 673
 674 void arm9tdmi_store_hword_reg(target_t *target, int num)
 675 {
 676         /* get pointers to arch-specific information */
 677         armv4_5_common_t *armv4_5 = target->arch_info;
 678         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 679         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 680
 681         /* put system-speed store half-word into the pipeline */
 682         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 683         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 684
 685 }
 686
 687 void arm9tdmi_store_byte_reg(target_t *target, int num)
 688 {
 689         /* get pointers to arch-specific information */
 690         armv4_5_common_t *armv4_5 = target->arch_info;
 691         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 692         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 693
 694         /* put system-speed store byte into the pipeline */
 695         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 696         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 697
 698 }
 699
 700 void arm9tdmi_write_pc(target_t *target, u32 pc)
 701 {
 702         /* get pointers to arch-specific information */
 703         armv4_5_common_t *armv4_5 = target->arch_info;
 704         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 705         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 706
 707         /* LDMIA r0-15, [r0] at debug speed
 708          * register values will start to appear on 4th DCLK
 709          */
 710         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 711
 712         /* fetch NOP, LDM in DECODE stage */
 713         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 714         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 715         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 716         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 717         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 718         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 719         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 720         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 721         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 722         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 723         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 724
 725 }
 726
 727 void arm9tdmi_branch_resume(target_t *target)
 728 {
 729         /* get pointers to arch-specific information */
 730         armv4_5_common_t *armv4_5 = target->arch_info;
 731         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 732         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 733
 734         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 735         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 736
 737 }
 738
 739 void arm9tdmi_branch_resume_thumb(target_t *target)
 740 {
 741         DEBUG("-");
 742
 743         /* get pointers to arch-specific information */
 744         armv4_5_common_t *armv4_5 = target->arch_info;
 745         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 746         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 747         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 748
 749         /* LDMIA r0-15, [r0] at debug speed
 750         * register values will start to appear on 4th DCLK
 751         */
 752         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 753
 754         /* fetch NOP, LDM in DECODE stage */
 755         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 756         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 757         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 758         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 759         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 760         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 761         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 762
 763         /* Branch and eXchange */
 764         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 765
 766         embeddedice_read_reg(dbg_stat);
 767
 768         /* fetch NOP, BX in DECODE stage */
 769         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 770
 771         embeddedice_read_reg(dbg_stat);
 772
 773         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 774         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 775
 776         /* target is now in Thumb state */
 777         embeddedice_read_reg(dbg_stat);
 778
 779         /* load r0 value, MOV_IM in Decode*/
 780         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 781         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 782         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 783         /* fetch NOP, LDR in Execute */
 784         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 785         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 786         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 787         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 788         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 789
 790         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 791         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 792
 793         embeddedice_read_reg(dbg_stat);
 794
 795         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 796         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 797
 798 }
 799
 800 void arm9tdmi_enable_single_step(target_t *target)
 801 {
 802         /* get pointers to arch-specific information */
 803         armv4_5_common_t *armv4_5 = target->arch_info;
 804         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 805
 806         if (arm7_9->has_single_step)
 807         {
 808                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 809                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 810         }
 811         else
 812         {
 813                 arm7_9_enable_eice_step(target);
 814         }
 815 }
 816
 817 void arm9tdmi_disable_single_step(target_t *target)
 818 {
 819         /* get pointers to arch-specific information */
 820         armv4_5_common_t *armv4_5 = target->arch_info;
 821         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 822
 823         if (arm7_9->has_single_step)
 824         {
 825                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 826                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 827         }
 828         else
 829         {
 830                 arm7_9_disable_eice_step(target);
 831         }
 832 }
 833
 834 void arm9tdmi_build_reg_cache(target_t *target)
 835 {
 836         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 837         /* get pointers to arch-specific information */
 838         armv4_5_common_t *armv4_5 = target->arch_info;
 839         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 840         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 841
 842         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 843         armv4_5->core_cache = (*cache_p);
 844
 845         /* one extra register (vector catch) */
 846         (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
 847         arm7_9->eice_cache = (*cache_p)->next;
 848
 849         if (arm7_9->has_etm)
 850         {
 851                 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
 852                 arm7_9->etm_cache = (*cache_p)->next->next;
 853         }
 854
 855         if (arm7_9->etb)
 856         {
 857                 (*cache_p)->next->next->next = etb_build_reg_cache(arm7_9->etb);
 858                 arm7_9->etb->reg_cache = (*cache_p)->next->next->next;
 859         }
 860 }
 861
 862 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 863 {
 864
 865         arm9tdmi_build_reg_cache(target);
 866
 867         return ERROR_OK;
 868
 869 }
 870
 871 int arm9tdmi_quit()
 872 {
 873
 874         return ERROR_OK;
 875 }
 876
 877 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
 878 {
 879         armv4_5_common_t *armv4_5;
 880         arm7_9_common_t *arm7_9;
 881
 882         arm7_9 = &arm9tdmi->arm7_9_common;
 883         armv4_5 = &arm7_9->armv4_5_common;
 884
 885         /* prepare JTAG information for the new target */
 886         arm7_9->jtag_info.chain_pos = chain_pos;
 887         arm7_9->jtag_info.scann_size = 5;
 888
 889         /* register arch-specific functions */
 890         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 891         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 892         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 893         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 894         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 895
 896         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 897         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 898         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 899
 900         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 901         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 902         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 903
 904         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 905         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 906         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 907
 908         arm7_9->write_pc = arm9tdmi_write_pc;
 909         arm7_9->branch_resume = arm9tdmi_branch_resume;
 910         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 911
 912         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 913         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 914
 915         arm7_9->pre_debug_entry = NULL;
 916         arm7_9->post_debug_entry = NULL;
 917
 918         arm7_9->pre_restore_context = NULL;
 919         arm7_9->post_restore_context = NULL;
 920
 921         /* initialize arch-specific breakpoint handling */
 922         buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
 923         buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
 924
 925         arm7_9->sw_bkpts_use_wp = 1;
 926         arm7_9->sw_bkpts_enabled = 0;
 927         arm7_9->dbgreq_adjust_pc = 3;
 928         arm7_9->arch_info = arm9tdmi;
 929
 930         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 931         arm9tdmi->arch_info = NULL;
 932
 933         if (variant)
 934         {
 935                 arm9tdmi->variant = strdup(variant);
 936         }
 937         else
 938         {
 939                 arm9tdmi->variant = strdup("");
 940         }
 941
 942         arm7_9_init_arch_info(target, arm7_9);
 943
 944         /* override use of DBGRQ, this is safe on ARM9TDMI */
 945         arm7_9->use_dbgrq = 1;
 946
 947         /* all ARM9s have the vector catch register */
 948         arm7_9->has_vector_catch = 1;
 949
 950         return ERROR_OK;
 951 }
 952
 953 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
 954 {
 955         armv4_5_common_t *armv4_5 = target->arch_info;
 956         arm7_9_common_t *arm7_9;
 957         arm9tdmi_common_t *arm9tdmi;
 958
 959         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 960         {
 961                 return -1;
 962         }
 963
 964         arm7_9 = armv4_5->arch_info;
 965         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 966         {
 967                 return -1;
 968         }
 969
 970         arm9tdmi = arm7_9->arch_info;
 971         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 972         {
 973                 return -1;
 974         }
 975
 976         *armv4_5_p = armv4_5;
 977         *arm7_9_p = arm7_9;
 978         *arm9tdmi_p = arm9tdmi;
 979
 980         return ERROR_OK;
 981 }
 982
 983
 984 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
 985 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 986 {
 987         int chain_pos;
 988         char *variant = NULL;
 989         arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
 990
 991         if (argc < 4)
 992         {
 993                 ERROR("'target arm9tdmi' requires at least one additional argument");
 994                 exit(-1);
 995         }
 996
 997         chain_pos = strtoul(args[3], NULL, 0);
 998
 999         if (argc >= 5)
1000                 variant = args[4];
1001
1002         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1003
1004         return ERROR_OK;
1005 }
1006
1007 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1008 {
1009         int retval;
1010
1011         command_t *arm9tdmi_cmd;
1012
1013
1014         retval = arm7_9_register_commands(cmd_ctx);
1015
1016         arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1017
1018         register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1019
1020
1021         return ERROR_OK;
1022
1023 }
1024
1025 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1026 {
1027         target_t *target = get_current_target(cmd_ctx);
1028         armv4_5_common_t *armv4_5;
1029         arm7_9_common_t *arm7_9;
1030         arm9tdmi_common_t *arm9tdmi;
1031         reg_t *vector_catch;
1032         u32 vector_catch_value;
1033         int i, j;
1034
1035         if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1036         {
1037                 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1038                 return ERROR_OK;
1039         }
1040
1041         vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1042
1043         /* read the vector catch register if necessary */
1044         if (!vector_catch->valid)
1045                 embeddedice_read_reg(vector_catch);
1046
1047         /* get the current setting */
1048         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1049
1050         if (argc > 0)
1051         {
1052                 vector_catch_value = 0x0;
1053                 if (strcmp(args[0], "all") == 0)
1054                 {
1055                         vector_catch_value = 0xdf;
1056                 }
1057                 else if (strcmp(args[0], "none") == 0)
1058                 {
1059                         /* do nothing */
1060                 }
1061                 else
1062                 {
1063                         for (i = 0; i < argc; i++)
1064                         {
1065                                 /* go through list of vectors */
1066                                 for(j = 0; arm9tdmi_vectors[j].name; j++)
1067                                 {
1068                                         if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1069                                         {
1070                                                 vector_catch_value |= arm9tdmi_vectors[j].value;
1071                                                 break;
1072                                         }
1073                                 }
1074
1075                                 /* complain if vector wasn't found */
1076                                 if (!arm9tdmi_vectors[j].name)
1077                                 {
1078                                         command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1079
1080                                         /* reread current setting */
1081                                         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1082
1083                                         break;
1084                                 }
1085                         }
1086                 }
1087
1088                 /* store new settings */
1089                 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1090                 embeddedice_store_reg(vector_catch);
1091         }
1092
1093         /* output current settings (skip RESERVED vector) */
1094         for (i = 0; i < 8; i++)
1095         {
1096                 if (i != 5)
1097                 {
1098                         command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1099                                 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1100                 }
1101         }
1102
1103         return ERROR_OK;
1104 }