1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap->ap_bank_value = -1;
116 dap->ap_csw_value = -1;
117 dap->ap_tar_value = -1;
121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
123 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
124 dap->apcsw[dap->ap_current >> 24];
126 if (csw != dap->ap_csw_value) {
127 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
128 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
129 if (retval != ERROR_OK)
131 dap->ap_csw_value = csw;
136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
138 if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
139 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
140 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
141 if (retval != ERROR_OK)
143 dap->ap_tar_value = tar;
149 * Queue transactions setting up transfer parameters for the
150 * currently selected MEM-AP.
152 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
153 * initiate data reads or writes using memory or peripheral addresses.
154 * If the CSW is configured for it, the TAR may be automatically
155 * incremented after each transfer.
157 * @todo Rename to reflect it being specifically a MEM-AP function.
159 * @param dap The DAP connected to the MEM-AP.
160 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
161 * matches the cached value, the register is not changed.
162 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
163 * matches the cached address, the register is not changed.
165 * @return ERROR_OK if the transaction was properly queued, else a fault code.
167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
170 retval = dap_setup_accessport_csw(dap, csw);
171 if (retval != ERROR_OK)
173 retval = dap_setup_accessport_tar(dap, tar);
174 if (retval != ERROR_OK)
180 * Asynchronous (queued) read of a word from memory or a system register.
182 * @param dap The DAP connected to the MEM-AP performing the read.
183 * @param address Address of the 32-bit word to read; it must be
184 * readable by the currently selected MEM-AP.
185 * @param value points to where the word will be stored when the
186 * transaction queue is flushed (assuming no errors).
188 * @return ERROR_OK for success. Otherwise a fault code.
190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
195 /* Use banked addressing (REG_BDx) to avoid some link traffic
196 * (updating TAR) when reading several consecutive addresses.
198 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
199 address & 0xFFFFFFF0);
200 if (retval != ERROR_OK)
203 return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
207 * Synchronous read of a word from memory or a system register.
208 * As a side effect, this flushes any queued transactions.
210 * @param dap The DAP connected to the MEM-AP performing the read.
211 * @param address Address of the 32-bit word to read; it must be
212 * readable by the currently selected MEM-AP.
213 * @param value points to where the result will be stored.
215 * @return ERROR_OK for success; *value holds the result.
216 * Otherwise a fault code.
218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
223 retval = mem_ap_read_u32(dap, address, value);
224 if (retval != ERROR_OK)
231 * Asynchronous (queued) write of a word to memory or a system register.
233 * @param dap The DAP connected to the MEM-AP.
234 * @param address Address to be written; it must be writable by
235 * the currently selected MEM-AP.
236 * @param value Word that will be written to the address when transaction
237 * queue is flushed (assuming no errors).
239 * @return ERROR_OK for success. Otherwise a fault code.
241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
246 /* Use banked addressing (REG_BDx) to avoid some link traffic
247 * (updating TAR) when writing several consecutive addresses.
249 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
250 address & 0xFFFFFFF0);
251 if (retval != ERROR_OK)
254 return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
259 * Synchronous write of a word to memory or a system register.
260 * As a side effect, this flushes any queued transactions.
262 * @param dap The DAP connected to the MEM-AP.
263 * @param address Address to be written; it must be writable by
264 * the currently selected MEM-AP.
265 * @param value Word that will be written.
267 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
272 int retval = mem_ap_write_u32(dap, address, value);
274 if (retval != ERROR_OK)
281 * Synchronous write of a block of memory, using a specific access size.
283 * @param dap The DAP connected to the MEM-AP.
284 * @param buffer The data buffer to write. No particular alignment is assumed.
285 * @param size Which access size to use, in bytes. 1, 2 or 4.
286 * @param count The number of writes to do (in size units, not bytes).
287 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
288 * @param addrinc Whether the target address should be increased for each write or not. This
289 * should normally be true, except when writing to e.g. a FIFO.
290 * @return ERROR_OK on success, otherwise an error code.
292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
293 uint32_t address, bool addrinc)
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
301 csw_size = CSW_32BIT;
303 csw_size = CSW_16BIT;
307 return ERROR_TARGET_UNALIGNED_ACCESS;
309 retval = dap_setup_accessport_tar(dap, address);
310 if (retval != ERROR_OK)
314 uint32_t this_size = size;
316 /* Select packed transfer if possible */
317 if (addrinc && dap->packed_transfers && nbytes >= 4
318 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
320 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
322 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
325 if (retval != ERROR_OK)
328 /* How many source bytes each transfer will consume, and their location in the DRW,
329 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
330 uint32_t outvalue = 0;
333 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
334 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
336 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
338 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
343 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
344 if (retval != ERROR_OK)
347 /* Rewrite TAR if it wrapped */
348 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
349 retval = dap_setup_accessport_tar(dap, address);
350 if (retval != ERROR_OK)
355 /* REVISIT: Might want to have a queued version of this function that does not run. */
356 if (retval == ERROR_OK)
357 retval = dap_run(dap);
359 if (retval != ERROR_OK) {
361 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
362 && dap_run(dap) == ERROR_OK)
363 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
365 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
372 * Synchronous read of a block of memory, using a specific access size.
374 * @param dap The DAP connected to the MEM-AP.
375 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
376 * @param size Which access size to use, in bytes. 1, 2 or 4.
377 * @param count The number of reads to do (in size units, not bytes).
378 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
379 * @param addrinc Whether the target address should be increased after each read or not. This
380 * should normally be true, except when reading from e.g. a FIFO.
381 * @return ERROR_OK on success, otherwise an error code.
383 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
384 uint32_t adr, bool addrinc)
386 size_t nbytes = size * count;
387 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
389 uint32_t address = adr;
393 csw_size = CSW_32BIT;
395 csw_size = CSW_16BIT;
399 return ERROR_TARGET_UNALIGNED_ACCESS;
401 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
402 * over-allocation if packed transfers are going to be used, but determining the real need at
403 * this point would be messy. */
404 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
405 uint32_t *read_ptr = read_buf;
406 if (read_buf == NULL) {
407 LOG_ERROR("Failed to allocate read buffer");
411 retval = dap_setup_accessport_tar(dap, address);
412 if (retval != ERROR_OK)
415 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
416 * useful bytes it contains, and their location in the word, depends on the type of transfer
419 uint32_t this_size = size;
421 /* Select packed transfer if possible */
422 if (addrinc && dap->packed_transfers && nbytes >= 4
423 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
425 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
427 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
429 if (retval != ERROR_OK)
432 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
433 if (retval != ERROR_OK)
437 address += this_size;
439 /* Rewrite TAR if it wrapped */
440 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
441 retval = dap_setup_accessport_tar(dap, address);
442 if (retval != ERROR_OK)
447 if (retval == ERROR_OK)
448 retval = dap_run(dap);
452 nbytes = size * count;
455 /* If something failed, read TAR to find out how much data was successfully read, so we can
456 * at least give the caller what we have. */
457 if (retval != ERROR_OK) {
459 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
460 && dap_run(dap) == ERROR_OK) {
461 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
462 if (nbytes > tar - address)
463 nbytes = tar - address;
465 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
470 /* Replay loop to populate caller's buffer from the correct word and byte lane */
472 uint32_t this_size = size;
474 if (addrinc && dap->packed_transfers && nbytes >= 4
475 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
481 *buffer++ = *read_ptr >> 8 * (address++ & 3);
482 *buffer++ = *read_ptr >> 8 * (address++ & 3);
484 *buffer++ = *read_ptr >> 8 * (address++ & 3);
486 *buffer++ = *read_ptr >> 8 * (address++ & 3);
497 /*--------------------------------------------------------------------*/
498 /* Wrapping function with selection of AP */
499 /*--------------------------------------------------------------------*/
500 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
501 uint32_t address, uint32_t *value)
503 dap_ap_select(swjdp, ap);
504 return mem_ap_read_u32(swjdp, address, value);
507 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
508 uint32_t address, uint32_t value)
510 dap_ap_select(swjdp, ap);
511 return mem_ap_write_u32(swjdp, address, value);
514 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
515 uint32_t address, uint32_t *value)
517 dap_ap_select(swjdp, ap);
518 return mem_ap_read_atomic_u32(swjdp, address, value);
521 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
522 uint32_t address, uint32_t value)
524 dap_ap_select(swjdp, ap);
525 return mem_ap_write_atomic_u32(swjdp, address, value);
528 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
529 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
531 dap_ap_select(swjdp, ap);
532 return mem_ap_read(swjdp, buffer, size, count, address, true);
535 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
536 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
538 dap_ap_select(swjdp, ap);
539 return mem_ap_write(swjdp, buffer, size, count, address, true);
542 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
543 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
545 dap_ap_select(swjdp, ap);
546 return mem_ap_read(swjdp, buffer, size, count, address, false);
549 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
550 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
552 dap_ap_select(swjdp, ap);
553 return mem_ap_write(swjdp, buffer, size, count, address, false);
556 #define MDM_REG_STAT 0x00
557 #define MDM_REG_CTRL 0x04
558 #define MDM_REG_ID 0xfc
560 #define MDM_STAT_FMEACK (1<<0)
561 #define MDM_STAT_FREADY (1<<1)
562 #define MDM_STAT_SYSSEC (1<<2)
563 #define MDM_STAT_SYSRES (1<<3)
564 #define MDM_STAT_FMEEN (1<<5)
565 #define MDM_STAT_BACKDOOREN (1<<6)
566 #define MDM_STAT_LPEN (1<<7)
567 #define MDM_STAT_VLPEN (1<<8)
568 #define MDM_STAT_LLSMODEXIT (1<<9)
569 #define MDM_STAT_VLLSXMODEXIT (1<<10)
570 #define MDM_STAT_CORE_HALTED (1<<16)
571 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
572 #define MDM_STAT_CORESLEEPING (1<<18)
574 #define MEM_CTRL_FMEIP (1<<0)
575 #define MEM_CTRL_DBG_DIS (1<<1)
576 #define MEM_CTRL_DBG_REQ (1<<2)
577 #define MEM_CTRL_SYS_RES_REQ (1<<3)
578 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
579 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
580 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
581 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
583 #define MDM_ACCESS_TIMEOUT 3000 /* ms */
588 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
593 enum reset_types jtag_reset_config = jtag_get_reset_config();
595 dap_ap_select(dap, 1);
597 /* first check mdm-ap id register */
598 retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
599 if (retval != ERROR_OK)
603 if (val != 0x001C0000) {
604 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
605 dap_ap_select(dap, 0);
609 /* read and parse status register
610 * it's important that the device is out of
614 if (timeout++ > MDM_ACCESS_TIMEOUT) {
615 LOG_DEBUG("MDMAP : flash ready timeout");
618 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
619 if (retval != ERROR_OK)
623 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
624 if (val & MDM_STAT_FREADY)
629 if ((val & MDM_STAT_SYSSEC)) {
630 LOG_DEBUG("MDMAP: system is secured, masserase needed");
632 if (!(val & MDM_STAT_FMEEN))
633 LOG_DEBUG("MDMAP: masserase is disabled");
635 /* we need to assert reset */
636 if (jtag_reset_config & RESET_HAS_SRST) {
637 /* default to asserting srst */
638 adapter_assert_reset();
640 LOG_DEBUG("SRST not configured");
641 dap_ap_select(dap, 0);
646 if (timeout++ > MDM_ACCESS_TIMEOUT) {
647 LOG_DEBUG("MDMAP : flash ready timeout");
650 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
651 if (retval != ERROR_OK)
654 /* read status register and wait for ready */
655 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
656 if (retval != ERROR_OK)
659 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
667 if (timeout++ > MDM_ACCESS_TIMEOUT) {
668 LOG_DEBUG("MDMAP : flash ready timeout");
671 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
672 if (retval != ERROR_OK)
675 /* read status register */
676 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
677 if (retval != ERROR_OK)
680 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
681 /* read control register and wait for ready */
682 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
683 if (retval != ERROR_OK)
686 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
695 dap_ap_select(dap, 0);
701 struct dap_syssec_filter {
705 int (*dap_init)(struct adiv5_dap *dap);
709 static struct dap_syssec_filter dap_syssec_filter_data[] = {
710 { 0x4BA00477, dap_syssec_kinetis_mdmap }
716 int dap_syssec(struct adiv5_dap *dap)
719 struct jtag_tap *tap;
721 for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
722 tap = dap->jtag_info->tap;
724 while (tap != NULL) {
725 if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
726 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
727 dap_syssec_filter_data[i].dap_init(dap);
736 /*--------------------------------------------------------------------------*/
739 /* FIXME don't import ... just initialize as
740 * part of DAP transport setup
742 extern const struct dap_ops jtag_dp_ops;
744 /*--------------------------------------------------------------------------*/
747 * Initialize a DAP. This sets up the power domains, prepares the DP
748 * for further use, and arranges to use AP #0 for all AP operations
749 * until dap_ap-select() changes that policy.
751 * @param dap The DAP being initialized.
753 * @todo Rename this. We also need an initialization scheme which account
754 * for SWD transports not just JTAG; that will need to address differences
755 * in layering. (JTAG is useful without any debug target; but not SWD.)
756 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
758 int ahbap_debugport_init(struct adiv5_dap *dap)
766 /* JTAG-DP or SWJ-DP, in JTAG mode
767 * ... for SWD mode this is patched as part
771 dap->ops = &jtag_dp_ops;
773 /* Default MEM-AP setup.
775 * REVISIT AP #0 may be an inappropriate default for this.
776 * Should we probe, or take a hint from the caller?
777 * Presumably we can ignore the possibility of multiple APs.
779 dap->ap_current = !0;
780 dap_ap_select(dap, 0);
782 /* DP initialization */
784 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
785 if (retval != ERROR_OK)
788 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
789 if (retval != ERROR_OK)
792 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
793 if (retval != ERROR_OK)
796 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
797 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
798 if (retval != ERROR_OK)
801 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
802 if (retval != ERROR_OK)
804 retval = dap_run(dap);
805 if (retval != ERROR_OK)
808 /* Check that we have debug power domains activated */
809 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
810 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
811 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
812 if (retval != ERROR_OK)
814 retval = dap_run(dap);
815 if (retval != ERROR_OK)
820 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
821 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
822 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
823 if (retval != ERROR_OK)
825 retval = dap_run(dap);
826 if (retval != ERROR_OK)
831 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
832 if (retval != ERROR_OK)
834 /* With debug power on we can activate OVERRUN checking */
835 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
836 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
837 if (retval != ERROR_OK)
839 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
840 if (retval != ERROR_OK)
845 /* check that we support packed transfers */
848 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
849 if (retval != ERROR_OK)
852 retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
853 if (retval != ERROR_OK)
856 retval = dap_run(dap);
857 if (retval != ERROR_OK)
860 if (csw & CSW_ADDRINC_PACKED)
861 dap->packed_transfers = true;
863 dap->packed_transfers = false;
865 LOG_DEBUG("MEM_AP Packed Transfers: %s",
866 dap->packed_transfers ? "enabled" : "disabled");
871 /* CID interpretation -- see ARM IHI 0029B section 3
872 * and ARM IHI 0031A table 13-3.
874 static const char *class_description[16] = {
875 "Reserved", "ROM table", "Reserved", "Reserved",
876 "Reserved", "Reserved", "Reserved", "Reserved",
877 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
878 "Reserved", "OptimoDE DESS",
879 "Generic IP component", "PrimeCell or System component"
882 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
884 return cid3 == 0xb1 && cid2 == 0x05
885 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
889 * This function checks the ID for each access port to find the requested Access Port type
891 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
895 /* Maximum AP number is 255 since the SELECT register is 8 bits */
896 for (ap = 0; ap <= 255; ap++) {
898 /* read the IDR register of the Access Port */
900 dap_ap_select(dap, ap);
902 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
903 if (retval != ERROR_OK)
906 retval = dap_run(dap);
910 * 27-24 : JEDEC bank (0x4 for ARM)
911 * 23-17 : JEDEC code (0x3B for ARM)
914 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
917 /* Reading register for a non-existant AP should not cause an error,
918 * but just to be sure, try to continue searching if an error does happen.
920 if ((retval == ERROR_OK) && /* Register read success */
921 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
922 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
924 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
925 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
926 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
927 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
935 LOG_DEBUG("No %s found",
936 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
937 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
938 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
942 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
943 uint32_t *out_dbgbase, uint32_t *out_apid)
947 uint32_t dbgbase, apid;
949 /* AP address is in bits 31:24 of DP_SELECT */
951 return ERROR_COMMAND_SYNTAX_ERROR;
953 ap_old = dap->ap_current;
954 dap_ap_select(dap, ap);
956 retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
957 if (retval != ERROR_OK)
959 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
960 if (retval != ERROR_OK)
962 retval = dap_run(dap);
963 if (retval != ERROR_OK)
966 /* Excavate the device ID code */
967 struct jtag_tap *tap = dap->jtag_info->tap;
968 while (tap != NULL) {
973 if (tap == NULL || !tap->hasidcode)
976 dap_ap_select(dap, ap_old);
978 /* The asignment happens only here to prevent modification of these
979 * values before they are certain. */
980 *out_dbgbase = dbgbase;
986 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
987 uint32_t dbgbase, uint8_t type, uint32_t *addr)
990 uint32_t romentry, entry_offset = 0, component_base, devtype;
991 int retval = ERROR_FAIL;
994 return ERROR_COMMAND_SYNTAX_ERROR;
996 ap_old = dap->ap_current;
997 dap_ap_select(dap, ap);
1000 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1001 entry_offset, &romentry);
1002 if (retval != ERROR_OK)
1005 component_base = (dbgbase & 0xFFFFF000)
1006 + (romentry & 0xFFFFF000);
1008 if (romentry & 0x1) {
1009 retval = mem_ap_read_atomic_u32(dap,
1010 (component_base & 0xfffff000) | 0xfcc,
1012 if (retval != ERROR_OK)
1014 if ((devtype & 0xff) == type) {
1015 *addr = component_base;
1021 } while (romentry > 0);
1023 dap_ap_select(dap, ap_old);
1028 static int dap_rom_display(struct command_context *cmd_ctx,
1029 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
1032 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1033 uint16_t entry_offset;
1037 command_print(cmd_ctx, "\tTables too deep");
1042 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1044 /* bit 16 of apid indicates a memory access port */
1046 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
1048 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
1050 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1051 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1052 if (retval != ERROR_OK)
1054 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1055 if (retval != ERROR_OK)
1057 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1058 if (retval != ERROR_OK)
1060 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1061 if (retval != ERROR_OK)
1063 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1064 if (retval != ERROR_OK)
1066 retval = dap_run(dap);
1067 if (retval != ERROR_OK)
1070 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1071 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1076 (unsigned)cid3, (unsigned)cid2,
1077 (unsigned)cid1, (unsigned)cid0);
1079 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1081 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1083 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1084 for (entry_offset = 0; ; entry_offset += 4) {
1085 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1086 if (retval != ERROR_OK)
1088 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1089 tabs, entry_offset, romentry);
1090 if (romentry & 0x01) {
1091 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1092 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1093 uint32_t component_base;
1097 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1099 /* IDs are in last 4K section */
1100 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1101 if (retval != ERROR_OK) {
1102 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1103 ", the corresponding core might be turned off", tabs, component_base);
1107 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1108 if (retval != ERROR_OK)
1111 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1112 if (retval != ERROR_OK)
1115 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1116 if (retval != ERROR_OK)
1119 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1120 if (retval != ERROR_OK)
1124 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1125 if (retval != ERROR_OK)
1128 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1129 if (retval != ERROR_OK)
1132 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1133 if (retval != ERROR_OK)
1136 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1137 if (retval != ERROR_OK)
1141 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1142 "start address 0x%" PRIx32, component_base,
1143 /* component may take multiple 4K pages */
1144 (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1145 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1146 (c_cid1 >> 4) & 0xf,
1147 /* See ARM IHI 0029B Table 3-3 */
1148 class_description[(c_cid1 >> 4) & 0xf]);
1150 /* CoreSight component? */
1151 if (((c_cid1 >> 4) & 0x0f) == 9) {
1154 char *major = "Reserved", *subtype = "Reserved";
1156 retval = mem_ap_read_atomic_u32(dap,
1157 (component_base & 0xfffff000) | 0xfcc,
1159 if (retval != ERROR_OK)
1161 minor = (devtype >> 4) & 0x0f;
1162 switch (devtype & 0x0f) {
1164 major = "Miscellaneous";
1170 subtype = "Validation component";
1175 major = "Trace Sink";
1189 major = "Trace Link";
1195 subtype = "Funnel, router";
1201 subtype = "FIFO, buffer";
1206 major = "Trace Source";
1212 subtype = "Processor";
1218 subtype = "Engine/Coprocessor";
1226 major = "Debug Control";
1232 subtype = "Trigger Matrix";
1235 subtype = "Debug Auth";
1240 major = "Debug Logic";
1246 subtype = "Processor";
1252 subtype = "Engine/Coprocessor";
1257 command_print(cmd_ctx, "\t\tType is 0x%02x, %s, %s",
1260 /* REVISIT also show 0xfc8 DevId */
1263 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1264 command_print(cmd_ctx,
1273 command_print(cmd_ctx,
1274 "\t\tPeripheral ID[4..0] = hex "
1275 "%02x %02x %02x %02x %02x",
1276 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1277 (int)c_pid1, (int)c_pid0);
1279 /* Part number interpretations are from Cortex
1280 * core specs, the CoreSight components TRM
1281 * (ARM DDI 0314H), CoreSight System Design
1282 * Guide (ARM DGI 0012D) and ETM specs; also
1283 * from chip observation (e.g. TI SDTI).
1285 part_num = (c_pid0 & 0xff);
1286 part_num |= (c_pid1 & 0x0f) << 8;
1289 type = "Cortex-M3 NVIC";
1290 full = "(Interrupt Controller)";
1293 type = "Cortex-M3 ITM";
1294 full = "(Instrumentation Trace Module)";
1297 type = "Cortex-M3 DWT";
1298 full = "(Data Watchpoint and Trace)";
1301 type = "Cortex-M3 FBP";
1302 full = "(Flash Patch and Breakpoint)";
1305 type = "Cortex-M4 SCS";
1306 full = "(System Control Space)";
1309 type = "CoreSight ETM11";
1310 full = "(Embedded Trace)";
1312 /* case 0x113: what? */
1313 case 0x120: /* from OMAP3 memmap */
1315 full = "(System Debug Trace Interface)";
1317 case 0x343: /* from OMAP3 memmap */
1322 type = "Coresight CTI";
1323 full = "(Cross Trigger)";
1326 type = "Coresight ETB";
1327 full = "(Trace Buffer)";
1330 type = "Coresight CSTF";
1331 full = "(Trace Funnel)";
1334 type = "CoreSight ETM9";
1335 full = "(Embedded Trace)";
1338 type = "Coresight TPIU";
1339 full = "(Trace Port Interface Unit)";
1342 type = "Coresight ITM";
1343 full = "(Instrumentation Trace Macrocell)";
1346 type = "Cortex-A8 ETM";
1347 full = "(Embedded Trace)";
1350 type = "Cortex-A8 CTI";
1351 full = "(Cross Trigger)";
1354 type = "Cortex-M3 TPIU";
1355 full = "(Trace Port Interface Unit)";
1358 type = "Cortex-M3 ETM";
1359 full = "(Embedded Trace)";
1362 type = "Cortex-M4 ETM";
1363 full = "(Embedded Trace)";
1366 type = "Cortex-R4 ETM";
1367 full = "(Embedded Trace)";
1370 type = "CoreSight Component";
1371 full = "(unidentified Cortex-A9 component)";
1374 type = "CoreSight PMU";
1375 full = "(Performance Monitoring Unit)";
1378 type = "Cortex-M4 TPUI";
1379 full = "(Trace Port Interface Unit)";
1382 type = "Cortex-A8 Debug";
1383 full = "(Debug Unit)";
1386 type = "Cortex-A9 Debug";
1387 full = "(Debug Unit)";
1390 type = "-*- unrecognized -*-";
1394 command_print(cmd_ctx, "\t\tPart is %s %s",
1398 if (((c_cid1 >> 4) & 0x0f) == 1) {
1399 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1400 if (retval != ERROR_OK)
1405 command_print(cmd_ctx, "\t\tComponent not present");
1410 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1414 static int dap_info_command(struct command_context *cmd_ctx,
1415 struct adiv5_dap *dap, int ap)
1418 uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1419 int romtable_present = 0;
1423 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1424 if (retval != ERROR_OK)
1427 ap_old = dap->ap_current;
1428 dap_ap_select(dap, ap);
1430 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1431 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1432 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1434 switch (apid&0x0F) {
1436 command_print(cmd_ctx, "\tType is JTAG-AP");
1439 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1442 command_print(cmd_ctx, "\tType is MEM-AP APB");
1445 command_print(cmd_ctx, "\tUnknown AP type");
1449 /* NOTE: a MEM-AP may have a single CoreSight component that's
1450 * not a ROM table ... or have no such components at all.
1453 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1455 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1457 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1458 if (romtable_present) {
1459 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1461 command_print(cmd_ctx, "\tNo ROM table present");
1462 dap_ap_select(dap, ap_old);
1467 COMMAND_HANDLER(handle_dap_info_command)
1469 struct target *target = get_current_target(CMD_CTX);
1470 struct arm *arm = target_to_arm(target);
1471 struct adiv5_dap *dap = arm->dap;
1479 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1482 return ERROR_COMMAND_SYNTAX_ERROR;
1485 return dap_info_command(CMD_CTX, dap, apsel);
1488 COMMAND_HANDLER(dap_baseaddr_command)
1490 struct target *target = get_current_target(CMD_CTX);
1491 struct arm *arm = target_to_arm(target);
1492 struct adiv5_dap *dap = arm->dap;
1494 uint32_t apsel, baseaddr;
1502 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1503 /* AP address is in bits 31:24 of DP_SELECT */
1505 return ERROR_COMMAND_SYNTAX_ERROR;
1508 return ERROR_COMMAND_SYNTAX_ERROR;
1511 dap_ap_select(dap, apsel);
1513 /* NOTE: assumes we're talking to a MEM-AP, which
1514 * has a base address. There are other kinds of AP,
1515 * though they're not common for now. This should
1516 * use the ID register to verify it's a MEM-AP.
1518 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1519 if (retval != ERROR_OK)
1521 retval = dap_run(dap);
1522 if (retval != ERROR_OK)
1525 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1530 COMMAND_HANDLER(dap_memaccess_command)
1532 struct target *target = get_current_target(CMD_CTX);
1533 struct arm *arm = target_to_arm(target);
1534 struct adiv5_dap *dap = arm->dap;
1536 uint32_t memaccess_tck;
1540 memaccess_tck = dap->memaccess_tck;
1543 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1546 return ERROR_COMMAND_SYNTAX_ERROR;
1548 dap->memaccess_tck = memaccess_tck;
1550 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1551 dap->memaccess_tck);
1556 COMMAND_HANDLER(dap_apsel_command)
1558 struct target *target = get_current_target(CMD_CTX);
1559 struct arm *arm = target_to_arm(target);
1560 struct adiv5_dap *dap = arm->dap;
1562 uint32_t apsel, apid;
1570 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1571 /* AP address is in bits 31:24 of DP_SELECT */
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1576 return ERROR_COMMAND_SYNTAX_ERROR;
1580 dap_ap_select(dap, apsel);
1582 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1583 if (retval != ERROR_OK)
1585 retval = dap_run(dap);
1586 if (retval != ERROR_OK)
1589 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1595 COMMAND_HANDLER(dap_apcsw_command)
1597 struct target *target = get_current_target(CMD_CTX);
1598 struct arm *arm = target_to_arm(target);
1599 struct adiv5_dap *dap = arm->dap;
1601 uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1605 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1606 (dap->apsel), apcsw);
1609 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1610 /* AP address is in bits 31:24 of DP_SELECT */
1612 return ERROR_COMMAND_SYNTAX_ERROR;
1616 apcsw &= ~CSW_SPROT;
1619 return ERROR_COMMAND_SYNTAX_ERROR;
1621 dap->apcsw[dap->apsel] = apcsw;
1628 COMMAND_HANDLER(dap_apid_command)
1630 struct target *target = get_current_target(CMD_CTX);
1631 struct arm *arm = target_to_arm(target);
1632 struct adiv5_dap *dap = arm->dap;
1634 uint32_t apsel, apid;
1642 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1643 /* AP address is in bits 31:24 of DP_SELECT */
1645 return ERROR_COMMAND_SYNTAX_ERROR;
1648 return ERROR_COMMAND_SYNTAX_ERROR;
1651 dap_ap_select(dap, apsel);
1653 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1654 if (retval != ERROR_OK)
1656 retval = dap_run(dap);
1657 if (retval != ERROR_OK)
1660 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1665 static const struct command_registration dap_commands[] = {
1668 .handler = handle_dap_info_command,
1669 .mode = COMMAND_EXEC,
1670 .help = "display ROM table for MEM-AP "
1671 "(default currently selected AP)",
1672 .usage = "[ap_num]",
1676 .handler = dap_apsel_command,
1677 .mode = COMMAND_EXEC,
1678 .help = "Set the currently selected AP (default 0) "
1679 "and display the result",
1680 .usage = "[ap_num]",
1684 .handler = dap_apcsw_command,
1685 .mode = COMMAND_EXEC,
1686 .help = "Set csw access bit ",
1692 .handler = dap_apid_command,
1693 .mode = COMMAND_EXEC,
1694 .help = "return ID register from AP "
1695 "(default currently selected AP)",
1696 .usage = "[ap_num]",
1700 .handler = dap_baseaddr_command,
1701 .mode = COMMAND_EXEC,
1702 .help = "return debug base address from MEM-AP "
1703 "(default currently selected AP)",
1704 .usage = "[ap_num]",
1707 .name = "memaccess",
1708 .handler = dap_memaccess_command,
1709 .mode = COMMAND_EXEC,
1710 .help = "set/get number of extra tck for MEM-AP memory "
1711 "bus access [0-255]",
1712 .usage = "[cycles]",
1714 COMMAND_REGISTRATION_DONE
1717 const struct command_registration dap_command_handlers[] = {
1720 .mode = COMMAND_EXEC,
1721 .help = "DAP command group",
1723 .chain = dap_commands,
1725 COMMAND_REGISTRATION_DONE