1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "arm_adi_v5.h"
74 #include <helper/time_support.h>
77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
80 uint32_t tar_block_size(uint32_t address)
81 Return the largest block starting at address that does not cross a tar block size alignment boundary
83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
85 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
88 /***************************************************************************
90 * DPACC and APACC scanchain access through JTAG-DP *
92 ***************************************************************************/
95 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
96 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
97 * discusses operations which access these registers.
99 * Note that only one scan is performed. If RnW is set, a separate scan
100 * will be needed to collect the data which was read; the "invalue" collects
101 * the posted result of a preceding operation, not the current one.
103 * @param swjdp the DAP
104 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
105 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
106 * SELECT register has more addressing bits.
107 * @param RnW false iff outvalue will be written to the DP or AP
108 * @param outvalue points to a 32-bit (little-endian) integer
109 * @param invalue NULL, or points to a 32-bit (little-endian) integer
110 * @param ack points to where the three bit JTAG_ACK_* code will be stored
112 static int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
113 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
114 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
116 struct arm_jtag *jtag_info = swjdp->jtag_info;
117 struct scan_field fields[2];
118 uint8_t out_addr_buf;
120 jtag_set_end_state(TAP_IDLE);
121 arm_jtag_set_instr(jtag_info, instr, NULL);
123 /* Scan out a read or write operation using some DP or AP register.
124 * For APACC access with any sticky error flag set, this is discarded.
126 fields[0].num_bits = 3;
127 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
128 fields[0].out_value = &out_addr_buf;
129 fields[0].in_value = ack;
131 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
132 * complete; data we write is discarded, data we read is unpredictable.
133 * When overrun detect is active, STICKYORUN is set.
136 fields[1].num_bits = 32;
137 fields[1].out_value = outvalue;
138 fields[1].in_value = invalue;
140 jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
142 /* Add specified number of tck clocks after starting memory bus
143 * access, giving the hardware time to complete the access.
144 * They provide more time for the (MEM) AP to complete the read ...
145 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
147 if ((instr == JTAG_DP_APACC)
148 && ((reg_addr == AP_REG_DRW)
149 || ((reg_addr & 0xF0) == AP_REG_BD0))
150 && (swjdp->memaccess_tck != 0))
151 jtag_add_runtest(swjdp->memaccess_tck,
152 jtag_set_end_state(TAP_IDLE));
154 return jtag_get_error();
158 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
159 * This is exactly like adi_jtag_dp_scan(), except that endianness
160 * conversions are performed (so the types of invalue and outvalue
161 * must be different).
163 static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
164 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
165 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
167 uint8_t out_value_buf[4];
170 buf_set_u32(out_value_buf, 0, 32, outvalue);
172 retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
173 out_value_buf, (uint8_t *)invalue, ack);
174 if (retval != ERROR_OK)
178 jtag_add_callback(arm_le_to_h_u32,
179 (jtag_callback_data_t) invalue);
185 * Utility to write AP registers.
187 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
188 uint8_t reg_addr, uint8_t *outvalue)
190 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
191 outvalue, NULL, NULL);
194 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
195 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
196 uint32_t outvalue, uint32_t *invalue)
200 /* Issue the read or write */
201 retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
202 RnW, outvalue, NULL, NULL);
203 if (retval != ERROR_OK)
206 /* For reads, collect posted value; RDBUFF has no other effect.
207 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
209 if ((RnW == DPAP_READ) && (invalue != NULL))
210 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
211 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
215 static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
220 /* too expensive to call keep_alive() here */
223 /* Danger!!!! BROKEN!!!! */
224 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
225 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
226 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
227 R956 introduced the check on return value here and now Michael Schwingen reports
228 that this code no longer works....
230 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
232 if ((retval = jtag_execute_queue()) != ERROR_OK)
234 LOG_ERROR("BUG: Why does this fail the first time????");
236 /* Why??? second time it works??? */
239 /* Post CTRL/STAT read; discard any previous posted read value
240 * but collect its ACK status.
242 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
243 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
244 if ((retval = jtag_execute_queue()) != ERROR_OK)
247 swjdp->ack = swjdp->ack & 0x7;
249 /* common code path avoids calling timeval_ms() */
250 if (swjdp->ack != JTAG_ACK_OK_FAULT)
252 long long then = timeval_ms();
254 while (swjdp->ack != JTAG_ACK_OK_FAULT)
256 if (swjdp->ack == JTAG_ACK_WAIT)
258 if ((timeval_ms()-then) > 1000)
260 /* NOTE: this would be a good spot
261 * to use JTAG_DP_ABORT.
263 LOG_WARNING("Timeout (1000ms) waiting "
265 "in JTAG-DP transaction");
266 return ERROR_JTAG_DEVICE_ERROR;
271 LOG_WARNING("Invalid ACK %#x "
272 "in JTAG-DP transaction",
274 return ERROR_JTAG_DEVICE_ERROR;
277 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
278 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
279 if ((retval = dap_run(swjdp)) != ERROR_OK)
281 swjdp->ack = swjdp->ack & 0x7;
285 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
287 /* Check for STICKYERR and STICKYORUN */
288 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
290 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
291 /* Check power to debug regions */
292 if ((ctrlstat & 0xf0000000) != 0xf0000000)
293 ahbap_debugport_init(swjdp);
296 uint32_t mem_ap_csw, mem_ap_tar;
298 /* Maybe print information about last intended
299 * MEM-AP access; but not if autoincrementing.
300 * *Real* CSW and TAR values are always shown.
302 if (swjdp->ap_tar_value != (uint32_t) -1)
303 LOG_DEBUG("MEM-AP Cached values: "
305 ", ap_csw 0x%" PRIx32
306 ", ap_tar 0x%" PRIx32,
307 swjdp->ap_bank_value,
309 swjdp->ap_tar_value);
311 if (ctrlstat & SSTICKYORUN)
312 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
313 "memaccess, or reduce jtag speed");
315 if (ctrlstat & SSTICKYERR)
316 LOG_ERROR("JTAG-DP STICKY ERROR");
318 /* Clear Sticky Error Bits */
319 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
320 DP_CTRL_STAT, DPAP_WRITE,
321 swjdp->dp_ctrl_stat | SSTICKYORUN
323 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
324 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
325 if ((retval = dap_run(swjdp)) != ERROR_OK)
328 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
330 retval = dap_queue_ap_read(swjdp,
331 AP_REG_CSW, &mem_ap_csw);
332 if (retval != ERROR_OK)
335 retval = dap_queue_ap_read(swjdp,
336 AP_REG_TAR, &mem_ap_tar);
337 if (retval != ERROR_OK)
340 if ((retval = dap_run(swjdp)) != ERROR_OK)
342 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
343 PRIx32, mem_ap_csw, mem_ap_tar);
346 if ((retval = dap_run(swjdp)) != ERROR_OK)
348 return ERROR_JTAG_DEVICE_ERROR;
354 /***************************************************************************
356 * DP and MEM-AP register access through APACC and DPACC *
358 ***************************************************************************/
361 * Select one of the APs connected to the specified DAP. The
362 * selection is implicitly used with future AP transactions.
363 * This is a NOP if the specified AP is already selected.
365 * @param swjdp The DAP
366 * @param apsel Number of the AP to (implicitly) use with further
367 * transactions. This normally identifies a MEM-AP.
369 void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
371 uint32_t select = (apsel << 24) & 0xFF000000;
373 if (select != swjdp->apsel)
375 swjdp->apsel = select;
376 /* Switching AP invalidates cached values.
377 * Values MUST BE UPDATED BEFORE AP ACCESS.
379 swjdp->ap_bank_value = -1;
380 swjdp->ap_csw_value = -1;
381 swjdp->ap_tar_value = -1;
386 * Queue transactions setting up transfer parameters for the
387 * currently selected MEM-AP.
389 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
390 * initiate data reads or writes using memory or peripheral addresses.
391 * If the CSW is configured for it, the TAR may be automatically
392 * incremented after each transfer.
394 * @todo Rename to reflect it being specifically a MEM-AP function.
396 * @param swjdp The DAP connected to the MEM-AP.
397 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
398 * matches the cached value, the register is not changed.
399 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
400 * matches the cached address, the register is not changed.
402 * @return ERROR_OK if the transaction was properly queued, else a fault code.
404 int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
408 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
409 if (csw != swjdp->ap_csw_value)
411 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
412 retval = dap_queue_ap_write(swjdp, AP_REG_CSW, csw);
413 if (retval != ERROR_OK)
415 swjdp->ap_csw_value = csw;
417 if (tar != swjdp->ap_tar_value)
419 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
420 retval = dap_queue_ap_write(swjdp, AP_REG_TAR, tar);
421 if (retval != ERROR_OK)
423 swjdp->ap_tar_value = tar;
425 /* Disable TAR cache when autoincrementing */
426 if (csw & CSW_ADDRINC_MASK)
427 swjdp->ap_tar_value = -1;
432 * Asynchronous (queued) read of a word from memory or a system register.
434 * @param swjdp The DAP connected to the MEM-AP performing the read.
435 * @param address Address of the 32-bit word to read; it must be
436 * readable by the currently selected MEM-AP.
437 * @param value points to where the word will be stored when the
438 * transaction queue is flushed (assuming no errors).
440 * @return ERROR_OK for success. Otherwise a fault code.
442 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
447 /* Use banked addressing (REG_BDx) to avoid some link traffic
448 * (updating TAR) when reading several consecutive addresses.
450 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
451 address & 0xFFFFFFF0);
452 if (retval != ERROR_OK)
455 return dap_queue_ap_read(swjdp, AP_REG_BD0 | (address & 0xC), value);
459 * Synchronous read of a word from memory or a system register.
460 * As a side effect, this flushes any queued transactions.
462 * @param swjdp The DAP connected to the MEM-AP performing the read.
463 * @param address Address of the 32-bit word to read; it must be
464 * readable by the currently selected MEM-AP.
465 * @param value points to where the result will be stored.
467 * @return ERROR_OK for success; *value holds the result.
468 * Otherwise a fault code.
470 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
475 retval = mem_ap_read_u32(swjdp, address, value);
476 if (retval != ERROR_OK)
479 return dap_run(swjdp);
483 * Asynchronous (queued) write of a word to memory or a system register.
485 * @param swjdp The DAP connected to the MEM-AP.
486 * @param address Address to be written; it must be writable by
487 * the currently selected MEM-AP.
488 * @param value Word that will be written to the address when transaction
489 * queue is flushed (assuming no errors).
491 * @return ERROR_OK for success. Otherwise a fault code.
493 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
498 /* Use banked addressing (REG_BDx) to avoid some link traffic
499 * (updating TAR) when writing several consecutive addresses.
501 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
502 address & 0xFFFFFFF0);
503 if (retval != ERROR_OK)
506 return dap_queue_ap_write(swjdp, AP_REG_BD0 | (address & 0xC),
511 * Synchronous write of a word to memory or a system register.
512 * As a side effect, this flushes any queued transactions.
514 * @param swjdp The DAP connected to the MEM-AP.
515 * @param address Address to be written; it must be writable by
516 * the currently selected MEM-AP.
517 * @param value Word that will be written.
519 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
521 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
524 int retval = mem_ap_write_u32(swjdp, address, value);
526 if (retval != ERROR_OK)
529 return dap_run(swjdp);
532 /*****************************************************************************
534 * mem_ap_write_buf(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address) *
536 * Write a buffer in target order (little endian) *
538 *****************************************************************************/
539 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
541 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
542 uint32_t adr = address;
543 uint8_t* pBuffer = buffer;
548 /* if we have an unaligned access - reorder data */
551 for (writecount = 0; writecount < count; writecount++)
555 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
557 for (i = 0; i < 4; i++)
559 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
563 pBuffer += sizeof(uint32_t);
569 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
570 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
571 if (wcount < blocksize)
574 /* handle unaligned data at 4k boundary */
578 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
580 for (writecount = 0; writecount < blocksize; writecount++)
582 retval = dap_queue_ap_write(swjdp, AP_REG_DRW,
583 *(uint32_t *) (buffer + 4 * writecount));
584 if (retval != ERROR_OK)
588 if (dap_run(swjdp) == ERROR_OK)
590 wcount = wcount - blocksize;
591 address = address + 4 * blocksize;
592 buffer = buffer + 4 * blocksize;
601 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
602 /* REVISIT return the *actual* fault code */
603 return ERROR_JTAG_DEVICE_ERROR;
610 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
611 uint8_t *buffer, int count, uint32_t address)
613 int retval = ERROR_OK;
614 int wcount, blocksize, writecount, i;
622 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
623 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
625 if (wcount < blocksize)
628 /* handle unaligned data at 4k boundary */
632 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
633 writecount = blocksize;
637 nbytes = MIN((writecount << 1), 4);
641 if (mem_ap_write_buf_u16(swjdp, buffer,
642 nbytes, address) != ERROR_OK)
644 LOG_WARNING("Block write error address "
645 "0x%" PRIx32 ", count 0x%x",
647 return ERROR_JTAG_DEVICE_ERROR;
650 address += nbytes >> 1;
655 memcpy(&outvalue, buffer, sizeof(uint32_t));
657 for (i = 0; i < nbytes; i++)
659 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
664 memcpy(&outvalue, buffer, sizeof(uint32_t));
665 retval = dap_queue_ap_write(swjdp,
666 AP_REG_DRW, outvalue);
667 if (retval != ERROR_OK)
670 if (dap_run(swjdp) != ERROR_OK)
672 LOG_WARNING("Block write error address "
673 "0x%" PRIx32 ", count 0x%x",
675 /* REVISIT return *actual* fault code */
676 return ERROR_JTAG_DEVICE_ERROR;
680 buffer += nbytes >> 1;
681 writecount -= nbytes >> 1;
683 } while (writecount);
690 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
692 int retval = ERROR_OK;
695 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
699 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
701 memcpy(&svalue, buffer, sizeof(uint16_t));
702 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
703 retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
704 if (retval != ERROR_OK)
707 retval = dap_run(swjdp);
708 if (retval != ERROR_OK)
719 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
720 uint8_t *buffer, int count, uint32_t address)
722 int retval = ERROR_OK;
723 int wcount, blocksize, writecount, i;
731 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
732 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
734 if (wcount < blocksize)
737 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
738 writecount = blocksize;
742 nbytes = MIN(writecount, 4);
746 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
748 LOG_WARNING("Block write error address "
749 "0x%" PRIx32 ", count 0x%x",
751 return ERROR_JTAG_DEVICE_ERROR;
759 memcpy(&outvalue, buffer, sizeof(uint32_t));
761 for (i = 0; i < nbytes; i++)
763 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
768 memcpy(&outvalue, buffer, sizeof(uint32_t));
769 retval = dap_queue_ap_write(swjdp,
770 AP_REG_DRW, outvalue);
771 if (retval != ERROR_OK)
774 if (dap_run(swjdp) != ERROR_OK)
776 LOG_WARNING("Block write error address "
777 "0x%" PRIx32 ", count 0x%x",
779 /* REVISIT return *actual* fault code */
780 return ERROR_JTAG_DEVICE_ERROR;
785 writecount -= nbytes;
787 } while (writecount);
794 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
796 int retval = ERROR_OK;
799 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
803 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
804 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
805 retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
806 if (retval != ERROR_OK)
809 retval = dap_run(swjdp);
810 if (retval != ERROR_OK)
822 * Synchronously read a block of 32-bit words into a buffer
823 * @param swjdp The DAP connected to the MEM-AP.
824 * @param buffer where the words will be stored (in host byte order).
825 * @param count How many words to read.
826 * @param address Memory address from which to read words; all the
827 * words must be readable by the currently selected MEM-AP.
829 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
830 int count, uint32_t address)
832 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
833 uint32_t adr = address;
834 uint8_t* pBuffer = buffer;
841 /* Adjust to read blocks within boundaries aligned to the
842 * TAR autoincrement size (at least 2^10). Autoincrement
843 * mode avoids an extra per-word roundtrip to update TAR.
845 blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
847 if (wcount < blocksize)
850 /* handle unaligned data at 4k boundary */
854 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
857 /* FIXME remove these three calls to adi_jtag_dp_scan(),
858 * so this routine becomes transport-neutral. Be careful
859 * not to cause performance problems with JTAG; would it
860 * suffice to loop over dap_queue_ap_read(), or would that
861 * be slower when JTAG is the chosen transport?
864 /* Scan out first read */
865 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
866 DPAP_READ, 0, NULL, NULL);
867 for (readcount = 0; readcount < blocksize - 1; readcount++)
869 /* Scan out next read; scan in posted value for the
870 * previous one. Assumes read is acked "OK/FAULT",
871 * and CTRL_STAT says that meant "OK".
873 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
874 DPAP_READ, 0, buffer + 4 * readcount,
878 /* Scan in last posted value; RDBUFF has no other effect,
879 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
881 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
882 DPAP_READ, 0, buffer + 4 * readcount,
884 if (dap_run(swjdp) == ERROR_OK)
886 wcount = wcount - blocksize;
887 address += 4 * blocksize;
888 buffer += 4 * blocksize;
897 LOG_WARNING("Block read error address 0x%" PRIx32
898 ", count 0x%x", address, count);
899 /* REVISIT return the *actual* fault code */
900 return ERROR_JTAG_DEVICE_ERROR;
904 /* if we have an unaligned access - reorder data */
907 for (readcount = 0; readcount < count; readcount++)
911 memcpy(&data, pBuffer, sizeof(uint32_t));
913 for (i = 0; i < 4; i++)
915 *((uint8_t*)pBuffer) =
916 (data >> 8 * (adr & 0x3));
926 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
927 uint8_t *buffer, int count, uint32_t address)
930 int retval = ERROR_OK;
931 int wcount, blocksize, readcount, i;
939 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
940 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
941 if (wcount < blocksize)
944 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
946 /* handle unaligned data at 4k boundary */
949 readcount = blocksize;
953 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
954 if (dap_run(swjdp) != ERROR_OK)
956 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
957 /* REVISIT return the *actual* fault code */
958 return ERROR_JTAG_DEVICE_ERROR;
961 nbytes = MIN((readcount << 1), 4);
963 for (i = 0; i < nbytes; i++)
965 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
970 readcount -= (nbytes >> 1);
979 * Synchronously read a block of 16-bit halfwords into a buffer
980 * @param swjdp The DAP connected to the MEM-AP.
981 * @param buffer where the halfwords will be stored (in host byte order).
982 * @param count How many halfwords to read.
983 * @param address Memory address from which to read words; all the
984 * words must be readable by the currently selected MEM-AP.
986 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
987 int count, uint32_t address)
990 int retval = ERROR_OK;
993 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
997 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
998 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
999 if (retval != ERROR_OK)
1002 retval = dap_run(swjdp);
1003 if (retval != ERROR_OK)
1008 for (i = 0; i < 2; i++)
1010 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1017 uint16_t svalue = (invalue >> 8 * (address & 0x3));
1018 memcpy(buffer, &svalue, sizeof(uint16_t));
1028 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1029 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1031 * The solution is to arrange for a large out/in scan in this loop and
1032 * and convert data afterwards.
1034 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
1035 uint8_t *buffer, int count, uint32_t address)
1038 int retval = ERROR_OK;
1039 int wcount, blocksize, readcount, i;
1047 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1048 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1050 if (wcount < blocksize)
1053 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1054 readcount = blocksize;
1058 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
1059 if (dap_run(swjdp) != ERROR_OK)
1061 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1062 /* REVISIT return the *actual* fault code */
1063 return ERROR_JTAG_DEVICE_ERROR;
1066 nbytes = MIN(readcount, 4);
1068 for (i = 0; i < nbytes; i++)
1070 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1075 readcount -= nbytes;
1076 } while (readcount);
1077 wcount -= blocksize;
1084 * Synchronously read a block of bytes into a buffer
1085 * @param swjdp The DAP connected to the MEM-AP.
1086 * @param buffer where the bytes will be stored.
1087 * @param count How many bytes to read.
1088 * @param address Memory address from which to read data; all the
1089 * data must be readable by the currently selected MEM-AP.
1091 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer,
1092 int count, uint32_t address)
1095 int retval = ERROR_OK;
1098 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1102 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1103 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
1104 retval = dap_run(swjdp);
1105 if (retval != ERROR_OK)
1108 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1117 /*--------------------------------------------------------------------------*/
1119 static int jtag_idcode_q_read(struct adiv5_dap *dap,
1120 uint8_t *ack, uint32_t *data)
1122 struct arm_jtag *jtag_info = dap->jtag_info;
1124 struct scan_field fields[1];
1126 jtag_set_end_state(TAP_IDLE);
1128 /* This is a standard JTAG operation -- no DAP tweakage */
1129 retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL);
1130 if (retval != ERROR_OK)
1133 fields[0].num_bits = 32;
1134 fields[0].out_value = NULL;
1135 fields[0].in_value = (void *) data;
1137 jtag_add_dr_scan(jtag_info->tap, 1, fields, jtag_get_end_state());
1138 retval = jtag_get_error();
1139 if (retval != ERROR_OK)
1142 jtag_add_callback(arm_le_to_h_u32,
1143 (jtag_callback_data_t) data);
1148 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
1151 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
1152 reg, DPAP_READ, 0, data);
1155 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
1158 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
1159 reg, DPAP_WRITE, data, NULL);
1162 /** Select the AP register bank matching bits 7:4 of reg. */
1163 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
1165 uint32_t select = reg & 0x000000F0;
1167 if (select == dap->ap_bank_value)
1169 dap->ap_bank_value = select;
1171 select |= dap->apsel;
1173 return jtag_dp_q_write(dap, DP_SELECT, select);
1176 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
1179 int retval = jtag_ap_q_bankselect(dap, reg);
1181 if (retval != ERROR_OK)
1184 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
1185 DPAP_READ, 0, data);
1188 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
1191 uint8_t out_value_buf[4];
1193 int retval = jtag_ap_q_bankselect(dap, reg);
1194 if (retval != ERROR_OK)
1197 buf_set_u32(out_value_buf, 0, 32, data);
1199 return adi_jtag_ap_write_check(dap, reg, out_value_buf);
1202 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
1204 /* for JTAG, this is the only valid ABORT register operation */
1205 return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
1206 0, DPAP_WRITE, 1, NULL, ack);
1209 static int jtag_dp_run(struct adiv5_dap *dap)
1211 return jtagdp_transaction_endcheck(dap);
1214 static const struct dap_ops jtag_dp_ops = {
1215 .queue_idcode_read = jtag_idcode_q_read,
1216 .queue_dp_read = jtag_dp_q_read,
1217 .queue_dp_write = jtag_dp_q_write,
1218 .queue_ap_read = jtag_ap_q_read,
1219 .queue_ap_write = jtag_ap_q_write,
1220 .queue_ap_abort = jtag_ap_q_abort,
1224 /*--------------------------------------------------------------------------*/
1227 * Initialize a DAP. This sets up the power domains, prepares the DP
1228 * for further use, and arranges to use AP #0 for all AP operations
1229 * until dap_ap-select() changes that policy.
1231 * @param swjdp The DAP being initialized.
1233 * @todo Rename this. We also need an initialization scheme which account
1234 * for SWD transports not just JTAG; that will need to address differences
1235 * in layering. (JTAG is useful without any debug target; but not SWD.)
1236 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1238 int ahbap_debugport_init(struct adiv5_dap *swjdp)
1240 uint32_t idreg, romaddr, dummy;
1247 /* JTAG-DP or SWJ-DP, in JTAG mode */
1248 swjdp->ops = &jtag_dp_ops;
1250 /* Default MEM-AP setup.
1252 * REVISIT AP #0 may be an inappropriate default for this.
1253 * Should we probe, or take a hint from the caller?
1254 * Presumably we can ignore the possibility of multiple APs.
1257 dap_ap_select(swjdp, 0);
1259 /* DP initialization */
1261 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1262 if (retval != ERROR_OK)
1265 retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, SSTICKYERR);
1266 if (retval != ERROR_OK)
1269 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1270 if (retval != ERROR_OK)
1273 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1274 retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
1275 if (retval != ERROR_OK)
1278 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1279 if (retval != ERROR_OK)
1281 if ((retval = dap_run(swjdp)) != ERROR_OK)
1284 /* Check that we have debug power domains activated */
1285 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1287 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1288 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1289 if (retval != ERROR_OK)
1291 if ((retval = dap_run(swjdp)) != ERROR_OK)
1296 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1298 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1299 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1300 if (retval != ERROR_OK)
1302 if ((retval = dap_run(swjdp)) != ERROR_OK)
1307 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1308 if (retval != ERROR_OK)
1310 /* With debug power on we can activate OVERRUN checking */
1311 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1312 retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
1313 if (retval != ERROR_OK)
1315 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1316 if (retval != ERROR_OK)
1320 * REVISIT this isn't actually *initializing* anything in an AP,
1321 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1322 * Should it? If the ROM address is valid, is this the right
1323 * place to scan the table and do any topology detection?
1325 retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &idreg);
1326 retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &romaddr);
1328 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1329 ", Debug ROM Address 0x%" PRIx32,
1330 swjdp->apsel, idreg, romaddr);
1335 /* CID interpretation -- see ARM IHI 0029B section 3
1336 * and ARM IHI 0031A table 13-3.
1338 static const char *class_description[16] ={
1339 "Reserved", "ROM table", "Reserved", "Reserved",
1340 "Reserved", "Reserved", "Reserved", "Reserved",
1341 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1342 "Reserved", "OptimoDE DESS",
1343 "Generic IP component", "PrimeCell or System component"
1347 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1349 return cid3 == 0xb1 && cid2 == 0x05
1350 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1353 static int dap_info_command(struct command_context *cmd_ctx,
1354 struct adiv5_dap *swjdp, int apsel)
1357 uint32_t dbgbase, apid;
1358 int romtable_present = 0;
1362 /* AP address is in bits 31:24 of DP_SELECT */
1364 return ERROR_INVALID_ARGUMENTS;
1366 apselold = swjdp->apsel;
1367 dap_ap_select(swjdp, apsel);
1368 retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &dbgbase);
1369 retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &apid);
1370 retval = dap_run(swjdp);
1371 if (retval != ERROR_OK)
1374 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1375 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1376 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1382 command_print(cmd_ctx, "\tType is JTAG-AP");
1385 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1388 command_print(cmd_ctx, "\tType is MEM-AP APB");
1391 command_print(cmd_ctx, "\tUnknown AP type");
1395 /* NOTE: a MEM-AP may have a single CoreSight component that's
1396 * not a ROM table ... or have no such components at all.
1399 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1404 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1407 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1408 if (romtable_present)
1410 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1411 uint16_t entry_offset;
1413 /* bit 16 of apid indicates a memory access port */
1415 command_print(cmd_ctx, "\tValid ROM table present");
1417 command_print(cmd_ctx, "\tROM table in legacy format");
1419 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1420 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1421 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1422 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1423 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1424 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1425 retval = dap_run(swjdp);
1426 if (retval != ERROR_OK)
1429 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1430 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1431 ", CID2 0x%2.2" PRIx32
1432 ", CID1 0x%2.2" PRIx32
1433 ", CID0 0x%2.2" PRIx32,
1434 cid3, cid2, cid1, cid0);
1436 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1438 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1439 "Dedicated debug bus.");
1441 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1445 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1446 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1449 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1450 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1451 uint32_t component_start, component_base;
1455 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1456 + (int)(romentry & 0xFFFFF000));
1457 mem_ap_read_atomic_u32(swjdp,
1458 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1459 mem_ap_read_atomic_u32(swjdp,
1460 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1461 mem_ap_read_atomic_u32(swjdp,
1462 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1463 mem_ap_read_atomic_u32(swjdp,
1464 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1465 mem_ap_read_atomic_u32(swjdp,
1466 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1467 mem_ap_read_atomic_u32(swjdp,
1468 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1469 mem_ap_read_atomic_u32(swjdp,
1470 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1471 mem_ap_read_atomic_u32(swjdp,
1472 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1473 mem_ap_read_atomic_u32(swjdp,
1474 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1475 component_start = component_base - 0x1000*(c_pid4 >> 4);
1477 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1478 ", start address 0x%" PRIx32,
1479 component_base, component_start);
1480 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1481 (int) (c_cid1 >> 4) & 0xf,
1482 /* See ARM IHI 0029B Table 3-3 */
1483 class_description[(c_cid1 >> 4) & 0xf]);
1485 /* CoreSight component? */
1486 if (((c_cid1 >> 4) & 0x0f) == 9) {
1489 char *major = "Reserved", *subtype = "Reserved";
1491 mem_ap_read_atomic_u32(swjdp,
1492 (component_base & 0xfffff000) | 0xfcc,
1494 minor = (devtype >> 4) & 0x0f;
1495 switch (devtype & 0x0f) {
1497 major = "Miscellaneous";
1503 subtype = "Validation component";
1508 major = "Trace Sink";
1522 major = "Trace Link";
1528 subtype = "Funnel, router";
1534 subtype = "FIFO, buffer";
1539 major = "Trace Source";
1545 subtype = "Processor";
1551 subtype = "Engine/Coprocessor";
1559 major = "Debug Control";
1565 subtype = "Trigger Matrix";
1568 subtype = "Debug Auth";
1573 major = "Debug Logic";
1579 subtype = "Processor";
1585 subtype = "Engine/Coprocessor";
1590 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1591 (unsigned) (devtype & 0xff),
1593 /* REVISIT also show 0xfc8 DevId */
1596 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1597 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1598 ", CID2 0x%2.2" PRIx32
1599 ", CID1 0x%2.2" PRIx32
1600 ", CID0 0x%2.2" PRIx32,
1601 c_cid3, c_cid2, c_cid1, c_cid0);
1602 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1603 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1605 (int) c_pid3, (int) c_pid2,
1606 (int) c_pid1, (int) c_pid0);
1608 /* Part number interpretations are from Cortex
1609 * core specs, the CoreSight components TRM
1610 * (ARM DDI 0314H), and ETM specs; also from
1611 * chip observation (e.g. TI SDTI).
1613 part_num = c_pid0 & 0xff;
1614 part_num |= (c_pid1 & 0x0f) << 8;
1617 type = "Cortex-M3 NVIC";
1618 full = "(Interrupt Controller)";
1621 type = "Cortex-M3 ITM";
1622 full = "(Instrumentation Trace Module)";
1625 type = "Cortex-M3 DWT";
1626 full = "(Data Watchpoint and Trace)";
1629 type = "Cortex-M3 FBP";
1630 full = "(Flash Patch and Breakpoint)";
1633 type = "CoreSight ETM11";
1634 full = "(Embedded Trace)";
1636 // case 0x113: what?
1637 case 0x120: /* from OMAP3 memmap */
1639 full = "(System Debug Trace Interface)";
1641 case 0x343: /* from OMAP3 memmap */
1646 type = "Coresight CTI";
1647 full = "(Cross Trigger)";
1650 type = "Coresight ETB";
1651 full = "(Trace Buffer)";
1654 type = "Coresight CSTF";
1655 full = "(Trace Funnel)";
1658 type = "CoreSight ETM9";
1659 full = "(Embedded Trace)";
1662 type = "Coresight TPIU";
1663 full = "(Trace Port Interface Unit)";
1666 type = "Cortex-A8 ETM";
1667 full = "(Embedded Trace)";
1670 type = "Cortex-A8 CTI";
1671 full = "(Cross Trigger)";
1674 type = "Cortex-M3 TPIU";
1675 full = "(Trace Port Interface Unit)";
1678 type = "Cortex-M3 ETM";
1679 full = "(Embedded Trace)";
1682 type = "Cortex-A8 Debug";
1683 full = "(Debug Unit)";
1686 type = "-*- unrecognized -*-";
1690 command_print(cmd_ctx, "\t\tPart is %s %s",
1696 command_print(cmd_ctx, "\t\tComponent not present");
1698 command_print(cmd_ctx, "\t\tEnd of ROM table");
1701 } while (romentry > 0);
1705 command_print(cmd_ctx, "\tNo ROM table present");
1707 dap_ap_select(swjdp, apselold);
1712 COMMAND_HANDLER(handle_dap_info_command)
1714 struct target *target = get_current_target(CMD_CTX);
1715 struct arm *arm = target_to_arm(target);
1716 struct adiv5_dap *dap = arm->dap;
1724 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1727 return ERROR_COMMAND_SYNTAX_ERROR;
1730 return dap_info_command(CMD_CTX, dap, apsel);
1733 COMMAND_HANDLER(dap_baseaddr_command)
1735 struct target *target = get_current_target(CMD_CTX);
1736 struct arm *arm = target_to_arm(target);
1737 struct adiv5_dap *dap = arm->dap;
1739 uint32_t apsel, apselsave, baseaddr;
1742 apselsave = dap->apsel;
1748 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1749 /* AP address is in bits 31:24 of DP_SELECT */
1751 return ERROR_INVALID_ARGUMENTS;
1754 return ERROR_COMMAND_SYNTAX_ERROR;
1757 if (apselsave != apsel)
1758 dap_ap_select(dap, apsel);
1760 /* NOTE: assumes we're talking to a MEM-AP, which
1761 * has a base address. There are other kinds of AP,
1762 * though they're not common for now. This should
1763 * use the ID register to verify it's a MEM-AP.
1765 retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1766 retval = dap_run(dap);
1767 if (retval != ERROR_OK)
1770 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1772 if (apselsave != apsel)
1773 dap_ap_select(dap, apselsave);
1778 COMMAND_HANDLER(dap_memaccess_command)
1780 struct target *target = get_current_target(CMD_CTX);
1781 struct arm *arm = target_to_arm(target);
1782 struct adiv5_dap *dap = arm->dap;
1784 uint32_t memaccess_tck;
1788 memaccess_tck = dap->memaccess_tck;
1791 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1794 return ERROR_COMMAND_SYNTAX_ERROR;
1796 dap->memaccess_tck = memaccess_tck;
1798 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1799 dap->memaccess_tck);
1804 COMMAND_HANDLER(dap_apsel_command)
1806 struct target *target = get_current_target(CMD_CTX);
1807 struct arm *arm = target_to_arm(target);
1808 struct adiv5_dap *dap = arm->dap;
1810 uint32_t apsel, apid;
1818 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1819 /* AP address is in bits 31:24 of DP_SELECT */
1821 return ERROR_INVALID_ARGUMENTS;
1824 return ERROR_COMMAND_SYNTAX_ERROR;
1827 dap_ap_select(dap, apsel);
1828 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1829 retval = dap_run(dap);
1830 if (retval != ERROR_OK)
1833 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1839 COMMAND_HANDLER(dap_apid_command)
1841 struct target *target = get_current_target(CMD_CTX);
1842 struct arm *arm = target_to_arm(target);
1843 struct adiv5_dap *dap = arm->dap;
1845 uint32_t apsel, apselsave, apid;
1848 apselsave = dap->apsel;
1854 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1855 /* AP address is in bits 31:24 of DP_SELECT */
1857 return ERROR_INVALID_ARGUMENTS;
1860 return ERROR_COMMAND_SYNTAX_ERROR;
1863 if (apselsave != apsel)
1864 dap_ap_select(dap, apsel);
1866 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1867 retval = dap_run(dap);
1868 if (retval != ERROR_OK)
1871 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1872 if (apselsave != apsel)
1873 dap_ap_select(dap, apselsave);
1878 static const struct command_registration dap_commands[] = {
1881 .handler = handle_dap_info_command,
1882 .mode = COMMAND_EXEC,
1883 .help = "display ROM table for MEM-AP "
1884 "(default currently selected AP)",
1885 .usage = "[ap_num]",
1889 .handler = dap_apsel_command,
1890 .mode = COMMAND_EXEC,
1891 .help = "Set the currently selected AP (default 0) "
1892 "and display the result",
1893 .usage = "[ap_num]",
1897 .handler = dap_apid_command,
1898 .mode = COMMAND_EXEC,
1899 .help = "return ID register from AP "
1900 "(default currently selected AP)",
1901 .usage = "[ap_num]",
1905 .handler = dap_baseaddr_command,
1906 .mode = COMMAND_EXEC,
1907 .help = "return debug base address from MEM-AP "
1908 "(default currently selected AP)",
1909 .usage = "[ap_num]",
1912 .name = "memaccess",
1913 .handler = dap_memaccess_command,
1914 .mode = COMMAND_EXEC,
1915 .help = "set/get number of extra tck for MEM-AP memory "
1916 "bus access [0-255]",
1917 .usage = "[cycles]",
1919 COMMAND_REGISTRATION_DONE
1922 const struct command_registration dap_command_handlers[] = {
1925 .mode = COMMAND_EXEC,
1926 .help = "DAP command group",
1927 .chain = dap_commands,
1929 COMMAND_REGISTRATION_DONE
1934 * This represents the bits which must be sent out on TMS/SWDIO to
1935 * switch a DAP implemented using an SWJ-DP module into SWD mode.
1936 * These bits are stored (and transmitted) LSB-first.
1938 * See the DAP-Lite specification, section 2.2.5 for information
1939 * about making the debug link select SWD or JTAG. (Similar info
1940 * is in a few other ARM documents.)
1942 static const uint8_t jtag2swd_bitseq[] = {
1943 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1944 * putting both JTAG and SWD logic into reset state.
1946 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1947 /* Switching sequence enables SWD and disables JTAG
1948 * NOTE: bits in the DP's IDCODE may expose the need for
1949 * an old/deprecated sequence (0xb6 0xed).
1952 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1953 * putting both JTAG and SWD logic into reset state.
1955 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1959 * Put the debug link into SWD mode, if the target supports it.
1960 * The link's initial mode may be either JTAG (for example,
1961 * with SWJ-DP after reset) or SWD.
1963 * @param target Enters SWD mode (if possible).
1965 * Note that targets using the JTAG-DP do not support SWD, and that
1966 * some targets which could otherwise support it may have have been
1967 * configured to disable SWD signaling
1969 * @return ERROR_OK or else a fault code.
1971 int dap_to_swd(struct target *target)
1975 LOG_DEBUG("Enter SWD mode");
1977 /* REVISIT it's nasty to need to make calls to a "jtag"
1978 * subsystem if the link isn't in JTAG mode...
1981 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
1982 jtag2swd_bitseq, TAP_INVALID);
1983 if (retval == ERROR_OK)
1984 retval = jtag_execute_queue();
1986 /* REVISIT set up the DAP's ops vector for SWD mode. */
1992 * This represents the bits which must be sent out on TMS/SWDIO to
1993 * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1994 * These bits are stored (and transmitted) LSB-first.
1996 * These bits are stored (and transmitted) LSB-first.
1998 static const uint8_t swd2jtag_bitseq[] = {
1999 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
2000 * putting both JTAG and SWD logic into reset state.
2002 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2003 /* Switching equence disables SWD and enables JTAG
2004 * NOTE: bits in the DP's IDCODE can expose the need for
2005 * the old/deprecated sequence (0xae 0xde).
2008 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
2009 * putting both JTAG and SWD logic into reset state.
2010 * NOTE: some docs say "at least 5".
2012 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
2015 /** Put the debug link into JTAG mode, if the target supports it.
2016 * The link's initial mode may be either SWD or JTAG.
2018 * @param target Enters JTAG mode (if possible).
2020 * Note that targets implemented with SW-DP do not support JTAG, and
2021 * that some targets which could otherwise support it may have been
2022 * configured to disable JTAG signaling
2024 * @return ERROR_OK or else a fault code.
2026 int dap_to_jtag(struct target *target)
2030 LOG_DEBUG("Enter JTAG mode");
2032 /* REVISIT it's nasty to need to make calls to a "jtag"
2033 * subsystem if the link isn't in JTAG mode...
2036 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
2037 swd2jtag_bitseq, TAP_RESET);
2038 if (retval == ERROR_OK)
2039 retval = jtag_execute_queue();
2041 /* REVISIT set up the DAP's ops vector for JTAG mode. */