1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focusses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction piplining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
76 #include <helper/jep106.h>
77 #include <helper/time_support.h>
78 #include <helper/list.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
99 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
102 if (csw != ap->csw_value) {
103 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
104 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
105 if (retval != ERROR_OK)
112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
114 if (tar != ap->tar_value ||
115 (ap->csw_value & CSW_ADDRINC_MASK)) {
116 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
117 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
118 if (retval != ERROR_OK)
126 * Queue transactions setting up transfer parameters for the
127 * currently selected MEM-AP.
129 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
130 * initiate data reads or writes using memory or peripheral addresses.
131 * If the CSW is configured for it, the TAR may be automatically
132 * incremented after each transfer.
134 * @param ap The MEM-AP.
135 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
136 * matches the cached value, the register is not changed.
137 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
138 * matches the cached address, the register is not changed.
140 * @return ERROR_OK if the transaction was properly queued, else a fault code.
142 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
145 retval = mem_ap_setup_csw(ap, csw);
146 if (retval != ERROR_OK)
148 retval = mem_ap_setup_tar(ap, tar);
149 if (retval != ERROR_OK)
155 * Asynchronous (queued) read of a word from memory or a system register.
157 * @param ap The MEM-AP to access.
158 * @param address Address of the 32-bit word to read; it must be
159 * readable by the currently selected MEM-AP.
160 * @param value points to where the word will be stored when the
161 * transaction queue is flushed (assuming no errors).
163 * @return ERROR_OK for success. Otherwise a fault code.
165 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
170 /* Use banked addressing (REG_BDx) to avoid some link traffic
171 * (updating TAR) when reading several consecutive addresses.
173 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
174 address & 0xFFFFFFF0);
175 if (retval != ERROR_OK)
178 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
182 * Synchronous read of a word from memory or a system register.
183 * As a side effect, this flushes any queued transactions.
185 * @param ap The MEM-AP to access.
186 * @param address Address of the 32-bit word to read; it must be
187 * readable by the currently selected MEM-AP.
188 * @param value points to where the result will be stored.
190 * @return ERROR_OK for success; *value holds the result.
191 * Otherwise a fault code.
193 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
198 retval = mem_ap_read_u32(ap, address, value);
199 if (retval != ERROR_OK)
202 return dap_run(ap->dap);
206 * Asynchronous (queued) write of a word to memory or a system register.
208 * @param ap The MEM-AP to access.
209 * @param address Address to be written; it must be writable by
210 * the currently selected MEM-AP.
211 * @param value Word that will be written to the address when transaction
212 * queue is flushed (assuming no errors).
214 * @return ERROR_OK for success. Otherwise a fault code.
216 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
221 /* Use banked addressing (REG_BDx) to avoid some link traffic
222 * (updating TAR) when writing several consecutive addresses.
224 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
225 address & 0xFFFFFFF0);
226 if (retval != ERROR_OK)
229 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
234 * Synchronous write of a word to memory or a system register.
235 * As a side effect, this flushes any queued transactions.
237 * @param ap The MEM-AP to access.
238 * @param address Address to be written; it must be writable by
239 * the currently selected MEM-AP.
240 * @param value Word that will be written.
242 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
244 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
247 int retval = mem_ap_write_u32(ap, address, value);
249 if (retval != ERROR_OK)
252 return dap_run(ap->dap);
256 * Synchronous write of a block of memory, using a specific access size.
258 * @param ap The MEM-AP to access.
259 * @param buffer The data buffer to write. No particular alignment is assumed.
260 * @param size Which access size to use, in bytes. 1, 2 or 4.
261 * @param count The number of writes to do (in size units, not bytes).
262 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
263 * @param addrinc Whether the target address should be increased for each write or not. This
264 * should normally be true, except when writing to e.g. a FIFO.
265 * @return ERROR_OK on success, otherwise an error code.
267 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
268 uint32_t address, bool addrinc)
270 struct adiv5_dap *dap = ap->dap;
271 size_t nbytes = size * count;
272 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
277 /* TI BE-32 Quirks mode:
278 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
279 * size write address bytes written in order
280 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
281 * 2 TAR ^ 2 (val >> 8), (val)
283 * For example, if you attempt to write a single byte to address 0, the processor
284 * will actually write a byte to address 3.
286 * To make writes of size < 4 work as expected, we xor a value with the address before
287 * setting the TAP, and we set the TAP after every transfer rather then relying on
288 * address increment. */
291 csw_size = CSW_32BIT;
293 } else if (size == 2) {
294 csw_size = CSW_16BIT;
295 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
296 } else if (size == 1) {
298 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
300 return ERROR_TARGET_UNALIGNED_ACCESS;
303 if (ap->unaligned_access_bad && (address % size != 0))
304 return ERROR_TARGET_UNALIGNED_ACCESS;
306 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
307 if (retval != ERROR_OK)
311 uint32_t this_size = size;
313 /* Select packed transfer if possible */
314 if (addrinc && ap->packed_transfers && nbytes >= 4
315 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
317 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
319 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
322 if (retval != ERROR_OK)
325 /* How many source bytes each transfer will consume, and their location in the DRW,
326 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
327 uint32_t outvalue = 0;
328 if (dap->ti_be_32_quirks) {
331 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
332 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
333 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
334 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
337 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
338 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
341 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
347 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
348 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
351 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
354 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
360 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
361 if (retval != ERROR_OK)
364 /* Rewrite TAR if it wrapped or we're xoring addresses */
365 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
366 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
367 if (retval != ERROR_OK)
372 /* REVISIT: Might want to have a queued version of this function that does not run. */
373 if (retval == ERROR_OK)
374 retval = dap_run(dap);
376 if (retval != ERROR_OK) {
378 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
379 && dap_run(dap) == ERROR_OK)
380 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
382 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
389 * Synchronous read of a block of memory, using a specific access size.
391 * @param ap The MEM-AP to access.
392 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
393 * @param size Which access size to use, in bytes. 1, 2 or 4.
394 * @param count The number of reads to do (in size units, not bytes).
395 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
396 * @param addrinc Whether the target address should be increased after each read or not. This
397 * should normally be true, except when reading from e.g. a FIFO.
398 * @return ERROR_OK on success, otherwise an error code.
400 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
401 uint32_t adr, bool addrinc)
403 struct adiv5_dap *dap = ap->dap;
404 size_t nbytes = size * count;
405 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
407 uint32_t address = adr;
410 /* TI BE-32 Quirks mode:
411 * Reads on big-endian TMS570 behave strangely differently than writes.
412 * They read from the physical address requested, but with DRW byte-reversed.
413 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
414 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
418 csw_size = CSW_32BIT;
420 csw_size = CSW_16BIT;
424 return ERROR_TARGET_UNALIGNED_ACCESS;
426 if (ap->unaligned_access_bad && (adr % size != 0))
427 return ERROR_TARGET_UNALIGNED_ACCESS;
429 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
430 * over-allocation if packed transfers are going to be used, but determining the real need at
431 * this point would be messy. */
432 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
433 uint32_t *read_ptr = read_buf;
434 if (read_buf == NULL) {
435 LOG_ERROR("Failed to allocate read buffer");
439 retval = mem_ap_setup_tar(ap, address);
440 if (retval != ERROR_OK) {
445 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
446 * useful bytes it contains, and their location in the word, depends on the type of transfer
449 uint32_t this_size = size;
451 /* Select packed transfer if possible */
452 if (addrinc && ap->packed_transfers && nbytes >= 4
453 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
455 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
457 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
459 if (retval != ERROR_OK)
462 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
463 if (retval != ERROR_OK)
467 address += this_size;
469 /* Rewrite TAR if it wrapped */
470 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
471 retval = mem_ap_setup_tar(ap, address);
472 if (retval != ERROR_OK)
477 if (retval == ERROR_OK)
478 retval = dap_run(dap);
482 nbytes = size * count;
485 /* If something failed, read TAR to find out how much data was successfully read, so we can
486 * at least give the caller what we have. */
487 if (retval != ERROR_OK) {
489 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
490 && dap_run(dap) == ERROR_OK) {
491 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
492 if (nbytes > tar - address)
493 nbytes = tar - address;
495 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
500 /* Replay loop to populate caller's buffer from the correct word and byte lane */
502 uint32_t this_size = size;
504 if (addrinc && ap->packed_transfers && nbytes >= 4
505 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
509 if (dap->ti_be_32_quirks) {
512 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
513 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
516 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
519 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
524 *buffer++ = *read_ptr >> 8 * (address++ & 3);
525 *buffer++ = *read_ptr >> 8 * (address++ & 3);
528 *buffer++ = *read_ptr >> 8 * (address++ & 3);
531 *buffer++ = *read_ptr >> 8 * (address++ & 3);
543 int mem_ap_read_buf(struct adiv5_ap *ap,
544 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
546 return mem_ap_read(ap, buffer, size, count, address, true);
549 int mem_ap_write_buf(struct adiv5_ap *ap,
550 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
552 return mem_ap_write(ap, buffer, size, count, address, true);
555 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
556 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
558 return mem_ap_read(ap, buffer, size, count, address, false);
561 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
562 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
564 return mem_ap_write(ap, buffer, size, count, address, false);
567 /*--------------------------------------------------------------------------*/
570 #define DAP_POWER_DOMAIN_TIMEOUT (10)
572 /* FIXME don't import ... just initialize as
573 * part of DAP transport setup
575 extern const struct dap_ops jtag_dp_ops;
577 /*--------------------------------------------------------------------------*/
582 struct adiv5_dap *dap_init(void)
584 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
586 /* Set up with safe defaults */
587 for (i = 0; i <= 255; i++) {
588 dap->ap[i].dap = dap;
589 dap->ap[i].ap_num = i;
590 /* memaccess_tck max is 255 */
591 dap->ap[i].memaccess_tck = 255;
592 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
593 dap->ap[i].tar_autoincr_block = (1<<10);
595 INIT_LIST_HEAD(&dap->cmd_journal);
600 * Initialize a DAP. This sets up the power domains, prepares the DP
601 * for further use and activates overrun checking.
603 * @param dap The DAP being initialized.
605 int dap_dp_init(struct adiv5_dap *dap)
610 /* JTAG-DP or SWJ-DP, in JTAG mode
611 * ... for SWD mode this is patched as part
613 * FIXME: This should already be setup by the respective transport specific DAP creation.
616 dap->ops = &jtag_dp_ops;
618 dap->select = DP_SELECT_INVALID;
619 dap->last_read = NULL;
621 for (size_t i = 0; i < 30; i++) {
622 /* DP initialization */
624 retval = dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
625 if (retval == ERROR_OK)
629 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
630 if (retval != ERROR_OK)
633 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
634 if (retval != ERROR_OK)
637 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
638 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
639 if (retval != ERROR_OK)
642 /* Check that we have debug power domains activated */
643 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
644 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
645 CDBGPWRUPACK, CDBGPWRUPACK,
646 DAP_POWER_DOMAIN_TIMEOUT);
647 if (retval != ERROR_OK)
650 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
651 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
652 CSYSPWRUPACK, CSYSPWRUPACK,
653 DAP_POWER_DOMAIN_TIMEOUT);
654 if (retval != ERROR_OK)
657 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
658 if (retval != ERROR_OK)
661 /* With debug power on we can activate OVERRUN checking */
662 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
663 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
664 if (retval != ERROR_OK)
666 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
667 if (retval != ERROR_OK)
670 retval = dap_run(dap);
671 if (retval != ERROR_OK)
678 * Initialize a DAP. This sets up the power domains, prepares the DP
679 * for further use, and arranges to use AP #0 for all AP operations
680 * until dap_ap-select() changes that policy.
682 * @param ap The MEM-AP being initialized.
684 int mem_ap_init(struct adiv5_ap *ap)
686 /* check that we support packed transfers */
689 struct adiv5_dap *dap = ap->dap;
691 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
692 if (retval != ERROR_OK)
695 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
696 if (retval != ERROR_OK)
699 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
700 if (retval != ERROR_OK)
703 retval = dap_run(dap);
704 if (retval != ERROR_OK)
707 if (csw & CSW_ADDRINC_PACKED)
708 ap->packed_transfers = true;
710 ap->packed_transfers = false;
712 /* Packed transfers on TI BE-32 processors do not work correctly in
714 if (dap->ti_be_32_quirks)
715 ap->packed_transfers = false;
717 LOG_DEBUG("MEM_AP Packed Transfers: %s",
718 ap->packed_transfers ? "enabled" : "disabled");
720 /* The ARM ADI spec leaves implementation-defined whether unaligned
721 * memory accesses work, only work partially, or cause a sticky error.
722 * On TI BE-32 processors, reads seem to return garbage in some bytes
723 * and unaligned writes seem to cause a sticky error.
724 * TODO: it would be nice to have a way to detect whether unaligned
725 * operations are supported on other processors. */
726 ap->unaligned_access_bad = dap->ti_be_32_quirks;
728 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
729 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
734 /* CID interpretation -- see ARM IHI 0029B section 3
735 * and ARM IHI 0031A table 13-3.
737 static const char *class_description[16] = {
738 "Reserved", "ROM table", "Reserved", "Reserved",
739 "Reserved", "Reserved", "Reserved", "Reserved",
740 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
741 "Reserved", "OptimoDE DESS",
742 "Generic IP component", "PrimeCell or System component"
745 static bool is_dap_cid_ok(uint32_t cid)
747 return (cid & 0xffff0fff) == 0xb105000d;
751 * This function checks the ID for each access port to find the requested Access Port type
753 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
757 /* Maximum AP number is 255 since the SELECT register is 8 bits */
758 for (ap_num = 0; ap_num <= 255; ap_num++) {
760 /* read the IDR register of the Access Port */
763 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
764 if (retval != ERROR_OK)
767 retval = dap_run(dap);
771 * 27-24 : JEDEC bank (0x4 for ARM)
772 * 23-17 : JEDEC code (0x3B for ARM)
773 * 16-13 : Class (0b1000=Mem-AP)
775 * 7-4 : AP Variant (non-zero for JTAG-AP)
776 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
779 /* Reading register for a non-existant AP should not cause an error,
780 * but just to be sure, try to continue searching if an error does happen.
782 if ((retval == ERROR_OK) && /* Register read success */
783 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
784 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
786 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
787 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
788 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
789 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
790 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
793 *ap_out = &dap->ap[ap_num];
798 LOG_DEBUG("No %s found",
799 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
800 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
801 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
802 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
806 int dap_get_debugbase(struct adiv5_ap *ap,
807 uint32_t *dbgbase, uint32_t *apid)
809 struct adiv5_dap *dap = ap->dap;
812 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
813 if (retval != ERROR_OK)
815 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
816 if (retval != ERROR_OK)
818 retval = dap_run(dap);
819 if (retval != ERROR_OK)
825 int dap_lookup_cs_component(struct adiv5_ap *ap,
826 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
828 uint32_t romentry, entry_offset = 0, component_base, devtype;
834 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
835 entry_offset, &romentry);
836 if (retval != ERROR_OK)
839 component_base = (dbgbase & 0xFFFFF000)
840 + (romentry & 0xFFFFF000);
842 if (romentry & 0x1) {
844 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
845 if (retval != ERROR_OK) {
846 LOG_ERROR("Can't read component with base address 0x%" PRIx32
847 ", the corresponding core might be turned off", component_base);
850 if (((c_cid1 >> 4) & 0x0f) == 1) {
851 retval = dap_lookup_cs_component(ap, component_base,
853 if (retval == ERROR_OK)
855 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
859 retval = mem_ap_read_atomic_u32(ap,
860 (component_base & 0xfffff000) | 0xfcc,
862 if (retval != ERROR_OK)
864 if ((devtype & 0xff) == type) {
866 *addr = component_base;
873 } while (romentry > 0);
876 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
881 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
883 assert((component_base & 0xFFF) == 0);
884 assert(ap != NULL && cid != NULL && pid != NULL);
886 uint32_t cid0, cid1, cid2, cid3;
887 uint32_t pid0, pid1, pid2, pid3, pid4;
890 /* IDs are in last 4K section */
891 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
892 if (retval != ERROR_OK)
894 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
895 if (retval != ERROR_OK)
897 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
898 if (retval != ERROR_OK)
900 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
901 if (retval != ERROR_OK)
903 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
904 if (retval != ERROR_OK)
906 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
907 if (retval != ERROR_OK)
909 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
910 if (retval != ERROR_OK)
912 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
913 if (retval != ERROR_OK)
915 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
916 if (retval != ERROR_OK)
919 retval = dap_run(ap->dap);
920 if (retval != ERROR_OK)
923 *cid = (cid3 & 0xff) << 24
924 | (cid2 & 0xff) << 16
927 *pid = (uint64_t)(pid4 & 0xff) << 32
928 | (pid3 & 0xff) << 24
929 | (pid2 & 0xff) << 16
936 /* The designer identity code is encoded as:
937 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
938 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
939 * a legacy ASCII Identity Code.
940 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
941 * JEP106 is a standard available from jedec.org
944 /* Part number interpretations are from Cortex
945 * core specs, the CoreSight components TRM
946 * (ARM DDI 0314H), CoreSight System Design
947 * Guide (ARM DGI 0012D) and ETM specs; also
948 * from chip observation (e.g. TI SDTI).
951 /* The legacy code only used the part number field to identify CoreSight peripherals.
952 * This meant that the same part number from two different manufacturers looked the same.
953 * It is desirable for all future additions to identify with both part number and JEP106.
954 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
957 #define ANY_ID 0x1000
961 static const struct {
962 uint16_t designer_id;
967 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
968 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
969 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
970 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
971 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
972 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
973 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
974 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
975 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
976 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
977 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
978 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
979 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
980 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
981 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
982 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
983 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
984 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
985 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
986 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
987 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
988 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
989 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
990 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
991 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
992 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
993 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
994 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
995 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
996 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
997 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
998 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
999 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1000 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1001 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1002 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1003 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1004 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1005 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1006 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1007 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1008 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1009 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1010 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1011 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1012 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1013 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1014 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1015 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1016 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1017 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1018 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1019 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1020 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1021 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1022 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1023 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1024 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1025 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1026 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1027 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1028 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitoring Unit)", },
1029 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1030 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1031 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1032 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1033 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1034 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1035 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1036 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1037 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1038 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1039 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1040 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1041 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1042 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1043 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1044 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1045 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1046 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1047 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1048 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1049 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1050 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1051 /* legacy comment: 0x113: what? */
1052 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1053 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1056 static int dap_rom_display(struct command_context *cmd_ctx,
1057 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1065 command_print(cmd_ctx, "\tTables too deep");
1070 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1072 uint32_t base_addr = dbgbase & 0xFFFFF000;
1073 command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1075 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1076 if (retval != ERROR_OK) {
1077 command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
1078 return ERROR_OK; /* Don't abort recursion */
1081 if (!is_dap_cid_ok(cid)) {
1082 command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
1083 return ERROR_OK; /* Don't abort recursion */
1086 /* component may take multiple 4K pages */
1087 uint32_t size = (pid >> 36) & 0xf;
1089 command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1091 command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1093 uint8_t class = (cid >> 12) & 0xf;
1094 uint16_t part_num = pid & 0xfff;
1095 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1097 if (designer_id & 0x80) {
1099 command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1100 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1102 /* Legacy ASCII ID, clear invalid bits */
1103 designer_id &= 0x7f;
1104 command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1105 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1108 /* default values to be overwritten upon finding a match */
1109 const char *type = "Unrecognized";
1110 const char *full = "";
1112 /* search dap_partnums[] array for a match */
1113 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1115 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1118 if (dap_partnums[entry].part_num != part_num)
1121 type = dap_partnums[entry].type;
1122 full = dap_partnums[entry].full;
1126 command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1127 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1129 if (class == 1) { /* ROM Table */
1131 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1132 if (retval != ERROR_OK)
1136 command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
1138 command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1140 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1141 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1143 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1144 if (retval != ERROR_OK)
1146 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1147 tabs, entry_offset, romentry);
1148 if (romentry & 0x01) {
1150 retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1151 if (retval != ERROR_OK)
1153 } else if (romentry != 0) {
1154 command_print(cmd_ctx, "\t\tComponent not present");
1156 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1160 } else if (class == 9) { /* CoreSight component */
1161 const char *major = "Reserved", *subtype = "Reserved";
1164 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1165 if (retval != ERROR_OK)
1167 unsigned minor = (devtype >> 4) & 0x0f;
1168 switch (devtype & 0x0f) {
1170 major = "Miscellaneous";
1176 subtype = "Validation component";
1181 major = "Trace Sink";
1198 major = "Trace Link";
1204 subtype = "Funnel, router";
1210 subtype = "FIFO, buffer";
1215 major = "Trace Source";
1221 subtype = "Processor";
1227 subtype = "Engine/Coprocessor";
1233 subtype = "Software";
1238 major = "Debug Control";
1244 subtype = "Trigger Matrix";
1247 subtype = "Debug Auth";
1250 subtype = "Power Requestor";
1255 major = "Debug Logic";
1261 subtype = "Processor";
1267 subtype = "Engine/Coprocessor";
1278 major = "Perfomance Monitor";
1284 subtype = "Processor";
1290 subtype = "Engine/Coprocessor";
1301 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1302 (uint8_t)(devtype & 0xff),
1304 /* REVISIT also show 0xfc8 DevId */
1310 static int dap_info_command(struct command_context *cmd_ctx,
1311 struct adiv5_ap *ap)
1314 uint32_t dbgbase, apid;
1317 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1318 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1319 if (retval != ERROR_OK)
1322 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1324 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1328 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1329 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1330 command_print(cmd_ctx, "\tType is JTAG-AP");
1332 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1333 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1335 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1336 command_print(cmd_ctx, "\tType is MEM-AP APB");
1338 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1339 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1342 command_print(cmd_ctx, "\tUnknown AP type");
1346 /* NOTE: a MEM-AP may have a single CoreSight component that's
1347 * not a ROM table ... or have no such components at all.
1349 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1351 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1353 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1354 command_print(cmd_ctx, "\tNo ROM table present");
1357 command_print(cmd_ctx, "\tValid ROM table present");
1359 command_print(cmd_ctx, "\tROM table in legacy format");
1361 dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
1368 int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi)
1370 struct adiv5_private_config *pc;
1375 /* check if argv[0] is for us */
1376 arg = Jim_GetString(goi->argv[0], NULL);
1377 if (strcmp(arg, "-ap-num"))
1378 return JIM_CONTINUE;
1380 e = Jim_GetOpt_String(goi, &arg, NULL);
1384 if (goi->argc == 0) {
1385 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-ap-num ?ap-number? ...");
1389 e = Jim_GetOpt_Wide(goi, &ap_num);
1393 if (target->private_config == NULL) {
1394 pc = calloc(1, sizeof(struct adiv5_private_config));
1395 target->private_config = pc;
1396 pc->ap_num = ap_num;
1403 COMMAND_HANDLER(handle_dap_info_command)
1405 struct target *target = get_current_target(CMD_CTX);
1406 struct arm *arm = target_to_arm(target);
1407 struct adiv5_dap *dap = arm->dap;
1415 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1417 return ERROR_COMMAND_SYNTAX_ERROR;
1420 return ERROR_COMMAND_SYNTAX_ERROR;
1423 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1426 COMMAND_HANDLER(dap_baseaddr_command)
1428 struct target *target = get_current_target(CMD_CTX);
1429 struct arm *arm = target_to_arm(target);
1430 struct adiv5_dap *dap = arm->dap;
1432 uint32_t apsel, baseaddr;
1440 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1441 /* AP address is in bits 31:24 of DP_SELECT */
1443 return ERROR_COMMAND_SYNTAX_ERROR;
1446 return ERROR_COMMAND_SYNTAX_ERROR;
1449 /* NOTE: assumes we're talking to a MEM-AP, which
1450 * has a base address. There are other kinds of AP,
1451 * though they're not common for now. This should
1452 * use the ID register to verify it's a MEM-AP.
1454 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1455 if (retval != ERROR_OK)
1457 retval = dap_run(dap);
1458 if (retval != ERROR_OK)
1461 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1466 COMMAND_HANDLER(dap_memaccess_command)
1468 struct target *target = get_current_target(CMD_CTX);
1469 struct arm *arm = target_to_arm(target);
1470 struct adiv5_dap *dap = arm->dap;
1472 uint32_t memaccess_tck;
1476 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1479 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1482 return ERROR_COMMAND_SYNTAX_ERROR;
1484 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1486 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1487 dap->ap[dap->apsel].memaccess_tck);
1492 COMMAND_HANDLER(dap_apsel_command)
1494 struct target *target = get_current_target(CMD_CTX);
1495 struct arm *arm = target_to_arm(target);
1496 struct adiv5_dap *dap = arm->dap;
1498 uint32_t apsel, apid;
1506 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1507 /* AP address is in bits 31:24 of DP_SELECT */
1509 return ERROR_COMMAND_SYNTAX_ERROR;
1512 return ERROR_COMMAND_SYNTAX_ERROR;
1517 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1518 if (retval != ERROR_OK)
1520 retval = dap_run(dap);
1521 if (retval != ERROR_OK)
1524 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1530 COMMAND_HANDLER(dap_apcsw_command)
1532 struct target *target = get_current_target(CMD_CTX);
1533 struct arm *arm = target_to_arm(target);
1534 struct adiv5_dap *dap = arm->dap;
1536 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1540 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1541 (dap->apsel), apcsw);
1544 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1545 /* AP address is in bits 31:24 of DP_SELECT */
1547 return ERROR_COMMAND_SYNTAX_ERROR;
1551 apcsw &= ~CSW_SPROT;
1554 return ERROR_COMMAND_SYNTAX_ERROR;
1556 dap->ap[dap->apsel].csw_default = apcsw;
1563 COMMAND_HANDLER(dap_apid_command)
1565 struct target *target = get_current_target(CMD_CTX);
1566 struct arm *arm = target_to_arm(target);
1567 struct adiv5_dap *dap = arm->dap;
1569 uint32_t apsel, apid;
1577 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1578 /* AP address is in bits 31:24 of DP_SELECT */
1580 return ERROR_COMMAND_SYNTAX_ERROR;
1583 return ERROR_COMMAND_SYNTAX_ERROR;
1586 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1587 if (retval != ERROR_OK)
1589 retval = dap_run(dap);
1590 if (retval != ERROR_OK)
1593 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1598 COMMAND_HANDLER(dap_apreg_command)
1600 struct target *target = get_current_target(CMD_CTX);
1601 struct arm *arm = target_to_arm(target);
1602 struct adiv5_dap *dap = arm->dap;
1604 uint32_t apsel, reg, value;
1607 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1608 return ERROR_COMMAND_SYNTAX_ERROR;
1610 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1611 /* AP address is in bits 31:24 of DP_SELECT */
1613 return ERROR_COMMAND_SYNTAX_ERROR;
1615 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1616 if (reg >= 256 || (reg & 3))
1617 return ERROR_COMMAND_SYNTAX_ERROR;
1619 if (CMD_ARGC == 3) {
1620 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1621 retval = dap_queue_ap_write(dap_ap(dap, apsel), reg, value);
1623 retval = dap_queue_ap_read(dap_ap(dap, apsel), reg, &value);
1625 if (retval == ERROR_OK)
1626 retval = dap_run(dap);
1628 if (retval != ERROR_OK)
1632 command_print(CMD_CTX, "0x%08" PRIx32, value);
1637 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1639 struct target *target = get_current_target(CMD_CTX);
1640 struct arm *arm = target_to_arm(target);
1641 struct adiv5_dap *dap = arm->dap;
1643 uint32_t enable = dap->ti_be_32_quirks;
1649 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1651 return ERROR_COMMAND_SYNTAX_ERROR;
1654 return ERROR_COMMAND_SYNTAX_ERROR;
1656 dap->ti_be_32_quirks = enable;
1657 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1658 enable ? "enabled" : "disabled");
1663 static const struct command_registration dap_commands[] = {
1666 .handler = handle_dap_info_command,
1667 .mode = COMMAND_EXEC,
1668 .help = "display ROM table for MEM-AP "
1669 "(default currently selected AP)",
1670 .usage = "[ap_num]",
1674 .handler = dap_apsel_command,
1675 .mode = COMMAND_EXEC,
1676 .help = "Set the currently selected AP (default 0) "
1677 "and display the result",
1678 .usage = "[ap_num]",
1682 .handler = dap_apcsw_command,
1683 .mode = COMMAND_EXEC,
1684 .help = "Set csw access bit ",
1690 .handler = dap_apid_command,
1691 .mode = COMMAND_EXEC,
1692 .help = "return ID register from AP "
1693 "(default currently selected AP)",
1694 .usage = "[ap_num]",
1698 .handler = dap_apreg_command,
1699 .mode = COMMAND_EXEC,
1700 .help = "read/write a register from AP "
1701 "(reg is byte address of a word register, like 0 4 8...)",
1702 .usage = "ap_num reg [value]",
1706 .handler = dap_baseaddr_command,
1707 .mode = COMMAND_EXEC,
1708 .help = "return debug base address from MEM-AP "
1709 "(default currently selected AP)",
1710 .usage = "[ap_num]",
1713 .name = "memaccess",
1714 .handler = dap_memaccess_command,
1715 .mode = COMMAND_EXEC,
1716 .help = "set/get number of extra tck for MEM-AP memory "
1717 "bus access [0-255]",
1718 .usage = "[cycles]",
1721 .name = "ti_be_32_quirks",
1722 .handler = dap_ti_be_32_quirks_command,
1723 .mode = COMMAND_CONFIG,
1724 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1725 .usage = "[enable]",
1727 COMMAND_REGISTRATION_DONE
1730 const struct command_registration dap_command_handlers[] = {
1733 .mode = COMMAND_EXEC,
1734 .help = "DAP command group",
1736 .chain = dap_commands,
1738 COMMAND_REGISTRATION_DONE